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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_msk.c
blobb0e06c59b26f40c7f5436fbe685e6d4edcb6c73f
1 /* $NetBSD: if_msk.c,v 1.30 2009/12/24 18:27:31 christos Exp $ */
2 /* $OpenBSD: if_msk.c,v 1.42 2007/01/17 02:43:02 krw Exp $ */
3
4 /*
5 * Copyright (c) 1997, 1998, 1999, 2000
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
36 */
37
38 /*
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
40 *
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
44 *
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.30 2009/12/24 18:27:31 christos Exp $");
56
57 #include "bpfilter.h"
58 #include "rnd.h"
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/sockio.h>
63 #include <sys/mbuf.h>
64 #include <sys/malloc.h>
65 #include <sys/mutex.h>
66 #include <sys/kernel.h>
67 #include <sys/socket.h>
68 #include <sys/device.h>
69 #include <sys/queue.h>
70 #include <sys/callout.h>
71 #include <sys/sysctl.h>
72 #include <sys/endian.h>
73 #ifdef __NetBSD__
74 #define letoh16 htole16
75 #define letoh32 htole32
76 #endif
77
78 #include <net/if.h>
79 #include <net/if_dl.h>
80 #include <net/if_types.h>
81
82 #include <net/if_media.h>
83
84 #if NBPFILTER > 0
85 #include <net/bpf.h>
86 #endif
87 #if NRND > 0
88 #include <sys/rnd.h>
89 #endif
90
91 #include <dev/mii/mii.h>
92 #include <dev/mii/miivar.h>
93 #include <dev/mii/brgphyreg.h>
94
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
97 #include <dev/pci/pcidevs.h>
98
99 #include <dev/pci/if_skreg.h>
100 #include <dev/pci/if_mskvar.h>
101
102 int mskc_probe(device_t, cfdata_t, void *);
103 void mskc_attach(device_t, device_t, void *);
104 static bool mskc_suspend(device_t, pmf_qual_t);
105 static bool mskc_resume(device_t, pmf_qual_t);
106 int msk_probe(device_t, cfdata_t, void *);
107 void msk_attach(device_t, device_t, void *);
108 int mskcprint(void *, const char *);
109 int msk_intr(void *);
110 void msk_intr_yukon(struct sk_if_softc *);
111 __inline int msk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
112 void msk_rxeof(struct sk_if_softc *, u_int16_t, u_int32_t);
113 void msk_txeof(struct sk_if_softc *, int);
114 int msk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *);
115 void msk_start(struct ifnet *);
116 int msk_ioctl(struct ifnet *, u_long, void *);
117 int msk_init(struct ifnet *);
118 void msk_init_yukon(struct sk_if_softc *);
119 void msk_stop(struct ifnet *, int);
120 void msk_watchdog(struct ifnet *);
121 void msk_reset(struct sk_softc *);
122 int msk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t);
123 int msk_alloc_jumbo_mem(struct sk_if_softc *);
124 void *msk_jalloc(struct sk_if_softc *);
125 void msk_jfree(struct mbuf *, void *, size_t, void *);
126 int msk_init_rx_ring(struct sk_if_softc *);
127 int msk_init_tx_ring(struct sk_if_softc *);
128
129 void msk_update_int_mod(struct sk_softc *, int);
130
131 int msk_miibus_readreg(device_t, int, int);
132 void msk_miibus_writereg(device_t, int, int, int);
133 void msk_miibus_statchg(device_t);
134
135 void msk_setfilt(struct sk_if_softc *, void *, int);
136 void msk_setmulti(struct sk_if_softc *);
137 void msk_setpromisc(struct sk_if_softc *);
138 void msk_tick(void *);
139
140 /* #define MSK_DEBUG 1 */
141 #ifdef MSK_DEBUG
142 #define DPRINTF(x) if (mskdebug) printf x
143 #define DPRINTFN(n,x) if (mskdebug >= (n)) printf x
144 int mskdebug = MSK_DEBUG;
145
146 void msk_dump_txdesc(struct msk_tx_desc *, int);
147 void msk_dump_mbuf(struct mbuf *);
148 void msk_dump_bytes(const char *, int);
149 #else
150 #define DPRINTF(x)
151 #define DPRINTFN(n,x)
152 #endif
153
154 static int msk_sysctl_handler(SYSCTLFN_PROTO);
155 static int msk_root_num;
156
157 /* supported device vendors */
158 static const struct msk_product {
159 pci_vendor_id_t msk_vendor;
160 pci_product_id_t msk_product;
161 } msk_products[] = {
162 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE550SX },
163 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560SX },
164 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T },
165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_1 },
166 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C032 },
167 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C033 },
168 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C034 },
169 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C036 },
170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C042 },
171 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_C055 },
172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8035 },
173 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8036 },
174 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8038 },
175 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8039 },
176 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8050 },
177 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8052 },
178 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8053 },
179 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8055 },
180 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_8056 },
181 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021CU },
182 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8021X },
183 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022CU },
184 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8022X },
185 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061CU },
186 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8061X },
187 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062CU },
188 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKONII_8062X },
189 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9SXX },
190 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9E21 }
191 };
192
193 static inline u_int32_t
194 sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
195 {
196 return CSR_READ_4(sc, reg);
197 }
198
199 static inline u_int16_t
200 sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
201 {
202 return CSR_READ_2(sc, reg);
203 }
204
205 static inline u_int8_t
206 sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
207 {
208 return CSR_READ_1(sc, reg);
209 }
210
211 static inline void
212 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
213 {
214 CSR_WRITE_4(sc, reg, x);
215 }
216
217 static inline void
218 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
219 {
220 CSR_WRITE_2(sc, reg, x);
221 }
222
223 static inline void
224 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
225 {
226 CSR_WRITE_1(sc, reg, x);
227 }
228
229 int
230 msk_miibus_readreg(device_t dev, int phy, int reg)
231 {
232 struct sk_if_softc *sc_if = device_private(dev);
233 u_int16_t val;
234 int i;
235
236 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
237 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
238
239 for (i = 0; i < SK_TIMEOUT; i++) {
240 DELAY(1);
241 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
242 if (val & YU_SMICR_READ_VALID)
243 break;
244 }
245
246 if (i == SK_TIMEOUT) {
247 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n");
248 return (0);
249 }
250
251 DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i,
252 SK_TIMEOUT));
253
254 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
255
256 DPRINTFN(9, ("msk_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
257 phy, reg, val));
258
259 return (val);
260 }
261
262 void
263 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
264 {
265 struct sk_if_softc *sc_if = device_private(dev);
266 int i;
267
268 DPRINTFN(9, ("msk_miibus_writereg phy=%d reg=%#x val=%#x\n",
269 phy, reg, val));
270
271 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
272 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
273 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
274
275 for (i = 0; i < SK_TIMEOUT; i++) {
276 DELAY(1);
277 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
278 break;
279 }
280
281 if (i == SK_TIMEOUT)
282 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n");
283 }
284
285 void
286 msk_miibus_statchg(device_t dev)
287 {
288 struct sk_if_softc *sc_if = device_private(dev);
289 struct mii_data *mii = &sc_if->sk_mii;
290 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
291 int gpcr;
292
293 gpcr = SK_YU_READ_2(sc_if, YUKON_GPCR);
294 gpcr &= (YU_GPCR_TXEN | YU_GPCR_RXEN);
295
296 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
297 /* Set speed. */
298 gpcr |= YU_GPCR_SPEED_DIS;
299 switch (IFM_SUBTYPE(mii->mii_media_active)) {
300 case IFM_1000_SX:
301 case IFM_1000_LX:
302 case IFM_1000_CX:
303 case IFM_1000_T:
304 gpcr |= (YU_GPCR_GIG | YU_GPCR_SPEED);
305 break;
306 case IFM_100_TX:
307 gpcr |= YU_GPCR_SPEED;
308 break;
309 }
310
311 /* Set duplex. */
312 gpcr |= YU_GPCR_DPLX_DIS;
313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
314 gpcr |= YU_GPCR_DUPLEX;
315
316 /* Disable flow control. */
317 gpcr |= YU_GPCR_FCTL_DIS;
318 gpcr |= (YU_GPCR_FCTL_TX_DIS | YU_GPCR_FCTL_RX_DIS);
319 }
320
321 SK_YU_WRITE_2(sc_if, YUKON_GPCR, gpcr);
322
323 DPRINTFN(9, ("msk_miibus_statchg: gpcr=%x\n",
324 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
325 }
326
327 #define HASH_BITS 6
328
329 void
330 msk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot)
331 {
332 char *addr = addrv;
333 int base = XM_RXFILT_ENTRY(slot);
334
335 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
336 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
337 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
338 }
339
340 void
341 msk_setmulti(struct sk_if_softc *sc_if)
342 {
343 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if;
344 u_int32_t hashes[2] = { 0, 0 };
345 int h;
346 struct ethercom *ec = &sc_if->sk_ethercom;
347 struct ether_multi *enm;
348 struct ether_multistep step;
349 u_int16_t reg;
350
351 /* First, zot all the existing filters. */
352 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
353 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
354 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
355 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
356
357
358 /* Now program new ones. */
359 reg = SK_YU_READ_2(sc_if, YUKON_RCR);
360 reg |= YU_RCR_UFLEN;
361 allmulti:
362 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 if ((ifp->if_flags & IFF_PROMISC) != 0)
364 reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
365 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
366 hashes[0] = 0xFFFFFFFF;
367 hashes[1] = 0xFFFFFFFF;
368 }
369 } else {
370 /* First find the tail of the list. */
371 ETHER_FIRST_MULTI(step, ec, enm);
372 while (enm != NULL) {
373 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
374 ETHER_ADDR_LEN)) {
375 ifp->if_flags |= IFF_ALLMULTI;
376 goto allmulti;
377 }
378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
379 ((1 << HASH_BITS) - 1);
380 if (h < 32)
381 hashes[0] |= (1 << h);
382 else
383 hashes[1] |= (1 << (h - 32));
384
385 ETHER_NEXT_MULTI(step, enm);
386 }
387 reg |= YU_RCR_MUFLEN;
388 }
389
390 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
391 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
392 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
393 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
394 SK_YU_WRITE_2(sc_if, YUKON_RCR, reg);
395 }
396
397 void
398 msk_setpromisc(struct sk_if_softc *sc_if)
399 {
400 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
401
402 if (ifp->if_flags & IFF_PROMISC)
403 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
404 YU_RCR_UFLEN | YU_RCR_MUFLEN);
405 else
406 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
407 YU_RCR_UFLEN | YU_RCR_MUFLEN);
408 }
409
410 int
411 msk_init_rx_ring(struct sk_if_softc *sc_if)
412 {
413 struct msk_chain_data *cd = &sc_if->sk_cdata;
414 struct msk_ring_data *rd = sc_if->sk_rdata;
415 int i, nexti;
416
417 memset(rd->sk_rx_ring, 0, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
418
419 for (i = 0; i < MSK_RX_RING_CNT; i++) {
420 cd->sk_rx_chain[i].sk_le = &rd->sk_rx_ring[i];
421 if (i == (MSK_RX_RING_CNT - 1))
422 nexti = 0;
423 else
424 nexti = i + 1;
425 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti];
426 }
427
428 for (i = 0; i < MSK_RX_RING_CNT; i++) {
429 if (msk_newbuf(sc_if, i, NULL,
430 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
431 aprint_error_dev(sc_if->sk_dev, "failed alloc of %dth mbuf\n", i);
432 return (ENOBUFS);
433 }
434 }
435
436 sc_if->sk_cdata.sk_rx_prod = MSK_RX_RING_CNT - 1;
437 sc_if->sk_cdata.sk_rx_cons = 0;
438
439 return (0);
440 }
441
442 int
443 msk_init_tx_ring(struct sk_if_softc *sc_if)
444 {
445 struct sk_softc *sc = sc_if->sk_softc;
446 struct msk_chain_data *cd = &sc_if->sk_cdata;
447 struct msk_ring_data *rd = sc_if->sk_rdata;
448 bus_dmamap_t dmamap;
449 struct sk_txmap_entry *entry;
450 int i, nexti;
451
452 memset(sc_if->sk_rdata->sk_tx_ring, 0,
453 sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
454
455 SIMPLEQ_INIT(&sc_if->sk_txmap_head);
456 for (i = 0; i < MSK_TX_RING_CNT; i++) {
457 cd->sk_tx_chain[i].sk_le = &rd->sk_tx_ring[i];
458 if (i == (MSK_TX_RING_CNT - 1))
459 nexti = 0;
460 else
461 nexti = i + 1;
462 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
463
464 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
465 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap))
466 return (ENOBUFS);
467
468 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
469 if (!entry) {
470 bus_dmamap_destroy(sc->sc_dmatag, dmamap);
471 return (ENOBUFS);
472 }
473 entry->dmamap = dmamap;
474 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
475 }
476
477 sc_if->sk_cdata.sk_tx_prod = 0;
478 sc_if->sk_cdata.sk_tx_cons = 0;
479 sc_if->sk_cdata.sk_tx_cnt = 0;
480
481 MSK_CDTXSYNC(sc_if, 0, MSK_TX_RING_CNT,
482 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
483
484 return (0);
485 }
486
487 int
488 msk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
489 bus_dmamap_t dmamap)
490 {
491 struct mbuf *m_new = NULL;
492 struct sk_chain *c;
493 struct msk_rx_desc *r;
494
495 if (m == NULL) {
496 void *buf = NULL;
497
498 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
499 if (m_new == NULL)
500 return (ENOBUFS);
501
502 /* Allocate the jumbo buffer */
503 buf = msk_jalloc(sc_if);
504 if (buf == NULL) {
505 m_freem(m_new);
506 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
507 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname));
508 return (ENOBUFS);
509 }
510
511 /* Attach the buffer to the mbuf */
512 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
513 MEXTADD(m_new, buf, SK_JLEN, 0, msk_jfree, sc_if);
514 } else {
515 /*
516 * We're re-using a previously allocated mbuf;
517 * be sure to re-init pointers and lengths to
518 * default values.
519 */
520 m_new = m;
521 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
522 m_new->m_data = m_new->m_ext.ext_buf;
523 }
524 m_adj(m_new, ETHER_ALIGN);
525
526 c = &sc_if->sk_cdata.sk_rx_chain[i];
527 r = c->sk_le;
528 c->sk_mbuf = m_new;
529 r->sk_addr = htole32(dmamap->dm_segs[0].ds_addr +
530 (((vaddr_t)m_new->m_data
531 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
532 r->sk_len = htole16(SK_JLEN);
533 r->sk_ctl = 0;
534 r->sk_opcode = SK_Y2_RXOPC_PACKET | SK_Y2_RXOPC_OWN;
535
536 MSK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
537
538 return (0);
539 }
540
541 /*
542 * Memory management for jumbo frames.
543 */
544
545 int
546 msk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
547 {
548 struct sk_softc *sc = sc_if->sk_softc;
549 char *ptr, *kva;
550 bus_dma_segment_t seg;
551 int i, rseg, state, error;
552 struct sk_jpool_entry *entry;
553
554 state = error = 0;
555
556 /* Grab a big chunk o' storage. */
557 if (bus_dmamem_alloc(sc->sc_dmatag, MSK_JMEM, PAGE_SIZE, 0,
558 &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
559 aprint_error(": can't alloc rx buffers");
560 return (ENOBUFS);
561 }
562
563 state = 1;
564 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, MSK_JMEM, (void **)&kva,
565 BUS_DMA_NOWAIT)) {
566 aprint_error(": can't map dma buffers (%d bytes)", MSK_JMEM);
567 error = ENOBUFS;
568 goto out;
569 }
570
571 state = 2;
572 if (bus_dmamap_create(sc->sc_dmatag, MSK_JMEM, 1, MSK_JMEM, 0,
573 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
574 aprint_error(": can't create dma map");
575 error = ENOBUFS;
576 goto out;
577 }
578
579 state = 3;
580 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
581 kva, MSK_JMEM, NULL, BUS_DMA_NOWAIT)) {
582 aprint_error(": can't load dma map");
583 error = ENOBUFS;
584 goto out;
585 }
586
587 state = 4;
588 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva;
589 DPRINTFN(1,("msk_jumbo_buf = %p\n", (void *)sc_if->sk_cdata.sk_jumbo_buf));
590
591 LIST_INIT(&sc_if->sk_jfree_listhead);
592 LIST_INIT(&sc_if->sk_jinuse_listhead);
593 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET);
594
595 /*
596 * Now divide it up into 9K pieces and save the addresses
597 * in an array.
598 */
599 ptr = sc_if->sk_cdata.sk_jumbo_buf;
600 for (i = 0; i < MSK_JSLOTS; i++) {
601 sc_if->sk_cdata.sk_jslots[i] = ptr;
602 ptr += SK_JLEN;
603 entry = malloc(sizeof(struct sk_jpool_entry),
604 M_DEVBUF, M_NOWAIT);
605 if (entry == NULL) {
606 sc_if->sk_cdata.sk_jumbo_buf = NULL;
607 aprint_error(": no memory for jumbo buffer queue!");
608 error = ENOBUFS;
609 goto out;
610 }
611 entry->slot = i;
612 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
613 entry, jpool_entries);
614 }
615 out:
616 if (error != 0) {
617 switch (state) {
618 case 4:
619 bus_dmamap_unload(sc->sc_dmatag,
620 sc_if->sk_cdata.sk_rx_jumbo_map);
621 case 3:
622 bus_dmamap_destroy(sc->sc_dmatag,
623 sc_if->sk_cdata.sk_rx_jumbo_map);
624 case 2:
625 bus_dmamem_unmap(sc->sc_dmatag, kva, MSK_JMEM);
626 case 1:
627 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
628 break;
629 default:
630 break;
631 }
632 }
633
634 return (error);
635 }
636
637 /*
638 * Allocate a jumbo buffer.
639 */
640 void *
641 msk_jalloc(struct sk_if_softc *sc_if)
642 {
643 struct sk_jpool_entry *entry;
644
645 mutex_enter(&sc_if->sk_jpool_mtx);
646 entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
647
648 if (entry == NULL) {
649 mutex_exit(&sc_if->sk_jpool_mtx);
650 return NULL;
651 }
652
653 LIST_REMOVE(entry, jpool_entries);
654 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
655 mutex_exit(&sc_if->sk_jpool_mtx);
656 return (sc_if->sk_cdata.sk_jslots[entry->slot]);
657 }
658
659 /*
660 * Release a jumbo buffer.
661 */
662 void
663 msk_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
664 {
665 struct sk_jpool_entry *entry;
666 struct sk_if_softc *sc;
667 int i;
668
669 /* Extract the softc struct pointer. */
670 sc = (struct sk_if_softc *)arg;
671
672 if (sc == NULL)
673 panic("msk_jfree: can't find softc pointer!");
674
675 /* calculate the slot this buffer belongs to */
676 i = ((vaddr_t)buf
677 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
678
679 if ((i < 0) || (i >= MSK_JSLOTS))
680 panic("msk_jfree: asked to free buffer that we don't manage!");
681
682 mutex_enter(&sc->sk_jpool_mtx);
683 entry = LIST_FIRST(&sc->sk_jinuse_listhead);
684 if (entry == NULL)
685 panic("msk_jfree: buffer not in use!");
686 entry->slot = i;
687 LIST_REMOVE(entry, jpool_entries);
688 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
689 mutex_exit(&sc->sk_jpool_mtx);
690
691 if (__predict_true(m != NULL))
692 pool_cache_put(mb_cache, m);
693 }
694
695 int
696 msk_ioctl(struct ifnet *ifp, u_long cmd, void *data)
697 {
698 struct sk_if_softc *sc_if = ifp->if_softc;
699 int s, error = 0;
700
701 s = splnet();
702
703 DPRINTFN(2, ("msk_ioctl ETHER\n"));
704 error = ether_ioctl(ifp, cmd, data);
705
706 if (error == ENETRESET) {
707 error = 0;
708 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
709 ;
710 else if (ifp->if_flags & IFF_RUNNING) {
711 /*
712 * Multicast list has changed; set the hardware
713 * filter accordingly.
714 */
715 msk_setmulti(sc_if);
716 }
717 }
718
719 splx(s);
720 return (error);
721 }
722
723 void
724 msk_update_int_mod(struct sk_softc *sc, int verbose)
725 {
726 u_int32_t imtimer_ticks;
727
728 /*
729 * Configure interrupt moderation. The moderation timer
730 * defers interrupts specified in the interrupt moderation
731 * timer mask based on the timeout specified in the interrupt
732 * moderation timer init register. Each bit in the timer
733 * register represents one tick, so to specify a timeout in
734 * microseconds, we have to multiply by the correct number of
735 * ticks-per-microsecond.
736 */
737 switch (sc->sk_type) {
738 case SK_YUKON_EC:
739 case SK_YUKON_EC_U:
740 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
741 break;
742 case SK_YUKON_FE:
743 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
744 break;
745 case SK_YUKON_XL:
746 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
747 break;
748 default:
749 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
750 }
751 if (verbose)
752 aprint_verbose_dev(sc->sk_dev,
753 "interrupt moderation is %d us\n", sc->sk_int_mod);
754 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
755 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
756 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
757 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
758 sc->sk_int_mod_pending = 0;
759 }
760
761 static int
762 msk_lookup(const struct pci_attach_args *pa)
763 {
764 const struct msk_product *pmsk;
765
766 for ( pmsk = &msk_products[0]; pmsk->msk_vendor != 0; pmsk++) {
767 if (PCI_VENDOR(pa->pa_id) == pmsk->msk_vendor &&
768 PCI_PRODUCT(pa->pa_id) == pmsk->msk_product)
769 return 1;
770 }
771 return 0;
772 }
773
774 /*
775 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
776 * IDs against our list and return a device name if we find a match.
777 */
778 int
779 mskc_probe(device_t parent, cfdata_t match, void *aux)
780 {
781 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
782
783 return msk_lookup(pa);
784 }
785
786 /*
787 * Force the GEnesis into reset, then bring it out of reset.
788 */
789 void msk_reset(struct sk_softc *sc)
790 {
791 u_int32_t imtimer_ticks, reg1;
792 int reg;
793
794 DPRINTFN(2, ("msk_reset\n"));
795
796 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
797 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
798
799 DELAY(1000);
800 CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_UNRESET);
801 DELAY(2);
802 CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
803 sk_win_write_1(sc, SK_TESTCTL1, 2);
804
805 reg1 = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1));
806 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
807 reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
808 else
809 reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
810
811 if (sc->sk_type == SK_YUKON_EC_U) {
812 uint32_t our;
813
814 CSR_WRITE_2(sc, SK_CSR, SK_CSR_WOL_ON);
815
816 /* enable all clocks. */
817 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
818 our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
819 our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST|
820 SK_Y2_REG4_ASPM_GPHY_LINK_DOWN|
821 SK_Y2_REG4_ASPM_INT_FIFO_EMPTY|
822 SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
823 /* Set all bits to 0 except bits 15..12 */
824 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
825 /* Set to default value */
826 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), 0);
827 }
828
829 /* release PHY from PowerDown/Coma mode. */
830 sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
831
832 if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
833 sk_win_write_1(sc, SK_Y2_CLKGATE,
834 SK_Y2_CLKGATE_LINK1_GATE_DIS |
835 SK_Y2_CLKGATE_LINK2_GATE_DIS |
836 SK_Y2_CLKGATE_LINK1_CORE_DIS |
837 SK_Y2_CLKGATE_LINK2_CORE_DIS |
838 SK_Y2_CLKGATE_LINK1_PCI_DIS | SK_Y2_CLKGATE_LINK2_PCI_DIS);
839 else
840 sk_win_write_1(sc, SK_Y2_CLKGATE, 0);
841
842 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
843 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET);
844 DELAY(1000);
845 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
846 CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR);
847
848 sk_win_write_1(sc, SK_TESTCTL1, 1);
849
850 DPRINTFN(2, ("msk_reset: sk_csr=%x\n", CSR_READ_1(sc, SK_CSR)));
851 DPRINTFN(2, ("msk_reset: sk_link_ctrl=%x\n",
852 CSR_READ_2(sc, SK_LINK_CTRL)));
853
854 /* Disable ASF */
855 CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
856 CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
857
858 /* Clear I2C IRQ noise */
859 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
860
861 /* Disable hardware timer */
862 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_STOP);
863 CSR_WRITE_1(sc, SK_TIMERCTL, SK_IMCTL_IRQ_CLEAR);
864
865 /* Disable descriptor polling */
866 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
867
868 /* Disable time stamps */
869 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_STOP);
870 CSR_WRITE_1(sc, SK_TSTAMP_CTL, SK_TSTAMP_IRQ_CLEAR);
871
872 /* Enable RAM interface */
873 sk_win_write_1(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
874 for (reg = SK_TO0;reg <= SK_TO11; reg++)
875 sk_win_write_1(sc, reg, 36);
876 sk_win_write_1(sc, SK_RAMCTL + (SK_WIN_LEN / 2), SK_RAMCTL_UNRESET);
877 for (reg = SK_TO0;reg <= SK_TO11; reg++)
878 sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);
879
880 /*
881 * Configure interrupt moderation. The moderation timer
882 * defers interrupts specified in the interrupt moderation
883 * timer mask based on the timeout specified in the interrupt
884 * moderation timer init register. Each bit in the timer
885 * register represents one tick, so to specify a timeout in
886 * microseconds, we have to multiply by the correct number of
887 * ticks-per-microsecond.
888 */
889 switch (sc->sk_type) {
890 case SK_YUKON_EC:
891 case SK_YUKON_EC_U:
892 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
893 break;
894 case SK_YUKON_FE:
895 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
896 break;
897 case SK_YUKON_XL:
898 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
899 break;
900 default:
901 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
902 }
903
904 /* Reset status ring. */
905 memset(sc->sk_status_ring, 0,
906 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
907 bus_dmamap_sync(sc->sc_dmatag, sc->sk_status_map, 0,
908 sc->sk_status_map->dm_mapsize, BUS_DMASYNC_PREREAD);
909 sc->sk_status_idx = 0;
910 sc->sk_status_own_idx = 0;
911
912 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_RESET);
913 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_UNRESET);
914
915 sk_win_write_2(sc, SK_STAT_BMU_LIDX, MSK_STATUS_RING_CNT - 1);
916 sk_win_write_4(sc, SK_STAT_BMU_ADDRLO,
917 sc->sk_status_map->dm_segs[0].ds_addr);
918 sk_win_write_4(sc, SK_STAT_BMU_ADDRHI,
919 (u_int64_t)sc->sk_status_map->dm_segs[0].ds_addr >> 32);
920 if ((sc->sk_workaround & SK_STAT_BMU_FIFOIWM) != 0) {
921 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, SK_STAT_BMU_TXTHIDX_MSK);
922 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x21);
923 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM, 0x07);
924 } else {
925 sk_win_write_2(sc, SK_STAT_BMU_TX_THRESH, 0x000a);
926 sk_win_write_1(sc, SK_STAT_BMU_FIFOWM, 0x10);
927 sk_win_write_1(sc, SK_STAT_BMU_FIFOIWM,
928 ((sc->sk_workaround & SK_WA_4109) != 0) ? 0x10 : 0x04);
929 sk_win_write_4(sc, SK_Y2_ISR_ITIMERINIT, 0x0190); /* 3.2us on Yukon-EC */
930 }
931
932 #if 0
933 sk_win_write_4(sc, SK_Y2_LEV_ITIMERINIT, SK_IM_USECS(100));
934 #endif
935 sk_win_write_4(sc, SK_Y2_TX_ITIMERINIT, SK_IM_USECS(1000));
936
937 sk_win_write_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_ON);
938
939 sk_win_write_1(sc, SK_Y2_LEV_ITIMERCTL, SK_IMCTL_START);
940 sk_win_write_1(sc, SK_Y2_TX_ITIMERCTL, SK_IMCTL_START);
941 sk_win_write_1(sc, SK_Y2_ISR_ITIMERCTL, SK_IMCTL_START);
942
943 msk_update_int_mod(sc, 0);
944 }
945
946 int
947 msk_probe(device_t parent, cfdata_t match, void *aux)
948 {
949 struct skc_attach_args *sa = aux;
950
951 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
952 return (0);
953
954 switch (sa->skc_type) {
955 case SK_YUKON_XL:
956 case SK_YUKON_EC_U:
957 case SK_YUKON_EC:
958 case SK_YUKON_FE:
959 return (1);
960 }
961
962 return (0);
963 }
964
965 static bool
966 msk_resume(device_t dv, pmf_qual_t qual)
967 {
968 struct sk_if_softc *sc_if = device_private(dv);
969
970 msk_init_yukon(sc_if);
971 return true;
972 }
973
974 /*
975 * Each XMAC chip is attached as a separate logical IP interface.
976 * Single port cards will have only one logical interface of course.
977 */
978 void
979 msk_attach(device_t parent, device_t self, void *aux)
980 {
981 struct sk_if_softc *sc_if = device_private(self);
982 struct sk_softc *sc = device_private(parent);
983 struct skc_attach_args *sa = aux;
984 struct ifnet *ifp;
985 void *kva;
986 bus_dma_segment_t seg;
987 int i, rseg;
988 u_int32_t chunk, val;
989
990 sc_if->sk_dev = self;
991 sc_if->sk_port = sa->skc_port;
992 sc_if->sk_softc = sc;
993 sc->sk_if[sa->skc_port] = sc_if;
994
995 DPRINTFN(2, ("begin msk_attach: port=%d\n", sc_if->sk_port));
996
997 /*
998 * Get station address for this interface. Note that
999 * dual port cards actually come with three station
1000 * addresses: one for each port, plus an extra. The
1001 * extra one is used by the SysKonnect driver software
1002 * as a 'virtual' station address for when both ports
1003 * are operating in failover mode. Currently we don't
1004 * use this extra address.
1005 */
1006 for (i = 0; i < ETHER_ADDR_LEN; i++)
1007 sc_if->sk_enaddr[i] =
1008 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
1009
1010 aprint_normal(": Ethernet address %s\n",
1011 ether_sprintf(sc_if->sk_enaddr));
1012
1013 /*
1014 * Set up RAM buffer addresses. The NIC will have a certain
1015 * amount of SRAM on it, somewhere between 512K and 2MB. We
1016 * need to divide this up a) between the transmitter and
1017 * receiver and b) between the two XMACs, if this is a
1018 * dual port NIC. Our algorithm is to divide up the memory
1019 * evenly so that everyone gets a fair share.
1020 *
1021 * Just to be contrary, Yukon2 appears to have separate memory
1022 * for each MAC.
1023 */
1024 chunk = sc->sk_ramsize - (sc->sk_ramsize + 2) / 3;
1025 val = sc->sk_rboff / sizeof(u_int64_t);
1026 sc_if->sk_rx_ramstart = val;
1027 val += (chunk / sizeof(u_int64_t));
1028 sc_if->sk_rx_ramend = val - 1;
1029 chunk = sc->sk_ramsize - chunk;
1030 sc_if->sk_tx_ramstart = val;
1031 val += (chunk / sizeof(u_int64_t));
1032 sc_if->sk_tx_ramend = val - 1;
1033
1034 DPRINTFN(2, ("msk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1035 " tx_ramstart=%#x tx_ramend=%#x\n",
1036 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1037 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1038
1039 /* Allocate the descriptor queues. */
1040 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct msk_ring_data),
1041 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1042 aprint_error(": can't alloc rx buffers\n");
1043 goto fail;
1044 }
1045 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1046 sizeof(struct msk_ring_data), &kva, BUS_DMA_NOWAIT)) {
1047 aprint_error(": can't map dma buffers (%zu bytes)\n",
1048 sizeof(struct msk_ring_data));
1049 goto fail_1;
1050 }
1051 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct msk_ring_data), 1,
1052 sizeof(struct msk_ring_data), 0, BUS_DMA_NOWAIT,
1053 &sc_if->sk_ring_map)) {
1054 aprint_error(": can't create dma map\n");
1055 goto fail_2;
1056 }
1057 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
1058 sizeof(struct msk_ring_data), NULL, BUS_DMA_NOWAIT)) {
1059 aprint_error(": can't load dma map\n");
1060 goto fail_3;
1061 }
1062 sc_if->sk_rdata = (struct msk_ring_data *)kva;
1063 memset(sc_if->sk_rdata, 0, sizeof(struct msk_ring_data));
1064
1065 ifp = &sc_if->sk_ethercom.ec_if;
1066 /* Try to allocate memory for jumbo buffers. */
1067 if (msk_alloc_jumbo_mem(sc_if)) {
1068 aprint_error(": jumbo buffer allocation failed\n");
1069 goto fail_3;
1070 }
1071 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU;
1072 if (sc->sk_type != SK_YUKON_FE)
1073 sc_if->sk_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
1074
1075 ifp->if_softc = sc_if;
1076 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1077 ifp->if_ioctl = msk_ioctl;
1078 ifp->if_start = msk_start;
1079 ifp->if_stop = msk_stop;
1080 ifp->if_init = msk_init;
1081 ifp->if_watchdog = msk_watchdog;
1082 ifp->if_baudrate = 1000000000;
1083 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1084 IFQ_SET_READY(&ifp->if_snd);
1085 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ);
1086
1087 /*
1088 * Do miibus setup.
1089 */
1090 msk_init_yukon(sc_if);
1091
1092 DPRINTFN(2, ("msk_attach: 1\n"));
1093
1094 sc_if->sk_mii.mii_ifp = ifp;
1095 sc_if->sk_mii.mii_readreg = msk_miibus_readreg;
1096 sc_if->sk_mii.mii_writereg = msk_miibus_writereg;
1097 sc_if->sk_mii.mii_statchg = msk_miibus_statchg;
1098
1099 sc_if->sk_ethercom.ec_mii = &sc_if->sk_mii;
1100 ifmedia_init(&sc_if->sk_mii.mii_media, 0,
1101 ether_mediachange, ether_mediastatus);
1102 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
1103 MII_OFFSET_ANY, MIIF_DOPAUSE|MIIF_FORCEANEG);
1104 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
1105 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n");
1106 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
1107 0, NULL);
1108 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL);
1109 } else
1110 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
1111
1112 callout_init(&sc_if->sk_tick_ch, 0);
1113 callout_setfunc(&sc_if->sk_tick_ch, msk_tick, sc_if);
1114 callout_schedule(&sc_if->sk_tick_ch, hz);
1115
1116 /*
1117 * Call MI attach routines.
1118 */
1119 if_attach(ifp);
1120 ether_ifattach(ifp, sc_if->sk_enaddr);
1121
1122 if (pmf_device_register(self, NULL, msk_resume))
1123 pmf_class_network_register(self, ifp);
1124 else
1125 aprint_error_dev(self, "couldn't establish power handler\n");
1126
1127 #if NRND > 0
1128 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev),
1129 RND_TYPE_NET, 0);
1130 #endif
1131
1132 DPRINTFN(2, ("msk_attach: end\n"));
1133 return;
1134
1135 fail_3:
1136 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1137 fail_2:
1138 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct msk_ring_data));
1139 fail_1:
1140 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1141 fail:
1142 sc->sk_if[sa->skc_port] = NULL;
1143 }
1144
1145 int
1146 mskcprint(void *aux, const char *pnp)
1147 {
1148 struct skc_attach_args *sa = aux;
1149
1150 if (pnp)
1151 aprint_normal("sk port %c at %s",
1152 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
1153 else
1154 aprint_normal(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
1155 return (UNCONF);
1156 }
1157
1158 /*
1159 * Attach the interface. Allocate softc structures, do ifmedia
1160 * setup and ethernet/BPF attach.
1161 */
1162 void
1163 mskc_attach(device_t parent, device_t self, void *aux)
1164 {
1165 struct sk_softc *sc = device_private(self);
1166 struct pci_attach_args *pa = aux;
1167 struct skc_attach_args skca;
1168 pci_chipset_tag_t pc = pa->pa_pc;
1169 pcireg_t command, memtype;
1170 pci_intr_handle_t ih;
1171 const char *intrstr = NULL;
1172 bus_size_t size;
1173 int rc, sk_nodenum;
1174 u_int8_t hw, skrs;
1175 const char *revstr = NULL;
1176 const struct sysctlnode *node;
1177 void *kva;
1178 bus_dma_segment_t seg;
1179 int rseg;
1180
1181 DPRINTFN(2, ("begin mskc_attach\n"));
1182
1183 sc->sk_dev = self;
1184 /*
1185 * Handle power management nonsense.
1186 */
1187 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
1188
1189 if (command == 0x01) {
1190 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
1191 if (command & SK_PSTATE_MASK) {
1192 u_int32_t iobase, membase, irq;
1193
1194 /* Save important PCI config data. */
1195 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
1196 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
1197 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
1198
1199 /* Reset the power state. */
1200 aprint_normal_dev(sc->sk_dev, "chip is in D%d power "
1201 "mode -- setting to D0\n",
1202 command & SK_PSTATE_MASK);
1203 command &= 0xFFFFFFFC;
1204 pci_conf_write(pc, pa->pa_tag,
1205 SK_PCI_PWRMGMTCTRL, command);
1206
1207 /* Restore PCI config data. */
1208 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase);
1209 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
1210 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
1211 }
1212 }
1213
1214 /*
1215 * Map control/status registers.
1216 */
1217
1218 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
1219 switch (memtype) {
1220 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1221 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1222 if (pci_mapreg_map(pa, SK_PCI_LOMEM,
1223 memtype, 0, &sc->sk_btag, &sc->sk_bhandle,
1224 NULL, &size) == 0) {
1225 break;
1226 }
1227 default:
1228 aprint_error(": can't map mem space\n");
1229 return;
1230 }
1231
1232 sc->sc_dmatag = pa->pa_dmat;
1233
1234 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1235 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1236
1237 /* bail out here if chip is not recognized */
1238 if (!(SK_IS_YUKON2(sc))) {
1239 aprint_error(": unknown chip type: %d\n", sc->sk_type);
1240 goto fail_1;
1241 }
1242 DPRINTFN(2, ("mskc_attach: allocate interrupt\n"));
1243
1244 /* Allocate interrupt */
1245 if (pci_intr_map(pa, &ih)) {
1246 aprint_error(": couldn't map interrupt\n");
1247 goto fail_1;
1248 }
1249
1250 intrstr = pci_intr_string(pc, ih);
1251 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, msk_intr, sc);
1252 if (sc->sk_intrhand == NULL) {
1253 aprint_error(": couldn't establish interrupt");
1254 if (intrstr != NULL)
1255 aprint_error(" at %s", intrstr);
1256 aprint_error("\n");
1257 goto fail_1;
1258 }
1259
1260 if (bus_dmamem_alloc(sc->sc_dmatag,
1261 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1262 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1263 aprint_error(": can't alloc status buffers\n");
1264 goto fail_2;
1265 }
1266
1267 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1268 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1269 &kva, BUS_DMA_NOWAIT)) {
1270 aprint_error(": can't map dma buffers (%zu bytes)\n",
1271 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1272 goto fail_3;
1273 }
1274 if (bus_dmamap_create(sc->sc_dmatag,
1275 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 1,
1276 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc), 0,
1277 BUS_DMA_NOWAIT, &sc->sk_status_map)) {
1278 aprint_error(": can't create dma map\n");
1279 goto fail_4;
1280 }
1281 if (bus_dmamap_load(sc->sc_dmatag, sc->sk_status_map, kva,
1282 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc),
1283 NULL, BUS_DMA_NOWAIT)) {
1284 aprint_error(": can't load dma map\n");
1285 goto fail_5;
1286 }
1287 sc->sk_status_ring = (struct msk_status_desc *)kva;
1288
1289
1290 sc->sk_int_mod = SK_IM_DEFAULT;
1291 sc->sk_int_mod_pending = 0;
1292
1293 /* Reset the adapter. */
1294 msk_reset(sc);
1295
1296 skrs = sk_win_read_1(sc, SK_EPROM0);
1297 if (skrs == 0x00)
1298 sc->sk_ramsize = 0x20000;
1299 else
1300 sc->sk_ramsize = skrs * (1<<12);
1301 sc->sk_rboff = SK_RBOFF_0;
1302
1303 DPRINTFN(2, ("mskc_attach: ramsize=%d (%dk), rboff=%d\n",
1304 sc->sk_ramsize, sc->sk_ramsize / 1024,
1305 sc->sk_rboff));
1306
1307 switch (sc->sk_type) {
1308 case SK_YUKON_XL:
1309 sc->sk_name = "Yukon-2 XL";
1310 break;
1311 case SK_YUKON_EC_U:
1312 sc->sk_name = "Yukon-2 EC Ultra";
1313 break;
1314 case SK_YUKON_EC:
1315 sc->sk_name = "Yukon-2 EC";
1316 break;
1317 case SK_YUKON_FE:
1318 sc->sk_name = "Yukon-2 FE";
1319 break;
1320 default:
1321 sc->sk_name = "Yukon (Unknown)";
1322 }
1323
1324 if (sc->sk_type == SK_YUKON_XL) {
1325 switch (sc->sk_rev) {
1326 case SK_YUKON_XL_REV_A0:
1327 sc->sk_workaround = 0;
1328 revstr = "A0";
1329 break;
1330 case SK_YUKON_XL_REV_A1:
1331 sc->sk_workaround = SK_WA_4109;
1332 revstr = "A1";
1333 break;
1334 case SK_YUKON_XL_REV_A2:
1335 sc->sk_workaround = SK_WA_4109;
1336 revstr = "A2";
1337 break;
1338 case SK_YUKON_XL_REV_A3:
1339 sc->sk_workaround = SK_WA_4109;
1340 revstr = "A3";
1341 break;
1342 default:
1343 sc->sk_workaround = 0;
1344 break;
1345 }
1346 }
1347
1348 if (sc->sk_type == SK_YUKON_EC) {
1349 switch (sc->sk_rev) {
1350 case SK_YUKON_EC_REV_A1:
1351 sc->sk_workaround = SK_WA_43_418 | SK_WA_4109;
1352 revstr = "A1";
1353 break;
1354 case SK_YUKON_EC_REV_A2:
1355 sc->sk_workaround = SK_WA_4109;
1356 revstr = "A2";
1357 break;
1358 case SK_YUKON_EC_REV_A3:
1359 sc->sk_workaround = SK_WA_4109;
1360 revstr = "A3";
1361 break;
1362 default:
1363 sc->sk_workaround = 0;
1364 break;
1365 }
1366 }
1367
1368 if (sc->sk_type == SK_YUKON_FE) {
1369 sc->sk_workaround = SK_WA_4109;
1370 switch (sc->sk_rev) {
1371 case SK_YUKON_FE_REV_A1:
1372 revstr = "A1";
1373 break;
1374 case SK_YUKON_FE_REV_A2:
1375 revstr = "A2";
1376 break;
1377 default:
1378 sc->sk_workaround = 0;
1379 break;
1380 }
1381 }
1382
1383 if (sc->sk_type == SK_YUKON_EC_U) {
1384 sc->sk_workaround = SK_WA_4109;
1385 switch (sc->sk_rev) {
1386 case SK_YUKON_EC_U_REV_A0:
1387 revstr = "A0";
1388 break;
1389 case SK_YUKON_EC_U_REV_A1:
1390 revstr = "A1";
1391 break;
1392 case SK_YUKON_EC_U_REV_B0:
1393 revstr = "B0";
1394 break;
1395 default:
1396 sc->sk_workaround = 0;
1397 break;
1398 }
1399 }
1400
1401 /* Announce the product name. */
1402 aprint_normal(", %s", sc->sk_name);
1403 if (revstr != NULL)
1404 aprint_normal(" rev. %s", revstr);
1405 aprint_normal(" (0x%x): %s\n", sc->sk_rev, intrstr);
1406
1407 sc->sk_macs = 1;
1408
1409 hw = sk_win_read_1(sc, SK_Y2_HWRES);
1410 if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
1411 if ((sk_win_read_1(sc, SK_Y2_CLKGATE) &
1412 SK_Y2_CLKGATE_LINK2_INACTIVE) == 0)
1413 sc->sk_macs++;
1414 }
1415
1416 skca.skc_port = SK_PORT_A;
1417 skca.skc_type = sc->sk_type;
1418 skca.skc_rev = sc->sk_rev;
1419 (void)config_found(sc->sk_dev, &skca, mskcprint);
1420
1421 if (sc->sk_macs > 1) {
1422 skca.skc_port = SK_PORT_B;
1423 skca.skc_type = sc->sk_type;
1424 skca.skc_rev = sc->sk_rev;
1425 (void)config_found(sc->sk_dev, &skca, mskcprint);
1426 }
1427
1428 /* Turn on the 'driver is loaded' LED. */
1429 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1430
1431 /* skc sysctl setup */
1432
1433 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1434 0, CTLTYPE_NODE, device_xname(sc->sk_dev),
1435 SYSCTL_DESCR("mskc per-controller controls"),
1436 NULL, 0, NULL, 0, CTL_HW, msk_root_num, CTL_CREATE,
1437 CTL_EOL)) != 0) {
1438 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n");
1439 goto fail_6;
1440 }
1441
1442 sk_nodenum = node->sysctl_num;
1443
1444 /* interrupt moderation time in usecs */
1445 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1446 CTLFLAG_READWRITE,
1447 CTLTYPE_INT, "int_mod",
1448 SYSCTL_DESCR("msk interrupt moderation timer"),
1449 msk_sysctl_handler, 0, sc,
1450 0, CTL_HW, msk_root_num, sk_nodenum, CTL_CREATE,
1451 CTL_EOL)) != 0) {
1452 aprint_normal_dev(sc->sk_dev, "couldn't create int_mod sysctl node\n");
1453 goto fail_6;
1454 }
1455
1456 if (!pmf_device_register(self, mskc_suspend, mskc_resume))
1457 aprint_error_dev(self, "couldn't establish power handler\n");
1458
1459 return;
1460
1461 fail_6:
1462 bus_dmamap_unload(sc->sc_dmatag, sc->sk_status_map);
1463 fail_5:
1464 bus_dmamap_destroy(sc->sc_dmatag, sc->sk_status_map);
1465 fail_4:
1466 bus_dmamem_unmap(sc->sc_dmatag, kva,
1467 MSK_STATUS_RING_CNT * sizeof(struct msk_status_desc));
1468 fail_3:
1469 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1470 fail_2:
1471 pci_intr_disestablish(pc, sc->sk_intrhand);
1472 fail_1:
1473 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size);
1474 }
1475
1476 int
1477 msk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
1478 {
1479 struct sk_softc *sc = sc_if->sk_softc;
1480 struct msk_tx_desc *f = NULL;
1481 u_int32_t frag, cur;
1482 int i;
1483 struct sk_txmap_entry *entry;
1484 bus_dmamap_t txmap;
1485
1486 DPRINTFN(2, ("msk_encap\n"));
1487
1488 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
1489 if (entry == NULL) {
1490 DPRINTFN(2, ("msk_encap: no txmap available\n"));
1491 return (ENOBUFS);
1492 }
1493 txmap = entry->dmamap;
1494
1495 cur = frag = *txidx;
1496
1497 #ifdef MSK_DEBUG
1498 if (mskdebug >= 2)
1499 msk_dump_mbuf(m_head);
1500 #endif
1501
1502 /*
1503 * Start packing the mbufs in this chain into
1504 * the fragment pointers. Stop when we run out
1505 * of fragments or hit the end of the mbuf chain.
1506 */
1507 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1508 BUS_DMA_NOWAIT)) {
1509 DPRINTFN(2, ("msk_encap: dmamap failed\n"));
1510 return (ENOBUFS);
1511 }
1512
1513 if (txmap->dm_nsegs > (MSK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) {
1514 DPRINTFN(2, ("msk_encap: too few descriptors free\n"));
1515 bus_dmamap_unload(sc->sc_dmatag, txmap);
1516 return (ENOBUFS);
1517 }
1518
1519 DPRINTFN(2, ("msk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
1520
1521 /* Sync the DMA map. */
1522 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1523 BUS_DMASYNC_PREWRITE);
1524
1525 for (i = 0; i < txmap->dm_nsegs; i++) {
1526 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1527 f->sk_addr = htole32(txmap->dm_segs[i].ds_addr);
1528 f->sk_len = htole16(txmap->dm_segs[i].ds_len);
1529 f->sk_ctl = 0;
1530 if (i == 0)
1531 f->sk_opcode = SK_Y2_TXOPC_PACKET;
1532 else
1533 f->sk_opcode = SK_Y2_TXOPC_BUFFER | SK_Y2_TXOPC_OWN;
1534 cur = frag;
1535 SK_INC(frag, MSK_TX_RING_CNT);
1536 }
1537
1538 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1539 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
1540
1541 sc_if->sk_cdata.sk_tx_map[cur] = entry;
1542 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= SK_Y2_TXCTL_LASTFRAG;
1543
1544 /* Sync descriptors before handing to chip */
1545 MSK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
1546 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1547
1548 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_opcode |= SK_Y2_TXOPC_OWN;
1549
1550 /* Sync first descriptor to hand it off */
1551 MSK_CDTXSYNC(sc_if, *txidx, 1,
1552 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1553
1554 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
1555
1556 #ifdef MSK_DEBUG
1557 if (mskdebug >= 2) {
1558 struct msk_tx_desc *le;
1559 u_int32_t idx;
1560 for (idx = *txidx; idx != frag; SK_INC(idx, MSK_TX_RING_CNT)) {
1561 le = &sc_if->sk_rdata->sk_tx_ring[idx];
1562 msk_dump_txdesc(le, idx);
1563 }
1564 }
1565 #endif
1566
1567 *txidx = frag;
1568
1569 DPRINTFN(2, ("msk_encap: completed successfully\n"));
1570
1571 return (0);
1572 }
1573
1574 void
1575 msk_start(struct ifnet *ifp)
1576 {
1577 struct sk_if_softc *sc_if = ifp->if_softc;
1578 struct mbuf *m_head = NULL;
1579 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod;
1580 int pkts = 0;
1581
1582 DPRINTFN(2, ("msk_start\n"));
1583
1584 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1585 IFQ_POLL(&ifp->if_snd, m_head);
1586 if (m_head == NULL)
1587 break;
1588
1589 /*
1590 * Pack the data into the transmit ring. If we
1591 * don't have room, set the OACTIVE flag and wait
1592 * for the NIC to drain the ring.
1593 */
1594 if (msk_encap(sc_if, m_head, &idx)) {
1595 ifp->if_flags |= IFF_OACTIVE;
1596 break;
1597 }
1598
1599 /* now we are committed to transmit the packet */
1600 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1601 pkts++;
1602
1603 /*
1604 * If there's a BPF listener, bounce a copy of this frame
1605 * to him.
1606 */
1607 #if NBPFILTER > 0
1608 if (ifp->if_bpf)
1609 bpf_mtap(ifp->if_bpf, m_head);
1610 #endif
1611 }
1612 if (pkts == 0)
1613 return;
1614
1615 /* Transmit */
1616 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1617 sc_if->sk_cdata.sk_tx_prod = idx;
1618 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_PUTIDX, idx);
1619
1620 /* Set a timeout in case the chip goes out to lunch. */
1621 ifp->if_timer = 5;
1622 }
1623 }
1624
1625 void
1626 msk_watchdog(struct ifnet *ifp)
1627 {
1628 struct sk_if_softc *sc_if = ifp->if_softc;
1629 u_int32_t reg;
1630 int idx;
1631
1632 /*
1633 * Reclaim first as there is a possibility of losing Tx completion
1634 * interrupts.
1635 */
1636 if (sc_if->sk_port == SK_PORT_A)
1637 reg = SK_STAT_BMU_TXA1_RIDX;
1638 else
1639 reg = SK_STAT_BMU_TXA2_RIDX;
1640
1641 idx = sk_win_read_2(sc_if->sk_softc, reg);
1642 if (sc_if->sk_cdata.sk_tx_cons != idx) {
1643 msk_txeof(sc_if, idx);
1644 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1645 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n");
1646
1647 ifp->if_oerrors++;
1648
1649 /* XXX Resets both ports; we shouldn't do that. */
1650 msk_reset(sc_if->sk_softc);
1651 msk_init(ifp);
1652 }
1653 }
1654 }
1655
1656 static bool
1657 mskc_suspend(device_t dv, pmf_qual_t qual)
1658 {
1659 struct sk_softc *sc = device_private(dv);
1660
1661 DPRINTFN(2, ("mskc_suspend\n"));
1662
1663 /* Turn off the 'driver is loaded' LED. */
1664 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1665
1666 return true;
1667 }
1668
1669 static bool
1670 mskc_resume(device_t dv, pmf_qual_t qual)
1671 {
1672 struct sk_softc *sc = device_private(dv);
1673
1674 DPRINTFN(2, ("mskc_resume\n"));
1675
1676 msk_reset(sc);
1677 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1678
1679 return true;
1680 }
1681
1682 __inline int
1683 msk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
1684 {
1685 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1686 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1687 YU_RXSTAT_JABBER)) != 0 ||
1688 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1689 YU_RXSTAT_BYTES(stat) != len)
1690 return (0);
1691
1692 return (1);
1693 }
1694
1695 void
1696 msk_rxeof(struct sk_if_softc *sc_if, u_int16_t len, u_int32_t rxstat)
1697 {
1698 struct sk_softc *sc = sc_if->sk_softc;
1699 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
1700 struct mbuf *m;
1701 struct sk_chain *cur_rx;
1702 int cur, total_len = len;
1703 bus_dmamap_t dmamap;
1704
1705 DPRINTFN(2, ("msk_rxeof\n"));
1706
1707 cur = sc_if->sk_cdata.sk_rx_cons;
1708 SK_INC(sc_if->sk_cdata.sk_rx_cons, MSK_RX_RING_CNT);
1709 SK_INC(sc_if->sk_cdata.sk_rx_prod, MSK_RX_RING_CNT);
1710
1711 /* Sync the descriptor */
1712 MSK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1713
1714 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
1715 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
1716
1717 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
1718 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1719
1720 m = cur_rx->sk_mbuf;
1721 cur_rx->sk_mbuf = NULL;
1722
1723 if (total_len < SK_MIN_FRAMELEN ||
1724 total_len > ETHER_MAX_LEN_JUMBO ||
1725 msk_rxvalid(sc, rxstat, total_len) == 0) {
1726 ifp->if_ierrors++;
1727 msk_newbuf(sc_if, cur, m, dmamap);
1728 return;
1729 }
1730
1731 /*
1732 * Try to allocate a new jumbo buffer. If that fails, copy the
1733 * packet to mbufs and put the jumbo buffer back in the ring
1734 * so it can be re-used. If allocating mbufs fails, then we
1735 * have to drop the packet.
1736 */
1737 if (msk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
1738 struct mbuf *m0;
1739 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1740 total_len + ETHER_ALIGN, 0, ifp, NULL);
1741 msk_newbuf(sc_if, cur, m, dmamap);
1742 if (m0 == NULL) {
1743 ifp->if_ierrors++;
1744 return;
1745 }
1746 m_adj(m0, ETHER_ALIGN);
1747 m = m0;
1748 } else {
1749 m->m_pkthdr.rcvif = ifp;
1750 m->m_pkthdr.len = m->m_len = total_len;
1751 }
1752
1753 ifp->if_ipackets++;
1754
1755 #if NBPFILTER > 0
1756 if (ifp->if_bpf)
1757 bpf_mtap(ifp->if_bpf, m);
1758 #endif
1759
1760 /* pass it on. */
1761 (*ifp->if_input)(ifp, m);
1762 }
1763
1764 void
1765 msk_txeof(struct sk_if_softc *sc_if, int idx)
1766 {
1767 struct sk_softc *sc = sc_if->sk_softc;
1768 struct msk_tx_desc *cur_tx;
1769 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
1770 u_int32_t sk_ctl;
1771 struct sk_txmap_entry *entry;
1772 int cons, prog;
1773
1774 DPRINTFN(2, ("msk_txeof\n"));
1775
1776 /*
1777 * Go through our tx ring and free mbufs for those
1778 * frames that have been sent.
1779 */
1780 cons = sc_if->sk_cdata.sk_tx_cons;
1781 prog = 0;
1782 while (cons != idx) {
1783 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
1784 break;
1785 prog++;
1786 cur_tx = &sc_if->sk_rdata->sk_tx_ring[cons];
1787
1788 MSK_CDTXSYNC(sc_if, cons, 1,
1789 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1790 sk_ctl = cur_tx->sk_ctl;
1791 MSK_CDTXSYNC(sc_if, cons, 1, BUS_DMASYNC_PREREAD);
1792 #ifdef MSK_DEBUG
1793 if (mskdebug >= 2)
1794 msk_dump_txdesc(cur_tx, cons);
1795 #endif
1796 if (sk_ctl & SK_Y2_TXCTL_LASTFRAG)
1797 ifp->if_opackets++;
1798 if (sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf != NULL) {
1799 entry = sc_if->sk_cdata.sk_tx_map[cons];
1800
1801 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
1802 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1803
1804 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
1805 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
1806 link);
1807 sc_if->sk_cdata.sk_tx_map[cons] = NULL;
1808 m_freem(sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf);
1809 sc_if->sk_cdata.sk_tx_chain[cons].sk_mbuf = NULL;
1810 }
1811 sc_if->sk_cdata.sk_tx_cnt--;
1812 SK_INC(cons, MSK_TX_RING_CNT);
1813 }
1814 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
1815
1816 if (sc_if->sk_cdata.sk_tx_cnt < MSK_TX_RING_CNT - 2)
1817 ifp->if_flags &= ~IFF_OACTIVE;
1818
1819 if (prog > 0)
1820 sc_if->sk_cdata.sk_tx_cons = cons;
1821 }
1822
1823 void
1824 msk_tick(void *xsc_if)
1825 {
1826 struct sk_if_softc *sc_if = xsc_if;
1827 struct mii_data *mii = &sc_if->sk_mii;
1828 uint16_t gpsr;
1829 int s;
1830
1831 s = splnet();
1832 gpsr = SK_YU_READ_2(sc_if, YUKON_GPSR);
1833 if ((gpsr & YU_GPSR_MII_PHY_STC) != 0) {
1834 SK_YU_WRITE_2(sc_if, YUKON_GPSR, YU_GPSR_MII_PHY_STC);
1835 mii_tick(mii);
1836 }
1837 splx(s);
1838
1839 callout_schedule(&sc_if->sk_tick_ch, hz);
1840 }
1841
1842 void
1843 msk_intr_yukon(struct sk_if_softc *sc_if)
1844 {
1845 u_int8_t status;
1846
1847 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
1848 /* RX overrun */
1849 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
1850 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
1851 SK_RFCTL_RX_FIFO_OVER);
1852 }
1853 /* TX underrun */
1854 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
1855 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
1856 SK_TFCTL_TX_FIFO_UNDER);
1857 }
1858
1859 DPRINTFN(2, ("msk_intr_yukon status=%#x\n", status));
1860 }
1861
1862 int
1863 msk_intr(void *xsc)
1864 {
1865 struct sk_softc *sc = xsc;
1866 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
1867 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
1868 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1869 int claimed = 0;
1870 u_int32_t status;
1871 uint32_t st_status;
1872 uint16_t st_len;
1873 uint8_t st_opcode, st_link;
1874 struct msk_status_desc *cur_st;
1875
1876 status = CSR_READ_4(sc, SK_Y2_ISSR2);
1877 if (status == 0) {
1878 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
1879 return (0);
1880 }
1881
1882 status = CSR_READ_4(sc, SK_ISR);
1883
1884 if (sc_if0 != NULL)
1885 ifp0 = &sc_if0->sk_ethercom.ec_if;
1886 if (sc_if1 != NULL)
1887 ifp1 = &sc_if1->sk_ethercom.ec_if;
1888
1889 if (sc_if0 && (status & SK_Y2_IMR_MAC1) &&
1890 (ifp0->if_flags & IFF_RUNNING)) {
1891 msk_intr_yukon(sc_if0);
1892 }
1893
1894 if (sc_if1 && (status & SK_Y2_IMR_MAC2) &&
1895 (ifp1->if_flags & IFF_RUNNING)) {
1896 msk_intr_yukon(sc_if1);
1897 }
1898
1899 for (;;) {
1900 cur_st = &sc->sk_status_ring[sc->sk_status_idx];
1901 MSK_CDSTSYNC(sc, sc->sk_status_idx,
1902 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1903 st_opcode = cur_st->sk_opcode;
1904 if ((st_opcode & SK_Y2_STOPC_OWN) == 0) {
1905 MSK_CDSTSYNC(sc, sc->sk_status_idx,
1906 BUS_DMASYNC_PREREAD);
1907 break;
1908 }
1909 st_status = le32toh(cur_st->sk_status);
1910 st_len = le16toh(cur_st->sk_len);
1911 st_link = cur_st->sk_link;
1912 st_opcode &= ~SK_Y2_STOPC_OWN;
1913
1914 switch (st_opcode) {
1915 case SK_Y2_STOPC_RXSTAT:
1916 msk_rxeof(sc->sk_if[st_link], st_len, st_status);
1917 SK_IF_WRITE_2(sc->sk_if[st_link], 0,
1918 SK_RXQ1_Y2_PREF_PUTIDX,
1919 sc->sk_if[st_link]->sk_cdata.sk_rx_prod);
1920 break;
1921 case SK_Y2_STOPC_TXSTAT:
1922 if (sc_if0)
1923 msk_txeof(sc_if0, st_status
1924 & SK_Y2_ST_TXA1_MSKL);
1925 if (sc_if1)
1926 msk_txeof(sc_if1,
1927 ((st_status & SK_Y2_ST_TXA2_MSKL)
1928 >> SK_Y2_ST_TXA2_SHIFTL)
1929 | ((st_len & SK_Y2_ST_TXA2_MSKH) << SK_Y2_ST_TXA2_SHIFTH));
1930 break;
1931 default:
1932 aprint_error("opcode=0x%x\n", st_opcode);
1933 break;
1934 }
1935 SK_INC(sc->sk_status_idx, MSK_STATUS_RING_CNT);
1936 }
1937
1938 #define MSK_STATUS_RING_OWN_CNT(sc) \
1939 (((sc)->sk_status_idx + MSK_STATUS_RING_CNT - \
1940 (sc)->sk_status_own_idx) % MSK_STATUS_RING_CNT)
1941
1942 while (MSK_STATUS_RING_OWN_CNT(sc) > MSK_STATUS_RING_CNT / 2) {
1943 cur_st = &sc->sk_status_ring[sc->sk_status_own_idx];
1944 cur_st->sk_opcode &= ~SK_Y2_STOPC_OWN;
1945 MSK_CDSTSYNC(sc, sc->sk_status_own_idx,
1946 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1947
1948 SK_INC(sc->sk_status_own_idx, MSK_STATUS_RING_CNT);
1949 }
1950
1951 if (status & SK_Y2_IMR_BMU) {
1952 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR);
1953 claimed = 1;
1954 }
1955
1956 CSR_WRITE_4(sc, SK_Y2_ICR, 2);
1957
1958 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd))
1959 msk_start(ifp0);
1960 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd))
1961 msk_start(ifp1);
1962
1963 #if NRND > 0
1964 if (RND_ENABLED(&sc->rnd_source))
1965 rnd_add_uint32(&sc->rnd_source, status);
1966 #endif
1967
1968 if (sc->sk_int_mod_pending)
1969 msk_update_int_mod(sc, 1);
1970
1971 return claimed;
1972 }
1973
1974 void
1975 msk_init_yukon(struct sk_if_softc *sc_if)
1976 {
1977 u_int32_t v;
1978 u_int16_t reg;
1979 struct sk_softc *sc;
1980 int i;
1981
1982 sc = sc_if->sk_softc;
1983
1984 DPRINTFN(2, ("msk_init_yukon: start: sk_csr=%#x\n",
1985 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
1986
1987 DPRINTFN(6, ("msk_init_yukon: 1\n"));
1988
1989 /* GMAC and GPHY Reset */
1990 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
1991 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
1992 DELAY(1000);
1993
1994 DPRINTFN(6, ("msk_init_yukon: 2\n"));
1995
1996 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
1997 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
1998 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
1999
2000 DPRINTFN(3, ("msk_init_yukon: gmac_ctrl=%#x\n",
2001 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2002
2003 DPRINTFN(6, ("msk_init_yukon: 3\n"));
2004
2005 /* unused read of the interrupt source register */
2006 DPRINTFN(6, ("msk_init_yukon: 4\n"));
2007 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2008
2009 DPRINTFN(6, ("msk_init_yukon: 4a\n"));
2010 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2011 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
2012
2013 /* MIB Counter Clear Mode set */
2014 reg |= YU_PAR_MIB_CLR;
2015 DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));
2016 DPRINTFN(6, ("msk_init_yukon: 4b\n"));
2017 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2018
2019 /* MIB Counter Clear Mode clear */
2020 DPRINTFN(6, ("msk_init_yukon: 5\n"));
2021 reg &= ~YU_PAR_MIB_CLR;
2022 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2023
2024 /* receive control reg */
2025 DPRINTFN(6, ("msk_init_yukon: 7\n"));
2026 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2027
2028 /* transmit control register */
2029 SK_YU_WRITE_2(sc_if, YUKON_TCR, (0x04 << 10));
2030
2031 /* transmit flow control register */
2032 SK_YU_WRITE_2(sc_if, YUKON_TFCR, 0xffff);
2033
2034 /* transmit parameter register */
2035 DPRINTFN(6, ("msk_init_yukon: 8\n"));
2036 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2037 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1c) | 0x04);
2038
2039 /* serial mode register */
2040 DPRINTFN(6, ("msk_init_yukon: 9\n"));
2041 reg = YU_SMR_DATA_BLIND(0x1c) |
2042 YU_SMR_MFL_VLAN |
2043 YU_SMR_IPG_DATA(0x1e);
2044
2045 if (sc->sk_type != SK_YUKON_FE)
2046 reg |= YU_SMR_MFL_JUMBO;
2047
2048 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2049
2050 DPRINTFN(6, ("msk_init_yukon: 10\n"));
2051 /* Setup Yukon's address */
2052 for (i = 0; i < 3; i++) {
2053 /* Write Source Address 1 (unicast filter) */
2054 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2055 sc_if->sk_enaddr[i * 2] |
2056 sc_if->sk_enaddr[i * 2 + 1] << 8);
2057 }
2058
2059 for (i = 0; i < 3; i++) {
2060 reg = sk_win_read_2(sc_if->sk_softc,
2061 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2062 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2063 }
2064
2065 /* Set promiscuous mode */
2066 msk_setpromisc(sc_if);
2067
2068 /* Set multicast filter */
2069 DPRINTFN(6, ("msk_init_yukon: 11\n"));
2070 msk_setmulti(sc_if);
2071
2072 /* enable interrupt mask for counter overflows */
2073 DPRINTFN(6, ("msk_init_yukon: 12\n"));
2074 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2075 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2076 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2077
2078 /* Configure RX MAC FIFO Flush Mask */
2079 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2080 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2081 YU_RXSTAT_JABBER;
2082 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2083
2084 /* Configure RX MAC FIFO */
2085 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2086 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON |
2087 SK_RFCTL_FIFO_FLUSH_ON);
2088
2089 /* Increase flush threshould to 64 bytes */
2090 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2091 SK_RFCTL_FIFO_THRESHOLD + 1);
2092
2093 /* Configure TX MAC FIFO */
2094 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2095 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2096
2097 #if 1
2098 SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
2099 #endif
2100 DPRINTFN(6, ("msk_init_yukon: end\n"));
2101 }
2102
2103 /*
2104 * Note that to properly initialize any part of the GEnesis chip,
2105 * you first have to take it out of reset mode.
2106 */
2107 int
2108 msk_init(struct ifnet *ifp)
2109 {
2110 struct sk_if_softc *sc_if = ifp->if_softc;
2111 struct sk_softc *sc = sc_if->sk_softc;
2112 int rc = 0, s;
2113 uint32_t imr, imtimer_ticks;
2114
2115
2116 DPRINTFN(2, ("msk_init\n"));
2117
2118 s = splnet();
2119
2120 /* Cancel pending I/O and free all RX/TX buffers. */
2121 msk_stop(ifp,0);
2122
2123 /* Configure I2C registers */
2124
2125 /* Configure XMAC(s) */
2126 msk_init_yukon(sc_if);
2127 if ((rc = ether_mediachange(ifp)) != 0)
2128 goto out;
2129
2130 /* Configure transmit arbiter(s) */
2131 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
2132 #if 0
2133 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2134 #endif
2135
2136 /* Configure RAMbuffers */
2137 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2138 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2139 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2140 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2141 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2142 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2143
2144 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_UNRESET);
2145 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_STORENFWD_ON);
2146 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_START, sc_if->sk_tx_ramstart);
2147 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_WR_PTR, sc_if->sk_tx_ramstart);
2148 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_RD_PTR, sc_if->sk_tx_ramstart);
2149 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_END, sc_if->sk_tx_ramend);
2150 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_ON);
2151
2152 /* Configure BMUs */
2153 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000016);
2154 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000d28);
2155 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, 0x00000080);
2156 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_WM, 0x0600); /* XXX ??? */
2157
2158 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000016);
2159 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000d28);
2160 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, 0x00000080);
2161 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_WM, 0x0600); /* XXX ??? */
2162
2163 /* Make sure the sync transmit queue is disabled. */
2164 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET);
2165
2166 /* Init descriptors */
2167 if (msk_init_rx_ring(sc_if) == ENOBUFS) {
2168 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2169 "memory for rx buffers\n");
2170 msk_stop(ifp,0);
2171 splx(s);
2172 return ENOBUFS;
2173 }
2174
2175 if (msk_init_tx_ring(sc_if) == ENOBUFS) {
2176 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2177 "memory for tx buffers\n");
2178 msk_stop(ifp,0);
2179 splx(s);
2180 return ENOBUFS;
2181 }
2182
2183 /* Set interrupt moderation if changed via sysctl. */
2184 switch (sc->sk_type) {
2185 case SK_YUKON_EC:
2186 case SK_YUKON_EC_U:
2187 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
2188 break;
2189 case SK_YUKON_FE:
2190 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_FE;
2191 break;
2192 case SK_YUKON_XL:
2193 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_XL;
2194 break;
2195 default:
2196 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
2197 }
2198 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2199 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
2200 sk_win_write_4(sc, SK_IMTIMERINIT,
2201 SK_IM_USECS(sc->sk_int_mod));
2202 aprint_verbose_dev(sc->sk_dev,
2203 "yinterrupt moderation is %d us\n", sc->sk_int_mod);
2204 }
2205
2206 /* Initialize prefetch engine. */
2207 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2208 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000002);
2209 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_LIDX, MSK_RX_RING_CNT - 1);
2210 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRLO,
2211 MSK_RX_RING_ADDR(sc_if, 0));
2212 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_ADDRHI,
2213 (u_int64_t)MSK_RX_RING_ADDR(sc_if, 0) >> 32);
2214 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000008);
2215 SK_IF_READ_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR);
2216
2217 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2218 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000002);
2219 SK_IF_WRITE_2(sc_if, 1, SK_TXQA1_Y2_PREF_LIDX, MSK_TX_RING_CNT - 1);
2220 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRLO,
2221 MSK_TX_RING_ADDR(sc_if, 0));
2222 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_ADDRHI,
2223 (u_int64_t)MSK_TX_RING_ADDR(sc_if, 0) >> 32);
2224 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000008);
2225 SK_IF_READ_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR);
2226
2227 SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
2228 sc_if->sk_cdata.sk_rx_prod);
2229
2230 /* Configure interrupt handling */
2231 if (sc_if->sk_port == SK_PORT_A)
2232 sc->sk_intrmask |= SK_Y2_INTRS1;
2233 else
2234 sc->sk_intrmask |= SK_Y2_INTRS2;
2235 sc->sk_intrmask |= SK_Y2_IMR_BMU;
2236 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2237
2238 ifp->if_flags |= IFF_RUNNING;
2239 ifp->if_flags &= ~IFF_OACTIVE;
2240
2241 callout_schedule(&sc_if->sk_tick_ch, hz);
2242
2243 out:
2244 splx(s);
2245 return rc;
2246 }
2247
2248 void
2249 msk_stop(struct ifnet *ifp, int disable)
2250 {
2251 struct sk_if_softc *sc_if = ifp->if_softc;
2252 struct sk_softc *sc = sc_if->sk_softc;
2253 struct sk_txmap_entry *dma;
2254 int i;
2255
2256 DPRINTFN(2, ("msk_stop\n"));
2257
2258 callout_stop(&sc_if->sk_tick_ch);
2259
2260 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2261
2262 /* Stop transfer of Tx descriptors */
2263
2264 /* Stop transfer of Rx descriptors */
2265
2266 /* Turn off various components of this interface. */
2267 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2268 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2269 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2270 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2271 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2272 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_BMU_CSR, SK_TXBMU_OFFLINE);
2273 SK_IF_WRITE_4(sc_if, 1, SK_TXRBA1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2274 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2275 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2276 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_STOP);
2277 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2278 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2279
2280 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_Y2_PREF_CSR, 0x00000001);
2281 SK_IF_WRITE_4(sc_if, 1, SK_TXQA1_Y2_PREF_CSR, 0x00000001);
2282
2283 /* Disable interrupts */
2284 if (sc_if->sk_port == SK_PORT_A)
2285 sc->sk_intrmask &= ~SK_Y2_INTRS1;
2286 else
2287 sc->sk_intrmask &= ~SK_Y2_INTRS2;
2288 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2289
2290 SK_XM_READ_2(sc_if, XM_ISR);
2291 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2292
2293 /* Free RX and TX mbufs still in the queues. */
2294 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2295 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2296 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2297 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2298 }
2299 }
2300
2301 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2302 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2303 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2304 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2305 #if 1
2306 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head,
2307 sc_if->sk_cdata.sk_tx_map[i], link);
2308 sc_if->sk_cdata.sk_tx_map[i] = 0;
2309 #endif
2310 }
2311 }
2312
2313 #if 1
2314 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) {
2315 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
2316 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap);
2317 free(dma, M_DEVBUF);
2318 }
2319 #endif
2320 }
2321
2322 CFATTACH_DECL_NEW(mskc, sizeof(struct sk_softc), mskc_probe, mskc_attach,
2323 NULL, NULL);
2324
2325 CFATTACH_DECL_NEW(msk, sizeof(struct sk_if_softc), msk_probe, msk_attach,
2326 NULL, NULL);
2327
2328 #ifdef MSK_DEBUG
2329 void
2330 msk_dump_txdesc(struct msk_tx_desc *le, int idx)
2331 {
2332 #define DESC_PRINT(X) \
2333 if (X) \
2334 printf("txdesc[%d]." #X "=%#x\n", \
2335 idx, X);
2336
2337 DESC_PRINT(letoh32(le->sk_addr));
2338 DESC_PRINT(letoh16(le->sk_len));
2339 DESC_PRINT(le->sk_ctl);
2340 DESC_PRINT(le->sk_opcode);
2341 #undef DESC_PRINT
2342 }
2343
2344 void
2345 msk_dump_bytes(const char *data, int len)
2346 {
2347 int c, i, j;
2348
2349 for (i = 0; i < len; i += 16) {
2350 printf("%08x ", i);
2351 c = len - i;
2352 if (c > 16) c = 16;
2353
2354 for (j = 0; j < c; j++) {
2355 printf("%02x ", data[i + j] & 0xff);
2356 if ((j & 0xf) == 7 && j > 0)
2357 printf(" ");
2358 }
2359
2360 for (; j < 16; j++)
2361 printf(" ");
2362 printf(" ");
2363
2364 for (j = 0; j < c; j++) {
2365 int ch = data[i + j] & 0xff;
2366 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2367 }
2368
2369 printf("\n");
2370
2371 if (c < 16)
2372 break;
2373 }
2374 }
2375
2376 void
2377 msk_dump_mbuf(struct mbuf *m)
2378 {
2379 int count = m->m_pkthdr.len;
2380
2381 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2382
2383 while (count > 0 && m) {
2384 printf("m=%p, m->m_data=%p, m->m_len=%d\n",
2385 m, m->m_data, m->m_len);
2386 msk_dump_bytes(mtod(m, char *), m->m_len);
2387
2388 count -= m->m_len;
2389 m = m->m_next;
2390 }
2391 }
2392 #endif
2393
2394 static int
2395 msk_sysctl_handler(SYSCTLFN_ARGS)
2396 {
2397 int error, t;
2398 struct sysctlnode node;
2399 struct sk_softc *sc;
2400
2401 node = *rnode;
2402 sc = node.sysctl_data;
2403 t = sc->sk_int_mod;
2404 node.sysctl_data = &t;
2405 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2406 if (error || newp == NULL)
2407 return error;
2408
2409 if (t < SK_IM_MIN || t > SK_IM_MAX)
2410 return EINVAL;
2411
2412 /* update the softc with sysctl-changed value, and mark
2413 for hardware update */
2414 sc->sk_int_mod = t;
2415 sc->sk_int_mod_pending = 1;
2416 return 0;
2417 }
2418
2419 /*
2420 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be
2421 * set up in skc_attach()
2422 */
2423 SYSCTL_SETUP(sysctl_msk, "sysctl msk subtree setup")
2424 {
2425 int rc;
2426 const struct sysctlnode *node;
2427
2428 if ((rc = sysctl_createv(clog, 0, NULL, NULL,
2429 0, CTLTYPE_NODE, "hw", NULL,
2430 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
2431 goto err;
2432 }
2433
2434 if ((rc = sysctl_createv(clog, 0, NULL, &node,
2435 0, CTLTYPE_NODE, "msk",
2436 SYSCTL_DESCR("msk interface controls"),
2437 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2438 goto err;
2439 }
2440
2441 msk_root_num = node->sysctl_num;
2442 return;
2443
2444 err:
2445 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2446 }
NetBSD on the FriendlyARM MINI2440