sys/dev/pci/if_ntwoc_pcireg.h

   1 /*      $NetBSD: if_ntwoc_pcireg.h,v 1.3.28.1 2005/03/04 16:45:18 skrll Exp $   */
   2
   3 /*
   4  * Copyright (c) 1998 Vixie Enterprises
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the name of Vixie Enterprises nor the names
  17  *    of its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND
  21  * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED.  IN NO EVENT SHALL VIXIE ENTERPRISES OR
  25  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * This software has been written for Vixie Enterprises by Michael Graff
  35  * <explorer@flame.org>.  To learn more about Vixie Enterprises, see
  36  * ``http://www.vix.com''.
  37  */
  38
  39 #ifndef _IF_NTWOC_PCIREG_H_
  40 #define _IF_NTWOC_PCIREG_H_
  41
  42 /* config flags are as follows */
  43 /*
  44  * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  45  * +-------------+ +-----+ +-----+ + +---+ +-+     + +---+ +-+   +
  46  *       tmc         tdiv    rdiv  e1 rxs1 ts1    e0 rxs0  txs0  nports - 1
  47  */
  48 #define NTWOC_FLAGS_CLK0_MASK   0x000000fc      /* port 0 clock info mask */
  49 #define NTWOC_FLAGS_CLK1_MASK   0x0000fc00      /* port 1 clock info mask */
  50 #define NTWOC_FLAGS_RXDIV_MASK  0x000F0000      /* rx div mask */
  51 #define NTWOC_FLAGS_TXDIV_MASK  0x00F00000      /* tx div mask */
  52 #define NTWOC_FLAGS_TMC_MASK    0xFF000000      /* tmc port 0 mask */
  53
  54 #define NTWOC_FLAGS_CLK1_SHIFT  8
  55
  56 /* these are used after you shift down to the clock byte for the resp. port */
  57 #define NTWOC_FLAGS_TXS_SHIFT           2
  58 #define NTWOC_FLAGS_TXS_MASK    0x0000000c      /* port 0 tx clk source mask */
  59 #define NTWOC_FLAGS_TXS_LINE            0       /* use the line clock */
  60 #define NTWOC_FLAGS_TXS_INTERNAL        1       /* use the internal clock */
  61 #define NTWOC_FLAGS_TXS_RXCLOCK         2       /* use the receive clock */
  62
  63 #define NTWOC_FLAGS_RXS_SHIFT           4
  64 #define NTWOC_FLAGS_RXS_MASK    0x00000070      /* port 0 rx clk source mask */
  65 #define NTWOC_FLAGS_RXS_LINE            0       /* use the line clock */
  66 #define NTWOC_FLAGS_RXS_LINE_SN         1       /* use line with noise supp. */
  67 #define NTWOC_FLAGS_RXS_INTERNAL        2       /* use internal clock */
  68 #define NTWOC_FLAGS_RXS_ADPLL_OUT       3       /* use brg out for adpll clk */
  69 #define NTWOC_FLAGS_RXS_ADPLL_IN        4       /* use line in for adpll clk */
  70
  71 #define NTWOC_FLAGS_ECLOCK_SHIFT        7       /* generate external clock */
  72 #define NTWOC_FLAGS_ECLOCK_MASK 0x00000080      /* port 0 ext clk gen mask */
  73
  74 /* these are used on the flags directly */
  75 #define NTWOC_FLAGS_RXDIV_SHIFT 16
  76 #define NTWOC_FLAGS_TXDIV_SHIFT 20
  77 #define NTWOC_FLAGS_TMC_SHIFT   24
  78
  79 /*
  80  * ASIC register offsets
  81  */
  82
  83 /*
  84  * This register is in the SCA namespace, but is NOT really an SCA register.
  85  * It contains information about the daughter cards, and provides a method
  86  * to configure them.
  87  */
  88 #define NTWOC_FECR      0x200
  89
  90 /*
  91  * definition of the NTWO_FECR register
  92  */
  93 #define NTWOC_FECR_ID0          0x0e00  /* mask of daughter card on port 0 */
  94 #define NTWOC_FECR_ID0_SHIFT         9
  95 #define NTWOC_FECR_ID1          0xe000  /* mask of daughter card on port 1 */
  96 #define NTWOC_FECR_ID1_SHIFT        13
  97
  98 #define NTWOC_FECR_DTR1         0x0080  /* DTR output for port 1 */
  99 #define NTWOC_FECR_DTR0         0x0040  /* DTR output for port 0 */
 100 #define NTWOC_FECR_DSR1         0x1000  /* DSR input for port 1 */
 101 #define NTWOC_FECR_DSR0         0x0100  /* DSR input for port 0 */
 102 #define NTWOC_FECR_TE1          0x0008  /* tristate enable port 1 */
 103 #define NTWOC_FECR_TE0          0x0004  /* tristate enable port 0 */
 104 #define NTWOC_FECR_ETC1         0x0002  /* output clock port 1 */
 105 #define NTWOC_FECR_ETC0         0x0001  /* output clock port 0 */
 106
 107 /*
 108  * Daughter card for port.
 109  */
 110 #define NTWOC_FE_ID_V35         0x00
 111 #define NTWOC_FE_ID_X01         0x01    /* unused? */
 112 #define NTWOC_FE_ID_TEST        0x02
 113 #define NTWOC_FE_ID_X03         0x03    /* unused? */
 114 #define NTWOC_FE_ID_RS232       0x04
 115 #define NTWOC_FE_ID_X05         0x05    /* was hssi, now unused? */
 116 #define NTWOC_FE_ID_RS422       0x06
 117 #define NTWOC_FE_ID_NONE        0x07    /* empty, no card present */
 118
 119 /*
 120  * ASIC Control defininitions
 121  */
 122
 123 /* Front End (Modem,etc) Control Register */
 124
 125 #define  ASIC_MODEM   0x200   /* ASIC modem control register Offset */
 126
 127 /* ASIC front end control register bits */
 128 #define  ASIC_DSR1       0x1000    /* DSR signal input port 1 */
 129 #define  ASIC_DSR0        0x100    /* DSR signal input port 0 */
 130 #define  ASIC_DTR1         0x80    /* DTR signal output port 1 */
 131 #define  ASIC_DTR0         0x40    /* DTR signal output port 0 */
 132 #define  ASIC_TE1           0x8    /* RS422 TX,enable port 1 */
 133 #define  ASIC_TE0           0x4    /* RS422 TX,enable port 0 */
 134 #define  ASIC_ETC1          0x2    /* ETC Clock out port 1 */
 135 #define  ASIC_ETC0          0x1    /* ETC Clock out port 0 */
 136
 137 #endif /* _IF_NTWOC_PCIREG_H_ */