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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_sip.c
blobadc1f2879880db0159296fdb8ba3c6ce92cb6b52
1 /* $NetBSD: if_sip.c,v 1.143 2009/11/26 15:17:10 njoly Exp $ */
2
3 /*-
4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*-
33 * Copyright (c) 1999 Network Computer, Inc.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. Neither the name of Network Computer, Inc. nor the names of its
45 * contributors may be used to endorse or promote products derived
46 * from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61 /*
62 * Device driver for the Silicon Integrated Systems SiS 900,
63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and
64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet
65 * controllers.
66 *
67 * Originally written to support the SiS 900 by Jason R. Thorpe for
68 * Network Computer, Inc.
69 *
70 * TODO:
71 *
72 * - Reduce the Rx interrupt load.
73 */
74
75 #include <sys/cdefs.h>
76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.143 2009/11/26 15:17:10 njoly Exp $");
77
78 #include "bpfilter.h"
79 #include "rnd.h"
80
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/callout.h>
84 #include <sys/mbuf.h>
85 #include <sys/malloc.h>
86 #include <sys/kernel.h>
87 #include <sys/socket.h>
88 #include <sys/ioctl.h>
89 #include <sys/errno.h>
90 #include <sys/device.h>
91 #include <sys/queue.h>
92
93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */
94
95 #if NRND > 0
96 #include <sys/rnd.h>
97 #endif
98
99 #include <net/if.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102 #include <net/if_ether.h>
103
104 #if NBPFILTER > 0
105 #include <net/bpf.h>
106 #endif
107
108 #include <sys/bus.h>
109 #include <sys/intr.h>
110 #include <machine/endian.h>
111
112 #include <dev/mii/mii.h>
113 #include <dev/mii/miivar.h>
114 #include <dev/mii/mii_bitbang.h>
115
116 #include <dev/pci/pcireg.h>
117 #include <dev/pci/pcivar.h>
118 #include <dev/pci/pcidevs.h>
119
120 #include <dev/pci/if_sipreg.h>
121
122 /*
123 * Transmit descriptor list size. This is arbitrary, but allocate
124 * enough descriptors for 128 pending transmissions, and 8 segments
125 * per packet (64 for DP83820 for jumbo frames).
126 *
127 * This MUST work out to a power of 2.
128 */
129 #define GSIP_NTXSEGS_ALLOC 16
130 #define SIP_NTXSEGS_ALLOC 8
131
132 #define SIP_TXQUEUELEN 256
133 #define MAX_SIP_NTXDESC \
134 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC))
135
136 /*
137 * Receive descriptor list size. We have one Rx buffer per incoming
138 * packet, so this logic is a little simpler.
139 *
140 * Actually, on the DP83820, we allow the packet to consume more than
141 * one buffer, in order to support jumbo Ethernet frames. In that
142 * case, a packet may consume up to 5 buffers (assuming a 2048 byte
143 * mbuf cluster). 256 receive buffers is only 51 maximum size packets,
144 * so we'd better be quick about handling receive interrupts.
145 */
146 #define GSIP_NRXDESC 256
147 #define SIP_NRXDESC 128
148
149 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC)
150
151 /*
152 * Control structures are DMA'd to the SiS900 chip. We allocate them in
153 * a single clump that maps to a single DMA segment to make several things
154 * easier.
155 */
156 struct sip_control_data {
157 /*
158 * The transmit descriptors.
159 */
160 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC];
161
162 /*
163 * The receive descriptors.
164 */
165 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC];
166 };
167
168 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x)
169 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)])
170 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)])
171
172 /*
173 * Software state for transmit jobs.
174 */
175 struct sip_txsoft {
176 struct mbuf *txs_mbuf; /* head of our mbuf chain */
177 bus_dmamap_t txs_dmamap; /* our DMA map */
178 int txs_firstdesc; /* first descriptor in packet */
179 int txs_lastdesc; /* last descriptor in packet */
180 SIMPLEQ_ENTRY(sip_txsoft) txs_q;
181 };
182
183 SIMPLEQ_HEAD(sip_txsq, sip_txsoft);
184
185 /*
186 * Software state for receive jobs.
187 */
188 struct sip_rxsoft {
189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
190 bus_dmamap_t rxs_dmamap; /* our DMA map */
191 };
192
193 enum sip_attach_stage {
194 SIP_ATTACH_FIN = 0
195 , SIP_ATTACH_CREATE_RXMAP
196 , SIP_ATTACH_CREATE_TXMAP
197 , SIP_ATTACH_LOAD_MAP
198 , SIP_ATTACH_CREATE_MAP
199 , SIP_ATTACH_MAP_MEM
200 , SIP_ATTACH_ALLOC_MEM
201 , SIP_ATTACH_INTR
202 , SIP_ATTACH_MAP
203 };
204
205 /*
206 * Software state per device.
207 */
208 struct sip_softc {
209 device_t sc_dev; /* generic device information */
210 struct device_suspensor sc_suspensor;
211 struct pmf_qual sc_qual;
212
213 bus_space_tag_t sc_st; /* bus space tag */
214 bus_space_handle_t sc_sh; /* bus space handle */
215 bus_size_t sc_sz; /* bus space size */
216 bus_dma_tag_t sc_dmat; /* bus DMA tag */
217 pci_chipset_tag_t sc_pc;
218 bus_dma_segment_t sc_seg;
219 struct ethercom sc_ethercom; /* ethernet common data */
220
221 const struct sip_product *sc_model; /* which model are we? */
222 int sc_gigabit; /* 1: 83820, 0: other */
223 int sc_rev; /* chip revision */
224
225 void *sc_ih; /* interrupt cookie */
226
227 struct mii_data sc_mii; /* MII/media information */
228
229 callout_t sc_tick_ch; /* tick callout */
230
231 bus_dmamap_t sc_cddmamap; /* control data DMA map */
232 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
233
234 /*
235 * Software state for transmit and receive descriptors.
236 */
237 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN];
238 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC];
239
240 /*
241 * Control data structures.
242 */
243 struct sip_control_data *sc_control_data;
244 #define sc_txdescs sc_control_data->scd_txdescs
245 #define sc_rxdescs sc_control_data->scd_rxdescs
246
247 #ifdef SIP_EVENT_COUNTERS
248 /*
249 * Event counters.
250 */
251 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */
252 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */
253 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */
254 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */
255 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */
256 struct evcnt sc_ev_rxintr; /* Rx interrupts */
257 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */
258 struct evcnt sc_ev_rxpause; /* PAUSE received */
259 /* DP83820 only */
260 struct evcnt sc_ev_txpause; /* PAUSE transmitted */
261 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */
262 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */
263 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */
264 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */
265 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */
266 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */
267 #endif /* SIP_EVENT_COUNTERS */
268
269 u_int32_t sc_txcfg; /* prototype TXCFG register */
270 u_int32_t sc_rxcfg; /* prototype RXCFG register */
271 u_int32_t sc_imr; /* prototype IMR register */
272 u_int32_t sc_rfcr; /* prototype RFCR register */
273
274 u_int32_t sc_cfg; /* prototype CFG register */
275
276 u_int32_t sc_gpior; /* prototype GPIOR register */
277
278 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */
279 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */
280
281 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */
282
283 int sc_flowflags; /* 802.3x flow control flags */
284 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */
285 int sc_paused; /* paused indication */
286
287 int sc_txfree; /* number of free Tx descriptors */
288 int sc_txnext; /* next ready Tx descriptor */
289 int sc_txwin; /* Tx descriptors since last intr */
290
291 struct sip_txsq sc_txfreeq; /* free Tx descsofts */
292 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */
293
294 /* values of interface state at last init */
295 struct {
296 /* if_capenable */
297 uint64_t if_capenable;
298 /* ec_capenable */
299 int ec_capenable;
300 /* VLAN_ATTACHED */
301 int is_vlan;
302 } sc_prev;
303
304 short sc_if_flags;
305
306 int sc_rxptr; /* next ready Rx descriptor/descsoft */
307 int sc_rxdiscard;
308 int sc_rxlen;
309 struct mbuf *sc_rxhead;
310 struct mbuf *sc_rxtail;
311 struct mbuf **sc_rxtailp;
312
313 int sc_ntxdesc;
314 int sc_ntxdesc_mask;
315
316 int sc_nrxdesc_mask;
317
318 const struct sip_parm {
319 const struct sip_regs {
320 int r_rxcfg;
321 int r_txcfg;
322 } p_regs;
323
324 const struct sip_bits {
325 uint32_t b_txcfg_mxdma_8;
326 uint32_t b_txcfg_mxdma_16;
327 uint32_t b_txcfg_mxdma_32;
328 uint32_t b_txcfg_mxdma_64;
329 uint32_t b_txcfg_mxdma_128;
330 uint32_t b_txcfg_mxdma_256;
331 uint32_t b_txcfg_mxdma_512;
332 uint32_t b_txcfg_flth_mask;
333 uint32_t b_txcfg_drth_mask;
334
335 uint32_t b_rxcfg_mxdma_8;
336 uint32_t b_rxcfg_mxdma_16;
337 uint32_t b_rxcfg_mxdma_32;
338 uint32_t b_rxcfg_mxdma_64;
339 uint32_t b_rxcfg_mxdma_128;
340 uint32_t b_rxcfg_mxdma_256;
341 uint32_t b_rxcfg_mxdma_512;
342
343 uint32_t b_isr_txrcmp;
344 uint32_t b_isr_rxrcmp;
345 uint32_t b_isr_dperr;
346 uint32_t b_isr_sserr;
347 uint32_t b_isr_rmabt;
348 uint32_t b_isr_rtabt;
349
350 uint32_t b_cmdsts_size_mask;
351 } p_bits;
352 int p_filtmem;
353 int p_rxbuf_len;
354 bus_size_t p_tx_dmamap_size;
355 int p_ntxsegs;
356 int p_ntxsegs_alloc;
357 int p_nrxdesc;
358 } *sc_parm;
359
360 void (*sc_rxintr)(struct sip_softc *);
361
362 #if NRND > 0
363 rndsource_element_t rnd_source; /* random source */
364 #endif
365 };
366
367 #define sc_bits sc_parm->p_bits
368 #define sc_regs sc_parm->p_regs
369
370 static const struct sip_parm sip_parm = {
371 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM
372 , .p_rxbuf_len = MCLBYTES - 1 /* field width */
373 , .p_tx_dmamap_size = MCLBYTES
374 , .p_ntxsegs = 16
375 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC
376 , .p_nrxdesc = SIP_NRXDESC
377 , .p_bits = {
378 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */
379 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */
380 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */
381 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */
382 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */
383 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */
384 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */
385 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */
386 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */
387
388 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */
389 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */
390 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */
391 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */
392 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */
393 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */
394 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */
395
396 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */
397 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */
398 , .b_isr_dperr = 0x00800000 /* detected parity error */
399 , .b_isr_sserr = 0x00400000 /* signalled system error */
400 , .b_isr_rmabt = 0x00200000 /* received master abort */
401 , .b_isr_rtabt = 0x00100000 /* received target abort */
402 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK
403 }
404 , .p_regs = {
405 .r_rxcfg = OTHER_SIP_RXCFG,
406 .r_txcfg = OTHER_SIP_TXCFG
407 }
408 }, gsip_parm = {
409 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM
410 , .p_rxbuf_len = MCLBYTES - 8
411 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO
412 , .p_ntxsegs = 64
413 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC
414 , .p_nrxdesc = GSIP_NRXDESC
415 , .p_bits = {
416 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */
417 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */
418 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */
419 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */
420 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */
421 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */
422 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */
423 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */
424 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */
425
426 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */
427 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */
428 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */
429 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */
430 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */
431 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */
432 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */
433
434 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */
435 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */
436 , .b_isr_dperr = 0x00100000 /* detected parity error */
437 , .b_isr_sserr = 0x00080000 /* signalled system error */
438 , .b_isr_rmabt = 0x00040000 /* received master abort */
439 , .b_isr_rtabt = 0x00020000 /* received target abort */
440 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK
441 }
442 , .p_regs = {
443 .r_rxcfg = DP83820_SIP_RXCFG,
444 .r_txcfg = DP83820_SIP_TXCFG
445 }
446 };
447
448 static inline int
449 sip_nexttx(const struct sip_softc *sc, int x)
450 {
451 return (x + 1) & sc->sc_ntxdesc_mask;
452 }
453
454 static inline int
455 sip_nextrx(const struct sip_softc *sc, int x)
456 {
457 return (x + 1) & sc->sc_nrxdesc_mask;
458 }
459
460 /* 83820 only */
461 static inline void
462 sip_rxchain_reset(struct sip_softc *sc)
463 {
464 sc->sc_rxtailp = &sc->sc_rxhead;
465 *sc->sc_rxtailp = NULL;
466 sc->sc_rxlen = 0;
467 }
468
469 /* 83820 only */
470 static inline void
471 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m)
472 {
473 *sc->sc_rxtailp = sc->sc_rxtail = m;
474 sc->sc_rxtailp = &m->m_next;
475 }
476
477 #ifdef SIP_EVENT_COUNTERS
478 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++
479 #else
480 #define SIP_EVCNT_INCR(ev) /* nothing */
481 #endif
482
483 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x)))
484 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x)))
485
486 static inline void
487 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops)
488 {
489 int x, n;
490
491 x = x0;
492 n = n0;
493
494 /* If it will wrap around, sync to the end of the ring. */
495 if (x + n > sc->sc_ntxdesc) {
496 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
497 SIP_CDTXOFF(x), sizeof(struct sip_desc) *
498 (sc->sc_ntxdesc - x), ops);
499 n -= (sc->sc_ntxdesc - x);
500 x = 0;
501 }
502
503 /* Now sync whatever is left. */
504 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
505 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops);
506 }
507
508 static inline void
509 sip_cdrxsync(struct sip_softc *sc, int x, int ops)
510 {
511 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
512 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops);
513 }
514
515 #if 0
516 #ifdef DP83820
517 u_int32_t sipd_bufptr; /* pointer to DMA segment */
518 u_int32_t sipd_cmdsts; /* command/status word */
519 #else
520 u_int32_t sipd_cmdsts; /* command/status word */
521 u_int32_t sipd_bufptr; /* pointer to DMA segment */
522 #endif /* DP83820 */
523 #endif /* 0 */
524
525 static inline volatile uint32_t *
526 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd)
527 {
528 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0];
529 }
530
531 static inline volatile uint32_t *
532 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd)
533 {
534 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1];
535 }
536
537 static inline void
538 sip_init_rxdesc(struct sip_softc *sc, int x)
539 {
540 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x];
541 struct sip_desc *sipd = &sc->sc_rxdescs[x];
542
543 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x)));
544 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr);
545 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR |
546 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask));
547 sipd->sipd_extsts = 0;
548 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
549 }
550
551 #define SIP_CHIP_VERS(sc, v, p, r) \
552 ((sc)->sc_model->sip_vendor == (v) && \
553 (sc)->sc_model->sip_product == (p) && \
554 (sc)->sc_rev == (r))
555
556 #define SIP_CHIP_MODEL(sc, v, p) \
557 ((sc)->sc_model->sip_vendor == (v) && \
558 (sc)->sc_model->sip_product == (p))
559
560 #define SIP_SIS900_REV(sc, rev) \
561 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev))
562
563 #define SIP_TIMEOUT 1000
564
565 static int sip_ifflags_cb(struct ethercom *);
566 static void sipcom_start(struct ifnet *);
567 static void sipcom_watchdog(struct ifnet *);
568 static int sipcom_ioctl(struct ifnet *, u_long, void *);
569 static int sipcom_init(struct ifnet *);
570 static void sipcom_stop(struct ifnet *, int);
571
572 static bool sipcom_reset(struct sip_softc *);
573 static void sipcom_rxdrain(struct sip_softc *);
574 static int sipcom_add_rxbuf(struct sip_softc *, int);
575 static void sipcom_read_eeprom(struct sip_softc *, int, int,
576 u_int16_t *);
577 static void sipcom_tick(void *);
578
579 static void sipcom_sis900_set_filter(struct sip_softc *);
580 static void sipcom_dp83815_set_filter(struct sip_softc *);
581
582 static void sipcom_dp83820_read_macaddr(struct sip_softc *,
583 const struct pci_attach_args *, u_int8_t *);
584 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc);
585 static void sipcom_sis900_read_macaddr(struct sip_softc *,
586 const struct pci_attach_args *, u_int8_t *);
587 static void sipcom_dp83815_read_macaddr(struct sip_softc *,
588 const struct pci_attach_args *, u_int8_t *);
589
590 static int sipcom_intr(void *);
591 static void sipcom_txintr(struct sip_softc *);
592 static void sip_rxintr(struct sip_softc *);
593 static void gsip_rxintr(struct sip_softc *);
594
595 static int sipcom_dp83820_mii_readreg(device_t, int, int);
596 static void sipcom_dp83820_mii_writereg(device_t, int, int, int);
597 static void sipcom_dp83820_mii_statchg(device_t);
598
599 static int sipcom_sis900_mii_readreg(device_t, int, int);
600 static void sipcom_sis900_mii_writereg(device_t, int, int, int);
601 static void sipcom_sis900_mii_statchg(device_t);
602
603 static int sipcom_dp83815_mii_readreg(device_t, int, int);
604 static void sipcom_dp83815_mii_writereg(device_t, int, int, int);
605 static void sipcom_dp83815_mii_statchg(device_t);
606
607 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *);
608
609 static int sipcom_match(device_t, cfdata_t, void *);
610 static void sipcom_attach(device_t, device_t, void *);
611 static void sipcom_do_detach(device_t, enum sip_attach_stage);
612 static int sipcom_detach(device_t, int);
613 static bool sipcom_resume(device_t, pmf_qual_t);
614 static bool sipcom_suspend(device_t, pmf_qual_t);
615
616 int gsip_copy_small = 0;
617 int sip_copy_small = 0;
618
619 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc),
620 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL,
621 DVF_DETACH_SHUTDOWN);
622 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc),
623 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL,
624 DVF_DETACH_SHUTDOWN);
625
626 /*
627 * Descriptions of the variants of the SiS900.
628 */
629 struct sip_variant {
630 int (*sipv_mii_readreg)(device_t, int, int);
631 void (*sipv_mii_writereg)(device_t, int, int, int);
632 void (*sipv_mii_statchg)(device_t);
633 void (*sipv_set_filter)(struct sip_softc *);
634 void (*sipv_read_macaddr)(struct sip_softc *,
635 const struct pci_attach_args *, u_int8_t *);
636 };
637
638 static u_int32_t sipcom_mii_bitbang_read(device_t);
639 static void sipcom_mii_bitbang_write(device_t, u_int32_t);
640
641 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = {
642 sipcom_mii_bitbang_read,
643 sipcom_mii_bitbang_write,
644 {
645 EROMAR_MDIO, /* MII_BIT_MDO */
646 EROMAR_MDIO, /* MII_BIT_MDI */
647 EROMAR_MDC, /* MII_BIT_MDC */
648 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */
649 0, /* MII_BIT_DIR_PHY_HOST */
650 }
651 };
652
653 static const struct sip_variant sipcom_variant_dp83820 = {
654 sipcom_dp83820_mii_readreg,
655 sipcom_dp83820_mii_writereg,
656 sipcom_dp83820_mii_statchg,
657 sipcom_dp83815_set_filter,
658 sipcom_dp83820_read_macaddr,
659 };
660
661 static const struct sip_variant sipcom_variant_sis900 = {
662 sipcom_sis900_mii_readreg,
663 sipcom_sis900_mii_writereg,
664 sipcom_sis900_mii_statchg,
665 sipcom_sis900_set_filter,
666 sipcom_sis900_read_macaddr,
667 };
668
669 static const struct sip_variant sipcom_variant_dp83815 = {
670 sipcom_dp83815_mii_readreg,
671 sipcom_dp83815_mii_writereg,
672 sipcom_dp83815_mii_statchg,
673 sipcom_dp83815_set_filter,
674 sipcom_dp83815_read_macaddr,
675 };
676
677
678 /*
679 * Devices supported by this driver.
680 */
681 static const struct sip_product {
682 pci_vendor_id_t sip_vendor;
683 pci_product_id_t sip_product;
684 const char *sip_name;
685 const struct sip_variant *sip_variant;
686 int sip_gigabit;
687 } sipcom_products[] = {
688 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
689 "NatSemi DP83820 Gigabit Ethernet",
690 &sipcom_variant_dp83820, 1 },
691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900,
692 "SiS 900 10/100 Ethernet",
693 &sipcom_variant_sis900, 0 },
694 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016,
695 "SiS 7016 10/100 Ethernet",
696 &sipcom_variant_sis900, 0 },
697
698 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815,
699 "NatSemi DP83815 10/100 Ethernet",
700 &sipcom_variant_dp83815, 0 },
701
702 { 0, 0,
703 NULL,
704 NULL, 0 },
705 };
706
707 static const struct sip_product *
708 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit)
709 {
710 const struct sip_product *sip;
711
712 for (sip = sipcom_products; sip->sip_name != NULL; sip++) {
713 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor &&
714 PCI_PRODUCT(pa->pa_id) == sip->sip_product &&
715 sip->sip_gigabit == gigabit)
716 return sip;
717 }
718 return NULL;
719 }
720
721 /*
722 * I really hate stupid hardware vendors. There's a bit in the EEPROM
723 * which indicates if the card can do 64-bit data transfers. Unfortunately,
724 * several vendors of 32-bit cards fail to clear this bit in the EEPROM,
725 * which means we try to use 64-bit data transfers on those cards if we
726 * happen to be plugged into a 32-bit slot.
727 *
728 * What we do is use this table of cards known to be 64-bit cards. If
729 * you have a 64-bit card who's subsystem ID is not listed in this table,
730 * send the output of "pcictl dump ..." of the device to me so that your
731 * card will use the 64-bit data path when plugged into a 64-bit slot.
732 *
733 * -- Jason R. Thorpe <thorpej@NetBSD.org>
734 * June 30, 2002
735 */
736 static int
737 sipcom_check_64bit(const struct pci_attach_args *pa)
738 {
739 static const struct {
740 pci_vendor_id_t c64_vendor;
741 pci_product_id_t c64_product;
742 } card64[] = {
743 /* Asante GigaNIX */
744 { 0x128a, 0x0002 },
745
746 /* Accton EN1407-T, Planex GN-1000TE */
747 { 0x1113, 0x1407 },
748
749 /* Netgear GA-621 */
750 { 0x1385, 0x621a },
751
752 /* SMC EZ Card */
753 { 0x10b8, 0x9462 },
754
755 { 0, 0}
756 };
757 pcireg_t subsys;
758 int i;
759
760 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
761
762 for (i = 0; card64[i].c64_vendor != 0; i++) {
763 if (PCI_VENDOR(subsys) == card64[i].c64_vendor &&
764 PCI_PRODUCT(subsys) == card64[i].c64_product)
765 return (1);
766 }
767
768 return (0);
769 }
770
771 static int
772 sipcom_match(device_t parent, cfdata_t cf, void *aux)
773 {
774 struct pci_attach_args *pa = aux;
775
776 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL)
777 return 1;
778
779 return 0;
780 }
781
782 static void
783 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa)
784 {
785 u_int32_t reg;
786 int i;
787
788 /*
789 * Cause the chip to load configuration data from the EEPROM.
790 */
791 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN);
792 for (i = 0; i < 10000; i++) {
793 delay(10);
794 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
795 PTSCR_EELOAD_EN) == 0)
796 break;
797 }
798 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
799 PTSCR_EELOAD_EN) {
800 printf("%s: timeout loading configuration from EEPROM\n",
801 device_xname(sc->sc_dev));
802 return;
803 }
804
805 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR);
806
807 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG);
808 if (reg & CFG_PCI64_DET) {
809 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev));
810 /*
811 * Check to see if this card is 64-bit. If so, enable 64-bit
812 * data transfers.
813 *
814 * We can't use the DATA64_EN bit in the EEPROM, because
815 * vendors of 32-bit cards fail to clear that bit in many
816 * cases (yet the card still detects that it's in a 64-bit
817 * slot; go figure).
818 */
819 if (sipcom_check_64bit(pa)) {
820 sc->sc_cfg |= CFG_DATA64_EN;
821 printf(", using 64-bit data transfers");
822 }
823 printf("\n");
824 }
825
826 /*
827 * XXX Need some PCI flags indicating support for
828 * XXX 64-bit addressing.
829 */
830 #if 0
831 if (reg & CFG_M64ADDR)
832 sc->sc_cfg |= CFG_M64ADDR;
833 if (reg & CFG_T64ADDR)
834 sc->sc_cfg |= CFG_T64ADDR;
835 #endif
836
837 if (reg & (CFG_TBI_EN|CFG_EXT_125)) {
838 const char *sep = "";
839 printf("%s: using ", device_xname(sc->sc_dev));
840 if (reg & CFG_EXT_125) {
841 sc->sc_cfg |= CFG_EXT_125;
842 printf("%s125MHz clock", sep);
843 sep = ", ";
844 }
845 if (reg & CFG_TBI_EN) {
846 sc->sc_cfg |= CFG_TBI_EN;
847 printf("%sten-bit interface", sep);
848 sep = ", ";
849 }
850 printf("\n");
851 }
852 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 ||
853 (reg & CFG_MRM_DIS) != 0)
854 sc->sc_cfg |= CFG_MRM_DIS;
855 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 ||
856 (reg & CFG_MWI_DIS) != 0)
857 sc->sc_cfg |= CFG_MWI_DIS;
858
859 /*
860 * Use the extended descriptor format on the DP83820. This
861 * gives us an interface to VLAN tagging and IPv4/TCP/UDP
862 * checksumming.
863 */
864 sc->sc_cfg |= CFG_EXTSTS_EN;
865 }
866
867 static int
868 sipcom_detach(device_t self, int flags)
869 {
870 int s;
871
872 s = splnet();
873 sipcom_do_detach(self, SIP_ATTACH_FIN);
874 splx(s);
875
876 return 0;
877 }
878
879 static void
880 sipcom_do_detach(device_t self, enum sip_attach_stage stage)
881 {
882 int i;
883 struct sip_softc *sc = device_private(self);
884 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
885
886 /*
887 * Free any resources we've allocated during attach.
888 * Do this in reverse order and fall through.
889 */
890 switch (stage) {
891 case SIP_ATTACH_FIN:
892 sipcom_stop(ifp, 1);
893 pmf_device_deregister(self);
894 #ifdef SIP_EVENT_COUNTERS
895 /*
896 * Attach event counters.
897 */
898 evcnt_detach(&sc->sc_ev_txforceintr);
899 evcnt_detach(&sc->sc_ev_txdstall);
900 evcnt_detach(&sc->sc_ev_txsstall);
901 evcnt_detach(&sc->sc_ev_hiberr);
902 evcnt_detach(&sc->sc_ev_rxintr);
903 evcnt_detach(&sc->sc_ev_txiintr);
904 evcnt_detach(&sc->sc_ev_txdintr);
905 if (!sc->sc_gigabit) {
906 evcnt_detach(&sc->sc_ev_rxpause);
907 } else {
908 evcnt_detach(&sc->sc_ev_txudpsum);
909 evcnt_detach(&sc->sc_ev_txtcpsum);
910 evcnt_detach(&sc->sc_ev_txipsum);
911 evcnt_detach(&sc->sc_ev_rxudpsum);
912 evcnt_detach(&sc->sc_ev_rxtcpsum);
913 evcnt_detach(&sc->sc_ev_rxipsum);
914 evcnt_detach(&sc->sc_ev_txpause);
915 evcnt_detach(&sc->sc_ev_rxpause);
916 }
917 #endif /* SIP_EVENT_COUNTERS */
918
919 #if NRND > 0
920 rnd_detach_source(&sc->rnd_source);
921 #endif
922
923 ether_ifdetach(ifp);
924 if_detach(ifp);
925 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
926
927 /*FALLTHROUGH*/
928 case SIP_ATTACH_CREATE_RXMAP:
929 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
930 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
931 bus_dmamap_destroy(sc->sc_dmat,
932 sc->sc_rxsoft[i].rxs_dmamap);
933 }
934 /*FALLTHROUGH*/
935 case SIP_ATTACH_CREATE_TXMAP:
936 for (i = 0; i < SIP_TXQUEUELEN; i++) {
937 if (sc->sc_txsoft[i].txs_dmamap != NULL)
938 bus_dmamap_destroy(sc->sc_dmat,
939 sc->sc_txsoft[i].txs_dmamap);
940 }
941 /*FALLTHROUGH*/
942 case SIP_ATTACH_LOAD_MAP:
943 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
944 /*FALLTHROUGH*/
945 case SIP_ATTACH_CREATE_MAP:
946 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
947 /*FALLTHROUGH*/
948 case SIP_ATTACH_MAP_MEM:
949 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
950 sizeof(struct sip_control_data));
951 /*FALLTHROUGH*/
952 case SIP_ATTACH_ALLOC_MEM:
953 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1);
954 /* FALLTHROUGH*/
955 case SIP_ATTACH_INTR:
956 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
957 /* FALLTHROUGH*/
958 case SIP_ATTACH_MAP:
959 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
960 break;
961 default:
962 break;
963 }
964 return;
965 }
966
967 static bool
968 sipcom_resume(device_t self, pmf_qual_t qual)
969 {
970 struct sip_softc *sc = device_private(self);
971
972 return sipcom_reset(sc);
973 }
974
975 static bool
976 sipcom_suspend(device_t self, pmf_qual_t qual)
977 {
978 struct sip_softc *sc = device_private(self);
979
980 sipcom_rxdrain(sc);
981 return true;
982 }
983
984 static void
985 sipcom_attach(device_t parent, device_t self, void *aux)
986 {
987 struct sip_softc *sc = device_private(self);
988 struct pci_attach_args *pa = aux;
989 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
990 pci_chipset_tag_t pc = pa->pa_pc;
991 pci_intr_handle_t ih;
992 const char *intrstr = NULL;
993 bus_space_tag_t iot, memt;
994 bus_space_handle_t ioh, memh;
995 bus_size_t iosz, memsz;
996 int ioh_valid, memh_valid;
997 int i, rseg, error;
998 const struct sip_product *sip;
999 u_int8_t enaddr[ETHER_ADDR_LEN];
1000 pcireg_t csr;
1001 pcireg_t memtype;
1002 bus_size_t tx_dmamap_size;
1003 int ntxsegs_alloc;
1004 cfdata_t cf = device_cfdata(self);
1005
1006 callout_init(&sc->sc_tick_ch, 0);
1007
1008 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0);
1009 if (sip == NULL) {
1010 printf("\n");
1011 panic("%s: impossible", __func__);
1012 }
1013 sc->sc_dev = self;
1014 sc->sc_gigabit = sip->sip_gigabit;
1015 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual);
1016 sc->sc_pc = pc;
1017
1018 if (sc->sc_gigabit) {
1019 sc->sc_rxintr = gsip_rxintr;
1020 sc->sc_parm = &gsip_parm;
1021 } else {
1022 sc->sc_rxintr = sip_rxintr;
1023 sc->sc_parm = &sip_parm;
1024 }
1025 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size;
1026 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc;
1027 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc;
1028 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1;
1029 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1;
1030
1031 sc->sc_rev = PCI_REVISION(pa->pa_class);
1032
1033 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev);
1034
1035 sc->sc_model = sip;
1036
1037 /*
1038 * XXX Work-around broken PXE firmware on some boards.
1039 *
1040 * The DP83815 shares an address decoder with the MEM BAR
1041 * and the ROM BAR. Make sure the ROM BAR is disabled,
1042 * so that memory mapped access works.
1043 */
1044 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
1045 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
1046 ~PCI_MAPREG_ROM_ENABLE);
1047
1048 /*
1049 * Map the device.
1050 */
1051 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA,
1052 PCI_MAPREG_TYPE_IO, 0,
1053 &iot, &ioh, NULL, &iosz) == 0);
1054 if (sc->sc_gigabit) {
1055 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA);
1056 switch (memtype) {
1057 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1058 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
1060 memtype, 0, &memt, &memh, NULL, &memsz) == 0);
1061 break;
1062 default:
1063 memh_valid = 0;
1064 }
1065 } else {
1066 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
1067 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
1068 &memt, &memh, NULL, &memsz) == 0);
1069 }
1070
1071 if (memh_valid) {
1072 sc->sc_st = memt;
1073 sc->sc_sh = memh;
1074 sc->sc_sz = memsz;
1075 } else if (ioh_valid) {
1076 sc->sc_st = iot;
1077 sc->sc_sh = ioh;
1078 sc->sc_sz = iosz;
1079 } else {
1080 printf("%s: unable to map device registers\n",
1081 device_xname(sc->sc_dev));
1082 return;
1083 }
1084
1085 sc->sc_dmat = pa->pa_dmat;
1086
1087 /*
1088 * Make sure bus mastering is enabled. Also make sure
1089 * Write/Invalidate is enabled if we're allowed to use it.
1090 */
1091 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1092 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
1093 csr |= PCI_COMMAND_INVALIDATE_ENABLE;
1094 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
1095 csr | PCI_COMMAND_MASTER_ENABLE);
1096
1097 /* power up chip */
1098 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null);
1099 if (error != 0 && error != EOPNOTSUPP) {
1100 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
1101 return;
1102 }
1103
1104 /*
1105 * Map and establish our interrupt.
1106 */
1107 if (pci_intr_map(pa, &ih)) {
1108 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
1109 return;
1110 }
1111 intrstr = pci_intr_string(pc, ih);
1112 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc);
1113 if (sc->sc_ih == NULL) {
1114 aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
1115 if (intrstr != NULL)
1116 aprint_error(" at %s", intrstr);
1117 aprint_error("\n");
1118 return sipcom_do_detach(self, SIP_ATTACH_MAP);
1119 }
1120 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
1121
1122 SIMPLEQ_INIT(&sc->sc_txfreeq);
1123 SIMPLEQ_INIT(&sc->sc_txdirtyq);
1124
1125 /*
1126 * Allocate the control data structures, and create and load the
1127 * DMA map for it.
1128 */
1129 if ((error = bus_dmamem_alloc(sc->sc_dmat,
1130 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1,
1131 &rseg, 0)) != 0) {
1132 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n",
1133 error);
1134 return sipcom_do_detach(self, SIP_ATTACH_INTR);
1135 }
1136
1137 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg,
1138 sizeof(struct sip_control_data), (void **)&sc->sc_control_data,
1139 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) {
1140 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n",
1141 error);
1142 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM);
1143 }
1144
1145 if ((error = bus_dmamap_create(sc->sc_dmat,
1146 sizeof(struct sip_control_data), 1,
1147 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
1148 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
1149 "error = %d\n", error);
1150 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM);
1151 }
1152
1153 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
1154 sc->sc_control_data, sizeof(struct sip_control_data), NULL,
1155 0)) != 0) {
1156 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n",
1157 error);
1158 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP);
1159 }
1160
1161 /*
1162 * Create the transmit buffer DMA maps.
1163 */
1164 for (i = 0; i < SIP_TXQUEUELEN; i++) {
1165 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size,
1166 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0,
1167 &sc->sc_txsoft[i].txs_dmamap)) != 0) {
1168 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, "
1169 "error = %d\n", i, error);
1170 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP);
1171 }
1172 }
1173
1174 /*
1175 * Create the receive buffer DMA maps.
1176 */
1177 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
1178 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1179 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
1180 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, "
1181 "error = %d\n", i, error);
1182 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP);
1183 }
1184 sc->sc_rxsoft[i].rxs_mbuf = NULL;
1185 }
1186
1187 /*
1188 * Reset the chip to a known state.
1189 */
1190 sipcom_reset(sc);
1191
1192 /*
1193 * Read the Ethernet address from the EEPROM. This might
1194 * also fetch other stuff from the EEPROM and stash it
1195 * in the softc.
1196 */
1197 sc->sc_cfg = 0;
1198 if (!sc->sc_gigabit) {
1199 if (SIP_SIS900_REV(sc,SIS_REV_635) ||
1200 SIP_SIS900_REV(sc,SIS_REV_900B))
1201 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT);
1202
1203 if (SIP_SIS900_REV(sc,SIS_REV_635) ||
1204 SIP_SIS900_REV(sc,SIS_REV_960) ||
1205 SIP_SIS900_REV(sc,SIS_REV_900B))
1206 sc->sc_cfg |=
1207 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) &
1208 CFG_EDBMASTEN);
1209 }
1210
1211 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr);
1212
1213 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev),
1214 ether_sprintf(enaddr));
1215
1216 /*
1217 * Initialize the configuration register: aggressive PCI
1218 * bus request algorithm, default backoff, default OW timer,
1219 * default parity error detection.
1220 *
1221 * NOTE: "Big endian mode" is useless on the SiS900 and
1222 * friends -- it affects packet data, not descriptors.
1223 */
1224 if (sc->sc_gigabit)
1225 sipcom_dp83820_attach(sc, pa);
1226
1227 /*
1228 * Initialize our media structures and probe the MII.
1229 */
1230 sc->sc_mii.mii_ifp = ifp;
1231 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg;
1232 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg;
1233 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg;
1234 sc->sc_ethercom.ec_mii = &sc->sc_mii;
1235 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange,
1236 sipcom_mediastatus);
1237
1238 /*
1239 * XXX We cannot handle flow control on the DP83815.
1240 */
1241 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815))
1242 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1243 MII_OFFSET_ANY, 0);
1244 else
1245 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1246 MII_OFFSET_ANY, MIIF_DOPAUSE);
1247 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
1248 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
1249 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
1250 } else
1251 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
1252
1253 ifp = &sc->sc_ethercom.ec_if;
1254 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
1255 ifp->if_softc = sc;
1256 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1257 sc->sc_if_flags = ifp->if_flags;
1258 ifp->if_ioctl = sipcom_ioctl;
1259 ifp->if_start = sipcom_start;
1260 ifp->if_watchdog = sipcom_watchdog;
1261 ifp->if_init = sipcom_init;
1262 ifp->if_stop = sipcom_stop;
1263 IFQ_SET_READY(&ifp->if_snd);
1264
1265 /*
1266 * We can support 802.1Q VLAN-sized frames.
1267 */
1268 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
1269
1270 if (sc->sc_gigabit) {
1271 /*
1272 * And the DP83820 can do VLAN tagging in hardware, and
1273 * support the jumbo Ethernet MTU.
1274 */
1275 sc->sc_ethercom.ec_capabilities |=
1276 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU;
1277
1278 /*
1279 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums
1280 * in hardware.
1281 */
1282 ifp->if_capabilities |=
1283 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1284 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1285 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
1286 }
1287
1288 /*
1289 * Attach the interface.
1290 */
1291 if_attach(ifp);
1292 ether_ifattach(ifp, enaddr);
1293 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb);
1294 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable;
1295 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom);
1296 sc->sc_prev.if_capenable = ifp->if_capenable;
1297 #if NRND > 0
1298 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
1299 RND_TYPE_NET, 0);
1300 #endif
1301
1302 /*
1303 * The number of bytes that must be available in
1304 * the Tx FIFO before the bus master can DMA more
1305 * data into the FIFO.
1306 */
1307 sc->sc_tx_fill_thresh = 64 / 32;
1308
1309 /*
1310 * Start at a drain threshold of 512 bytes. We will
1311 * increase it if a DMA underrun occurs.
1312 *
1313 * XXX The minimum value of this variable should be
1314 * tuned. We may be able to improve performance
1315 * by starting with a lower value. That, however,
1316 * may trash the first few outgoing packets if the
1317 * PCI bus is saturated.
1318 */
1319 if (sc->sc_gigabit)
1320 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */
1321 else
1322 sc->sc_tx_drain_thresh = 1504 / 32;
1323
1324 /*
1325 * Initialize the Rx FIFO drain threshold.
1326 *
1327 * This is in units of 8 bytes.
1328 *
1329 * We should never set this value lower than 2; 14 bytes are
1330 * required to filter the packet.
1331 */
1332 sc->sc_rx_drain_thresh = 128 / 8;
1333
1334 #ifdef SIP_EVENT_COUNTERS
1335 /*
1336 * Attach event counters.
1337 */
1338 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
1339 NULL, device_xname(sc->sc_dev), "txsstall");
1340 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
1341 NULL, device_xname(sc->sc_dev), "txdstall");
1342 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR,
1343 NULL, device_xname(sc->sc_dev), "txforceintr");
1344 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR,
1345 NULL, device_xname(sc->sc_dev), "txdintr");
1346 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR,
1347 NULL, device_xname(sc->sc_dev), "txiintr");
1348 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
1349 NULL, device_xname(sc->sc_dev), "rxintr");
1350 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR,
1351 NULL, device_xname(sc->sc_dev), "hiberr");
1352 if (!sc->sc_gigabit) {
1353 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR,
1354 NULL, device_xname(sc->sc_dev), "rxpause");
1355 } else {
1356 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC,
1357 NULL, device_xname(sc->sc_dev), "rxpause");
1358 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC,
1359 NULL, device_xname(sc->sc_dev), "txpause");
1360 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
1361 NULL, device_xname(sc->sc_dev), "rxipsum");
1362 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,
1363 NULL, device_xname(sc->sc_dev), "rxtcpsum");
1364 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,
1365 NULL, device_xname(sc->sc_dev), "rxudpsum");
1366 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
1367 NULL, device_xname(sc->sc_dev), "txipsum");
1368 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
1369 NULL, device_xname(sc->sc_dev), "txtcpsum");
1370 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
1371 NULL, device_xname(sc->sc_dev), "txudpsum");
1372 }
1373 #endif /* SIP_EVENT_COUNTERS */
1374
1375 if (pmf_device_register(self, sipcom_suspend, sipcom_resume))
1376 pmf_class_network_register(self, ifp);
1377 else
1378 aprint_error_dev(self, "couldn't establish power handler\n");
1379 }
1380
1381 static inline void
1382 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0,
1383 uint64_t capenable)
1384 {
1385 struct m_tag *mtag;
1386 u_int32_t extsts;
1387 #ifdef DEBUG
1388 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1389 #endif
1390 /*
1391 * If VLANs are enabled and the packet has a VLAN tag, set
1392 * up the descriptor to encapsulate the packet for us.
1393 *
1394 * This apparently has to be on the last descriptor of
1395 * the packet.
1396 */
1397
1398 /*
1399 * Byte swapping is tricky. We need to provide the tag
1400 * in a network byte order. On a big-endian machine,
1401 * the byteorder is correct, but we need to swap it
1402 * anyway, because this will be undone by the outside
1403 * htole32(). That's why there must be an
1404 * unconditional swap instead of htons() inside.
1405 */
1406 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
1407 sc->sc_txdescs[lasttx].sipd_extsts |=
1408 htole32(EXTSTS_VPKT |
1409 (bswap16(VLAN_TAG_VALUE(mtag)) &
1410 EXTSTS_VTCI));
1411 }
1412
1413 /*
1414 * If the upper-layer has requested IPv4/TCPv4/UDPv4
1415 * checksumming, set up the descriptor to do this work
1416 * for us.
1417 *
1418 * This apparently has to be on the first descriptor of
1419 * the packet.
1420 *
1421 * Byte-swap constants so the compiler can optimize.
1422 */
1423 extsts = 0;
1424 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
1425 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx);
1426 SIP_EVCNT_INCR(&sc->sc_ev_txipsum);
1427 extsts |= htole32(EXTSTS_IPPKT);
1428 }
1429 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
1430 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx);
1431 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum);
1432 extsts |= htole32(EXTSTS_TCPPKT);
1433 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
1434 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx);
1435 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum);
1436 extsts |= htole32(EXTSTS_UDPPKT);
1437 }
1438 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts;
1439 }
1440
1441 /*
1442 * sip_start: [ifnet interface function]
1443 *
1444 * Start packet transmission on the interface.
1445 */
1446 static void
1447 sipcom_start(struct ifnet *ifp)
1448 {
1449 struct sip_softc *sc = ifp->if_softc;
1450 struct mbuf *m0;
1451 struct mbuf *m;
1452 struct sip_txsoft *txs;
1453 bus_dmamap_t dmamap;
1454 int error, nexttx, lasttx, seg;
1455 int ofree = sc->sc_txfree;
1456 #if 0
1457 int firsttx = sc->sc_txnext;
1458 #endif
1459
1460 /*
1461 * If we've been told to pause, don't transmit any more packets.
1462 */
1463 if (!sc->sc_gigabit && sc->sc_paused)
1464 ifp->if_flags |= IFF_OACTIVE;
1465
1466 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1467 return;
1468
1469 /*
1470 * Loop through the send queue, setting up transmit descriptors
1471 * until we drain the queue, or use up all available transmit
1472 * descriptors.
1473 */
1474 for (;;) {
1475 /* Get a work queue entry. */
1476 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1477 SIP_EVCNT_INCR(&sc->sc_ev_txsstall);
1478 break;
1479 }
1480
1481 /*
1482 * Grab a packet off the queue.
1483 */
1484 IFQ_POLL(&ifp->if_snd, m0);
1485 if (m0 == NULL)
1486 break;
1487 m = NULL;
1488
1489 dmamap = txs->txs_dmamap;
1490
1491 /*
1492 * Load the DMA map. If this fails, the packet either
1493 * didn't fit in the alloted number of segments, or we
1494 * were short on resources.
1495 */
1496 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
1497 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1498 /* In the non-gigabit case, we'll copy and try again. */
1499 if (error != 0 && !sc->sc_gigabit) {
1500 MGETHDR(m, M_DONTWAIT, MT_DATA);
1501 if (m == NULL) {
1502 printf("%s: unable to allocate Tx mbuf\n",
1503 device_xname(sc->sc_dev));
1504 break;
1505 }
1506 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
1507 if (m0->m_pkthdr.len > MHLEN) {
1508 MCLGET(m, M_DONTWAIT);
1509 if ((m->m_flags & M_EXT) == 0) {
1510 printf("%s: unable to allocate Tx "
1511 "cluster\n", device_xname(sc->sc_dev));
1512 m_freem(m);
1513 break;
1514 }
1515 }
1516 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
1517 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
1518 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
1519 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1520 if (error) {
1521 printf("%s: unable to load Tx buffer, "
1522 "error = %d\n", device_xname(sc->sc_dev), error);
1523 break;
1524 }
1525 } else if (error == EFBIG) {
1526 /*
1527 * For the too-many-segments case, we simply
1528 * report an error and drop the packet,
1529 * since we can't sanely copy a jumbo packet
1530 * to a single buffer.
1531 */
1532 printf("%s: Tx packet consumes too many "
1533 "DMA segments, dropping...\n", device_xname(sc->sc_dev));
1534 IFQ_DEQUEUE(&ifp->if_snd, m0);
1535 m_freem(m0);
1536 continue;
1537 } else if (error != 0) {
1538 /*
1539 * Short on resources, just stop for now.
1540 */
1541 break;
1542 }
1543
1544 /*
1545 * Ensure we have enough descriptors free to describe
1546 * the packet. Note, we always reserve one descriptor
1547 * at the end of the ring as a termination point, to
1548 * prevent wrap-around.
1549 */
1550 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) {
1551 /*
1552 * Not enough free descriptors to transmit this
1553 * packet. We haven't committed anything yet,
1554 * so just unload the DMA map, put the packet
1555 * back on the queue, and punt. Notify the upper
1556 * layer that there are not more slots left.
1557 *
1558 * XXX We could allocate an mbuf and copy, but
1559 * XXX is it worth it?
1560 */
1561 ifp->if_flags |= IFF_OACTIVE;
1562 bus_dmamap_unload(sc->sc_dmat, dmamap);
1563 if (m != NULL)
1564 m_freem(m);
1565 SIP_EVCNT_INCR(&sc->sc_ev_txdstall);
1566 break;
1567 }
1568
1569 IFQ_DEQUEUE(&ifp->if_snd, m0);
1570 if (m != NULL) {
1571 m_freem(m0);
1572 m0 = m;
1573 }
1574
1575 /*
1576 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1577 */
1578
1579 /* Sync the DMA map. */
1580 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1581 BUS_DMASYNC_PREWRITE);
1582
1583 /*
1584 * Initialize the transmit descriptors.
1585 */
1586 for (nexttx = lasttx = sc->sc_txnext, seg = 0;
1587 seg < dmamap->dm_nsegs;
1588 seg++, nexttx = sip_nexttx(sc, nexttx)) {
1589 /*
1590 * If this is the first descriptor we're
1591 * enqueueing, don't set the OWN bit just
1592 * yet. That could cause a race condition.
1593 * We'll do it below.
1594 */
1595 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) =
1596 htole32(dmamap->dm_segs[seg].ds_addr);
1597 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) =
1598 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) |
1599 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len);
1600 sc->sc_txdescs[nexttx].sipd_extsts = 0;
1601 lasttx = nexttx;
1602 }
1603
1604 /* Clear the MORE bit on the last segment. */
1605 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &=
1606 htole32(~CMDSTS_MORE);
1607
1608 /*
1609 * If we're in the interrupt delay window, delay the
1610 * interrupt.
1611 */
1612 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) {
1613 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr);
1614 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |=
1615 htole32(CMDSTS_INTR);
1616 sc->sc_txwin = 0;
1617 }
1618
1619 if (sc->sc_gigabit)
1620 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable);
1621
1622 /* Sync the descriptors we're using. */
1623 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs,
1624 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1625
1626 /*
1627 * The entire packet is set up. Give the first descrptor
1628 * to the chip now.
1629 */
1630 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |=
1631 htole32(CMDSTS_OWN);
1632 sip_cdtxsync(sc, sc->sc_txnext, 1,
1633 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1634
1635 /*
1636 * Store a pointer to the packet so we can free it later,
1637 * and remember what txdirty will be once the packet is
1638 * done.
1639 */
1640 txs->txs_mbuf = m0;
1641 txs->txs_firstdesc = sc->sc_txnext;
1642 txs->txs_lastdesc = lasttx;
1643
1644 /* Advance the tx pointer. */
1645 sc->sc_txfree -= dmamap->dm_nsegs;
1646 sc->sc_txnext = nexttx;
1647
1648 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1649 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1650
1651 #if NBPFILTER > 0
1652 /*
1653 * Pass the packet to any BPF listeners.
1654 */
1655 if (ifp->if_bpf)
1656 bpf_mtap(ifp->if_bpf, m0);
1657 #endif /* NBPFILTER > 0 */
1658 }
1659
1660 if (txs == NULL || sc->sc_txfree == 0) {
1661 /* No more slots left; notify upper layer. */
1662 ifp->if_flags |= IFF_OACTIVE;
1663 }
1664
1665 if (sc->sc_txfree != ofree) {
1666 /*
1667 * Start the transmit process. Note, the manual says
1668 * that if there are no pending transmissions in the
1669 * chip's internal queue (indicated by TXE being clear),
1670 * then the driver software must set the TXDP to the
1671 * first descriptor to be transmitted. However, if we
1672 * do this, it causes serious performance degredation on
1673 * the DP83820 under load, not setting TXDP doesn't seem
1674 * to adversely affect the SiS 900 or DP83815.
1675 *
1676 * Well, I guess it wouldn't be the first time a manual
1677 * has lied -- and they could be speaking of the NULL-
1678 * terminated descriptor list case, rather than OWN-
1679 * terminated rings.
1680 */
1681 #if 0
1682 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) &
1683 CR_TXE) == 0) {
1684 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP,
1685 SIP_CDTXADDR(sc, firsttx));
1686 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
1687 }
1688 #else
1689 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
1690 #endif
1691
1692 /* Set a watchdog timer in case the chip flakes out. */
1693 /* Gigabit autonegotiation takes 5 seconds. */
1694 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5;
1695 }
1696 }
1697
1698 /*
1699 * sip_watchdog: [ifnet interface function]
1700 *
1701 * Watchdog timer handler.
1702 */
1703 static void
1704 sipcom_watchdog(struct ifnet *ifp)
1705 {
1706 struct sip_softc *sc = ifp->if_softc;
1707
1708 /*
1709 * The chip seems to ignore the CMDSTS_INTR bit sometimes!
1710 * If we get a timeout, try and sweep up transmit descriptors.
1711 * If we manage to sweep them all up, ignore the lack of
1712 * interrupt.
1713 */
1714 sipcom_txintr(sc);
1715
1716 if (sc->sc_txfree != sc->sc_ntxdesc) {
1717 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1718 ifp->if_oerrors++;
1719
1720 /* Reset the interface. */
1721 (void) sipcom_init(ifp);
1722 } else if (ifp->if_flags & IFF_DEBUG)
1723 printf("%s: recovered from device timeout\n",
1724 device_xname(sc->sc_dev));
1725
1726 /* Try to get more packets going. */
1727 sipcom_start(ifp);
1728 }
1729
1730 /* If the interface is up and running, only modify the receive
1731 * filter when setting promiscuous or debug mode. Otherwise fall
1732 * through to ether_ioctl, which will reset the chip.
1733 */
1734 static int
1735 sip_ifflags_cb(struct ethercom *ec)
1736 {
1737 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \
1738 == (sc)->sc_ethercom.ec_capenable) \
1739 && ((sc)->sc_prev.is_vlan == \
1740 VLAN_ATTACHED(&(sc)->sc_ethercom) ))
1741 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable)
1742 struct ifnet *ifp = &ec->ec_if;
1743 struct sip_softc *sc = ifp->if_softc;
1744 int change = ifp->if_flags ^ sc->sc_if_flags;
1745
1746 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) ||
1747 !COMPARE_IC(sc, ifp))
1748 return ENETRESET;
1749 /* Set up the receive filter. */
1750 (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1751 return 0;
1752 }
1753
1754 /*
1755 * sip_ioctl: [ifnet interface function]
1756 *
1757 * Handle control requests from the operator.
1758 */
1759 static int
1760 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1761 {
1762 struct sip_softc *sc = ifp->if_softc;
1763 struct ifreq *ifr = (struct ifreq *)data;
1764 int s, error;
1765
1766 s = splnet();
1767
1768 switch (cmd) {
1769 case SIOCSIFMEDIA:
1770 /* Flow control requires full-duplex mode. */
1771 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
1772 (ifr->ifr_media & IFM_FDX) == 0)
1773 ifr->ifr_media &= ~IFM_ETH_FMASK;
1774
1775 /* XXX */
1776 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815))
1777 ifr->ifr_media &= ~IFM_ETH_FMASK;
1778 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
1779 if (sc->sc_gigabit &&
1780 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
1781 /* We can do both TXPAUSE and RXPAUSE. */
1782 ifr->ifr_media |=
1783 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1784 } else if (ifr->ifr_media & IFM_FLOW) {
1785 /*
1786 * Both TXPAUSE and RXPAUSE must be set.
1787 * (SiS900 and DP83815 don't have PAUSE_ASYM
1788 * feature.)
1789 *
1790 * XXX Can SiS900 and DP83815 send PAUSE?
1791 */
1792 ifr->ifr_media |=
1793 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
1794 }
1795 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
1796 }
1797 /*FALLTHROUGH*/
1798 default:
1799 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1800 break;
1801
1802 error = 0;
1803
1804 if (cmd == SIOCSIFCAP)
1805 error = (*ifp->if_init)(ifp);
1806 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1807 ;
1808 else if (ifp->if_flags & IFF_RUNNING) {
1809 /*
1810 * Multicast list has changed; set the hardware filter
1811 * accordingly.
1812 */
1813 (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
1814 }
1815 break;
1816 }
1817
1818 /* Try to get more packets going. */
1819 sipcom_start(ifp);
1820
1821 sc->sc_if_flags = ifp->if_flags;
1822 splx(s);
1823 return (error);
1824 }
1825
1826 /*
1827 * sip_intr:
1828 *
1829 * Interrupt service routine.
1830 */
1831 static int
1832 sipcom_intr(void *arg)
1833 {
1834 struct sip_softc *sc = arg;
1835 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1836 u_int32_t isr;
1837 int handled = 0;
1838
1839 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
1840 return 0;
1841
1842 /* Disable interrupts. */
1843 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0);
1844
1845 for (;;) {
1846 /* Reading clears interrupt. */
1847 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR);
1848 if ((isr & sc->sc_imr) == 0)
1849 break;
1850
1851 #if NRND > 0
1852 if (RND_ENABLED(&sc->rnd_source))
1853 rnd_add_uint32(&sc->rnd_source, isr);
1854 #endif
1855
1856 handled = 1;
1857
1858 if ((ifp->if_flags & IFF_RUNNING) == 0)
1859 break;
1860
1861 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) {
1862 SIP_EVCNT_INCR(&sc->sc_ev_rxintr);
1863
1864 /* Grab any new packets. */
1865 (*sc->sc_rxintr)(sc);
1866
1867 if (isr & ISR_RXORN) {
1868 printf("%s: receive FIFO overrun\n",
1869 device_xname(sc->sc_dev));
1870
1871 /* XXX adjust rx_drain_thresh? */
1872 }
1873
1874 if (isr & ISR_RXIDLE) {
1875 printf("%s: receive ring overrun\n",
1876 device_xname(sc->sc_dev));
1877
1878 /* Get the receive process going again. */
1879 bus_space_write_4(sc->sc_st, sc->sc_sh,
1880 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
1881 bus_space_write_4(sc->sc_st, sc->sc_sh,
1882 SIP_CR, CR_RXE);
1883 }
1884 }
1885
1886 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) {
1887 #ifdef SIP_EVENT_COUNTERS
1888 if (isr & ISR_TXDESC)
1889 SIP_EVCNT_INCR(&sc->sc_ev_txdintr);
1890 else if (isr & ISR_TXIDLE)
1891 SIP_EVCNT_INCR(&sc->sc_ev_txiintr);
1892 #endif
1893
1894 /* Sweep up transmit descriptors. */
1895 sipcom_txintr(sc);
1896
1897 if (isr & ISR_TXURN) {
1898 u_int32_t thresh;
1899 int txfifo_size = (sc->sc_gigabit)
1900 ? DP83820_SIP_TXFIFO_SIZE
1901 : OTHER_SIP_TXFIFO_SIZE;
1902
1903 printf("%s: transmit FIFO underrun",
1904 device_xname(sc->sc_dev));
1905 thresh = sc->sc_tx_drain_thresh + 1;
1906 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask)
1907 && (thresh * 32) <= (txfifo_size -
1908 (sc->sc_tx_fill_thresh * 32))) {
1909 printf("; increasing Tx drain "
1910 "threshold to %u bytes\n",
1911 thresh * 32);
1912 sc->sc_tx_drain_thresh = thresh;
1913 (void) sipcom_init(ifp);
1914 } else {
1915 (void) sipcom_init(ifp);
1916 printf("\n");
1917 }
1918 }
1919 }
1920
1921 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) {
1922 if (isr & ISR_PAUSE_ST) {
1923 sc->sc_paused = 1;
1924 SIP_EVCNT_INCR(&sc->sc_ev_rxpause);
1925 ifp->if_flags |= IFF_OACTIVE;
1926 }
1927 if (isr & ISR_PAUSE_END) {
1928 sc->sc_paused = 0;
1929 ifp->if_flags &= ~IFF_OACTIVE;
1930 }
1931 }
1932
1933 if (isr & ISR_HIBERR) {
1934 int want_init = 0;
1935
1936 SIP_EVCNT_INCR(&sc->sc_ev_hiberr);
1937
1938 #define PRINTERR(bit, str) \
1939 do { \
1940 if ((isr & (bit)) != 0) { \
1941 if ((ifp->if_flags & IFF_DEBUG) != 0) \
1942 printf("%s: %s\n", \
1943 device_xname(sc->sc_dev), str); \
1944 want_init = 1; \
1945 } \
1946 } while (/*CONSTCOND*/0)
1947
1948 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error");
1949 PRINTERR(sc->sc_bits.b_isr_sserr, "system error");
1950 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort");
1951 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort");
1952 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun");
1953 /*
1954 * Ignore:
1955 * Tx reset complete
1956 * Rx reset complete
1957 */
1958 if (want_init)
1959 (void) sipcom_init(ifp);
1960 #undef PRINTERR
1961 }
1962 }
1963
1964 /* Re-enable interrupts. */
1965 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE);
1966
1967 /* Try to get more packets going. */
1968 sipcom_start(ifp);
1969
1970 return (handled);
1971 }
1972
1973 /*
1974 * sip_txintr:
1975 *
1976 * Helper; handle transmit interrupts.
1977 */
1978 static void
1979 sipcom_txintr(struct sip_softc *sc)
1980 {
1981 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1982 struct sip_txsoft *txs;
1983 u_int32_t cmdsts;
1984
1985 if (sc->sc_paused == 0)
1986 ifp->if_flags &= ~IFF_OACTIVE;
1987
1988 /*
1989 * Go through our Tx list and free mbufs for those
1990 * frames which have been transmitted.
1991 */
1992 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1993 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs,
1994 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1995
1996 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc]));
1997 if (cmdsts & CMDSTS_OWN)
1998 break;
1999
2000 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
2001
2002 sc->sc_txfree += txs->txs_dmamap->dm_nsegs;
2003
2004 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
2005 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2006 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2007 m_freem(txs->txs_mbuf);
2008 txs->txs_mbuf = NULL;
2009
2010 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2011
2012 /*
2013 * Check for errors and collisions.
2014 */
2015 if (cmdsts &
2016 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) {
2017 ifp->if_oerrors++;
2018 if (cmdsts & CMDSTS_Tx_EC)
2019 ifp->if_collisions += 16;
2020 if (ifp->if_flags & IFF_DEBUG) {
2021 if (cmdsts & CMDSTS_Tx_ED)
2022 printf("%s: excessive deferral\n",
2023 device_xname(sc->sc_dev));
2024 if (cmdsts & CMDSTS_Tx_EC)
2025 printf("%s: excessive collisions\n",
2026 device_xname(sc->sc_dev));
2027 }
2028 } else {
2029 /* Packet was transmitted successfully. */
2030 ifp->if_opackets++;
2031 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts);
2032 }
2033 }
2034
2035 /*
2036 * If there are no more pending transmissions, cancel the watchdog
2037 * timer.
2038 */
2039 if (txs == NULL) {
2040 ifp->if_timer = 0;
2041 sc->sc_txwin = 0;
2042 }
2043 }
2044
2045 /*
2046 * gsip_rxintr:
2047 *
2048 * Helper; handle receive interrupts on gigabit parts.
2049 */
2050 static void
2051 gsip_rxintr(struct sip_softc *sc)
2052 {
2053 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2054 struct sip_rxsoft *rxs;
2055 struct mbuf *m;
2056 u_int32_t cmdsts, extsts;
2057 int i, len;
2058
2059 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) {
2060 rxs = &sc->sc_rxsoft[i];
2061
2062 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2063
2064 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i]));
2065 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts);
2066 len = CMDSTS_SIZE(sc, cmdsts);
2067
2068 /*
2069 * NOTE: OWN is set if owned by _consumer_. We're the
2070 * consumer of the receive ring, so if the bit is clear,
2071 * we have processed all of the packets.
2072 */
2073 if ((cmdsts & CMDSTS_OWN) == 0) {
2074 /*
2075 * We have processed all of the receive buffers.
2076 */
2077 break;
2078 }
2079
2080 if (__predict_false(sc->sc_rxdiscard)) {
2081 sip_init_rxdesc(sc, i);
2082 if ((cmdsts & CMDSTS_MORE) == 0) {
2083 /* Reset our state. */
2084 sc->sc_rxdiscard = 0;
2085 }
2086 continue;
2087 }
2088
2089 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2090 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2091
2092 m = rxs->rxs_mbuf;
2093
2094 /*
2095 * Add a new receive buffer to the ring.
2096 */
2097 if (sipcom_add_rxbuf(sc, i) != 0) {
2098 /*
2099 * Failed, throw away what we've done so
2100 * far, and discard the rest of the packet.
2101 */
2102 ifp->if_ierrors++;
2103 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2104 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2105 sip_init_rxdesc(sc, i);
2106 if (cmdsts & CMDSTS_MORE)
2107 sc->sc_rxdiscard = 1;
2108 if (sc->sc_rxhead != NULL)
2109 m_freem(sc->sc_rxhead);
2110 sip_rxchain_reset(sc);
2111 continue;
2112 }
2113
2114 sip_rxchain_link(sc, m);
2115
2116 m->m_len = len;
2117
2118 /*
2119 * If this is not the end of the packet, keep
2120 * looking.
2121 */
2122 if (cmdsts & CMDSTS_MORE) {
2123 sc->sc_rxlen += len;
2124 continue;
2125 }
2126
2127 /*
2128 * Okay, we have the entire packet now. The chip includes
2129 * the FCS, so we need to trim it.
2130 */
2131 m->m_len -= ETHER_CRC_LEN;
2132
2133 *sc->sc_rxtailp = NULL;
2134 len = m->m_len + sc->sc_rxlen;
2135 m = sc->sc_rxhead;
2136
2137 sip_rxchain_reset(sc);
2138
2139 /*
2140 * If an error occurred, update stats and drop the packet.
2141 */
2142 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT|
2143 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) {
2144 ifp->if_ierrors++;
2145 if ((cmdsts & CMDSTS_Rx_RXA) != 0 &&
2146 (cmdsts & CMDSTS_Rx_RXO) == 0) {
2147 /* Receive overrun handled elsewhere. */
2148 printf("%s: receive descriptor error\n",
2149 device_xname(sc->sc_dev));
2150 }
2151 #define PRINTERR(bit, str) \
2152 if ((ifp->if_flags & IFF_DEBUG) != 0 && \
2153 (cmdsts & (bit)) != 0) \
2154 printf("%s: %s\n", device_xname(sc->sc_dev), str)
2155 PRINTERR(CMDSTS_Rx_RUNT, "runt packet");
2156 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error");
2157 PRINTERR(CMDSTS_Rx_CRCE, "CRC error");
2158 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error");
2159 #undef PRINTERR
2160 m_freem(m);
2161 continue;
2162 }
2163
2164 /*
2165 * If the packet is small enough to fit in a
2166 * single header mbuf, allocate one and copy
2167 * the data into it. This greatly reduces
2168 * memory consumption when we receive lots
2169 * of small packets.
2170 */
2171 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) {
2172 struct mbuf *nm;
2173 MGETHDR(nm, M_DONTWAIT, MT_DATA);
2174 if (nm == NULL) {
2175 ifp->if_ierrors++;
2176 m_freem(m);
2177 continue;
2178 }
2179 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
2180 nm->m_data += 2;
2181 nm->m_pkthdr.len = nm->m_len = len;
2182 m_copydata(m, 0, len, mtod(nm, void *));
2183 m_freem(m);
2184 m = nm;
2185 }
2186 #ifndef __NO_STRICT_ALIGNMENT
2187 else {
2188 /*
2189 * The DP83820's receive buffers must be 4-byte
2190 * aligned. But this means that the data after
2191 * the Ethernet header is misaligned. To compensate,
2192 * we have artificially shortened the buffer size
2193 * in the descriptor, and we do an overlapping copy
2194 * of the data two bytes further in (in the first
2195 * buffer of the chain only).
2196 */
2197 memmove(mtod(m, char *) + 2, mtod(m, void *),
2198 m->m_len);
2199 m->m_data += 2;
2200 }
2201 #endif /* ! __NO_STRICT_ALIGNMENT */
2202
2203 /*
2204 * If VLANs are enabled, VLAN packets have been unwrapped
2205 * for us. Associate the tag with the packet.
2206 */
2207
2208 /*
2209 * Again, byte swapping is tricky. Hardware provided
2210 * the tag in the network byte order, but extsts was
2211 * passed through le32toh() in the meantime. On a
2212 * big-endian machine, we need to swap it again. On a
2213 * little-endian machine, we need to convert from the
2214 * network to host byte order. This means that we must
2215 * swap it in any case, so unconditional swap instead
2216 * of htons() is used.
2217 */
2218 if ((extsts & EXTSTS_VPKT) != 0) {
2219 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI),
2220 continue);
2221 }
2222
2223 /*
2224 * Set the incoming checksum information for the
2225 * packet.
2226 */
2227 if ((extsts & EXTSTS_IPPKT) != 0) {
2228 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum);
2229 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
2230 if (extsts & EXTSTS_Rx_IPERR)
2231 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
2232 if (extsts & EXTSTS_TCPPKT) {
2233 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum);
2234 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
2235 if (extsts & EXTSTS_Rx_TCPERR)
2236 m->m_pkthdr.csum_flags |=
2237 M_CSUM_TCP_UDP_BAD;
2238 } else if (extsts & EXTSTS_UDPPKT) {
2239 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum);
2240 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
2241 if (extsts & EXTSTS_Rx_UDPERR)
2242 m->m_pkthdr.csum_flags |=
2243 M_CSUM_TCP_UDP_BAD;
2244 }
2245 }
2246
2247 ifp->if_ipackets++;
2248 m->m_pkthdr.rcvif = ifp;
2249 m->m_pkthdr.len = len;
2250
2251 #if NBPFILTER > 0
2252 /*
2253 * Pass this up to any BPF listeners, but only
2254 * pass if up the stack if it's for us.
2255 */
2256 if (ifp->if_bpf)
2257 bpf_mtap(ifp->if_bpf, m);
2258 #endif /* NBPFILTER > 0 */
2259
2260 /* Pass it on. */
2261 (*ifp->if_input)(ifp, m);
2262 }
2263
2264 /* Update the receive pointer. */
2265 sc->sc_rxptr = i;
2266 }
2267
2268 /*
2269 * sip_rxintr:
2270 *
2271 * Helper; handle receive interrupts on 10/100 parts.
2272 */
2273 static void
2274 sip_rxintr(struct sip_softc *sc)
2275 {
2276 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2277 struct sip_rxsoft *rxs;
2278 struct mbuf *m;
2279 u_int32_t cmdsts;
2280 int i, len;
2281
2282 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) {
2283 rxs = &sc->sc_rxsoft[i];
2284
2285 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2286
2287 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i]));
2288
2289 /*
2290 * NOTE: OWN is set if owned by _consumer_. We're the
2291 * consumer of the receive ring, so if the bit is clear,
2292 * we have processed all of the packets.
2293 */
2294 if ((cmdsts & CMDSTS_OWN) == 0) {
2295 /*
2296 * We have processed all of the receive buffers.
2297 */
2298 break;
2299 }
2300
2301 /*
2302 * If any collisions were seen on the wire, count one.
2303 */
2304 if (cmdsts & CMDSTS_Rx_COL)
2305 ifp->if_collisions++;
2306
2307 /*
2308 * If an error occurred, update stats, clear the status
2309 * word, and leave the packet buffer in place. It will
2310 * simply be reused the next time the ring comes around.
2311 */
2312 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT|
2313 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) {
2314 ifp->if_ierrors++;
2315 if ((cmdsts & CMDSTS_Rx_RXA) != 0 &&
2316 (cmdsts & CMDSTS_Rx_RXO) == 0) {
2317 /* Receive overrun handled elsewhere. */
2318 printf("%s: receive descriptor error\n",
2319 device_xname(sc->sc_dev));
2320 }
2321 #define PRINTERR(bit, str) \
2322 if ((ifp->if_flags & IFF_DEBUG) != 0 && \
2323 (cmdsts & (bit)) != 0) \
2324 printf("%s: %s\n", device_xname(sc->sc_dev), str)
2325 PRINTERR(CMDSTS_Rx_RUNT, "runt packet");
2326 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error");
2327 PRINTERR(CMDSTS_Rx_CRCE, "CRC error");
2328 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error");
2329 #undef PRINTERR
2330 sip_init_rxdesc(sc, i);
2331 continue;
2332 }
2333
2334 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2335 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2336
2337 /*
2338 * No errors; receive the packet. Note, the SiS 900
2339 * includes the CRC with every packet.
2340 */
2341 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN;
2342
2343 #ifdef __NO_STRICT_ALIGNMENT
2344 /*
2345 * If the packet is small enough to fit in a
2346 * single header mbuf, allocate one and copy
2347 * the data into it. This greatly reduces
2348 * memory consumption when we receive lots
2349 * of small packets.
2350 *
2351 * Otherwise, we add a new buffer to the receive
2352 * chain. If this fails, we drop the packet and
2353 * recycle the old buffer.
2354 */
2355 if (sip_copy_small != 0 && len <= MHLEN) {
2356 MGETHDR(m, M_DONTWAIT, MT_DATA);
2357 if (m == NULL)
2358 goto dropit;
2359 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
2360 memcpy(mtod(m, void *),
2361 mtod(rxs->rxs_mbuf, void *), len);
2362 sip_init_rxdesc(sc, i);
2363 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2364 rxs->rxs_dmamap->dm_mapsize,
2365 BUS_DMASYNC_PREREAD);
2366 } else {
2367 m = rxs->rxs_mbuf;
2368 if (sipcom_add_rxbuf(sc, i) != 0) {
2369 dropit:
2370 ifp->if_ierrors++;
2371 sip_init_rxdesc(sc, i);
2372 bus_dmamap_sync(sc->sc_dmat,
2373 rxs->rxs_dmamap, 0,
2374 rxs->rxs_dmamap->dm_mapsize,
2375 BUS_DMASYNC_PREREAD);
2376 continue;
2377 }
2378 }
2379 #else
2380 /*
2381 * The SiS 900's receive buffers must be 4-byte aligned.
2382 * But this means that the data after the Ethernet header
2383 * is misaligned. We must allocate a new buffer and
2384 * copy the data, shifted forward 2 bytes.
2385 */
2386 MGETHDR(m, M_DONTWAIT, MT_DATA);
2387 if (m == NULL) {
2388 dropit:
2389 ifp->if_ierrors++;
2390 sip_init_rxdesc(sc, i);
2391 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2392 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2393 continue;
2394 }
2395 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
2396 if (len > (MHLEN - 2)) {
2397 MCLGET(m, M_DONTWAIT);
2398 if ((m->m_flags & M_EXT) == 0) {
2399 m_freem(m);
2400 goto dropit;
2401 }
2402 }
2403 m->m_data += 2;
2404
2405 /*
2406 * Note that we use clusters for incoming frames, so the
2407 * buffer is virtually contiguous.
2408 */
2409 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len);
2410
2411 /* Allow the receive descriptor to continue using its mbuf. */
2412 sip_init_rxdesc(sc, i);
2413 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2414 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2415 #endif /* __NO_STRICT_ALIGNMENT */
2416
2417 ifp->if_ipackets++;
2418 m->m_pkthdr.rcvif = ifp;
2419 m->m_pkthdr.len = m->m_len = len;
2420
2421 #if NBPFILTER > 0
2422 /*
2423 * Pass this up to any BPF listeners, but only
2424 * pass if up the stack if it's for us.
2425 */
2426 if (ifp->if_bpf)
2427 bpf_mtap(ifp->if_bpf, m);
2428 #endif /* NBPFILTER > 0 */
2429
2430 /* Pass it on. */
2431 (*ifp->if_input)(ifp, m);
2432 }
2433
2434 /* Update the receive pointer. */
2435 sc->sc_rxptr = i;
2436 }
2437
2438 /*
2439 * sip_tick:
2440 *
2441 * One second timer, used to tick the MII.
2442 */
2443 static void
2444 sipcom_tick(void *arg)
2445 {
2446 struct sip_softc *sc = arg;
2447 int s;
2448
2449 s = splnet();
2450 #ifdef SIP_EVENT_COUNTERS
2451 if (sc->sc_gigabit) {
2452 /* Read PAUSE related counts from MIB registers. */
2453 sc->sc_ev_rxpause.ev_count +=
2454 bus_space_read_4(sc->sc_st, sc->sc_sh,
2455 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff;
2456 sc->sc_ev_txpause.ev_count +=
2457 bus_space_read_4(sc->sc_st, sc->sc_sh,
2458 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff;
2459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR);
2460 }
2461 #endif /* SIP_EVENT_COUNTERS */
2462 mii_tick(&sc->sc_mii);
2463 splx(s);
2464
2465 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc);
2466 }
2467
2468 /*
2469 * sip_reset:
2470 *
2471 * Perform a soft reset on the SiS 900.
2472 */
2473 static bool
2474 sipcom_reset(struct sip_softc *sc)
2475 {
2476 bus_space_tag_t st = sc->sc_st;
2477 bus_space_handle_t sh = sc->sc_sh;
2478 int i;
2479
2480 bus_space_write_4(st, sh, SIP_IER, 0);
2481 bus_space_write_4(st, sh, SIP_IMR, 0);
2482 bus_space_write_4(st, sh, SIP_RFCR, 0);
2483 bus_space_write_4(st, sh, SIP_CR, CR_RST);
2484
2485 for (i = 0; i < SIP_TIMEOUT; i++) {
2486 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0)
2487 break;
2488 delay(2);
2489 }
2490
2491 if (i == SIP_TIMEOUT) {
2492 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev));
2493 return false;
2494 }
2495
2496 delay(1000);
2497
2498 if (sc->sc_gigabit) {
2499 /*
2500 * Set the general purpose I/O bits. Do it here in case we
2501 * need to have GPIO set up to talk to the media interface.
2502 */
2503 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior);
2504 delay(1000);
2505 }
2506 return true;
2507 }
2508
2509 static void
2510 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable)
2511 {
2512 u_int32_t reg;
2513 bus_space_tag_t st = sc->sc_st;
2514 bus_space_handle_t sh = sc->sc_sh;
2515 /*
2516 * Initialize the VLAN/IP receive control register.
2517 * We enable checksum computation on all incoming
2518 * packets, and do not reject packets w/ bad checksums.
2519 */
2520 reg = 0;
2521 if (capenable &
2522 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx))
2523 reg |= VRCR_IPEN;
2524 if (VLAN_ATTACHED(&sc->sc_ethercom))
2525 reg |= VRCR_VTDEN|VRCR_VTREN;
2526 bus_space_write_4(st, sh, SIP_VRCR, reg);
2527
2528 /*
2529 * Initialize the VLAN/IP transmit control register.
2530 * We enable outgoing checksum computation on a
2531 * per-packet basis.
2532 */
2533 reg = 0;
2534 if (capenable &
2535 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx))
2536 reg |= VTCR_PPCHK;
2537 if (VLAN_ATTACHED(&sc->sc_ethercom))
2538 reg |= VTCR_VPPTI;
2539 bus_space_write_4(st, sh, SIP_VTCR, reg);
2540
2541 /*
2542 * If we're using VLANs, initialize the VLAN data register.
2543 * To understand why we bswap the VLAN Ethertype, see section
2544 * 4.2.36 of the DP83820 manual.
2545 */
2546 if (VLAN_ATTACHED(&sc->sc_ethercom))
2547 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN));
2548 }
2549
2550 /*
2551 * sip_init: [ ifnet interface function ]
2552 *
2553 * Initialize the interface. Must be called at splnet().
2554 */
2555 static int
2556 sipcom_init(struct ifnet *ifp)
2557 {
2558 struct sip_softc *sc = ifp->if_softc;
2559 bus_space_tag_t st = sc->sc_st;
2560 bus_space_handle_t sh = sc->sc_sh;
2561 struct sip_txsoft *txs;
2562 struct sip_rxsoft *rxs;
2563 struct sip_desc *sipd;
2564 int i, error = 0;
2565
2566 if (device_is_active(sc->sc_dev)) {
2567 /*
2568 * Cancel any pending I/O.
2569 */
2570 sipcom_stop(ifp, 0);
2571 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) ||
2572 !device_is_active(sc->sc_dev))
2573 return 0;
2574
2575 /*
2576 * Reset the chip to a known state.
2577 */
2578 if (!sipcom_reset(sc))
2579 return EBUSY;
2580
2581 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) {
2582 /*
2583 * DP83815 manual, page 78:
2584 * 4.4 Recommended Registers Configuration
2585 * For optimum performance of the DP83815, version noted
2586 * as DP83815CVNG (SRR = 203h), the listed register
2587 * modifications must be followed in sequence...
2588 *
2589 * It's not clear if this should be 302h or 203h because that
2590 * chip name is listed as SRR 302h in the description of the
2591 * SRR register. However, my revision 302h DP83815 on the
2592 * Netgear FA311 purchased in 02/2001 needs these settings
2593 * to avoid tons of errors in AcceptPerfectMatch (non-
2594 * IFF_PROMISC) mode. I do not know if other revisions need
2595 * this set or not. [briggs -- 09 March 2001]
2596 *
2597 * Note that only the low-order 12 bits of 0xe4 are documented
2598 * and that this sets reserved bits in that register.
2599 */
2600 bus_space_write_4(st, sh, 0x00cc, 0x0001);
2601
2602 bus_space_write_4(st, sh, 0x00e4, 0x189C);
2603 bus_space_write_4(st, sh, 0x00fc, 0x0000);
2604 bus_space_write_4(st, sh, 0x00f4, 0x5040);
2605 bus_space_write_4(st, sh, 0x00f8, 0x008c);
2606
2607 bus_space_write_4(st, sh, 0x00cc, 0x0000);
2608 }
2609
2610 /*
2611 * Initialize the transmit descriptor ring.
2612 */
2613 for (i = 0; i < sc->sc_ntxdesc; i++) {
2614 sipd = &sc->sc_txdescs[i];
2615 memset(sipd, 0, sizeof(struct sip_desc));
2616 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i)));
2617 }
2618 sip_cdtxsync(sc, 0, sc->sc_ntxdesc,
2619 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2620 sc->sc_txfree = sc->sc_ntxdesc;
2621 sc->sc_txnext = 0;
2622 sc->sc_txwin = 0;
2623
2624 /*
2625 * Initialize the transmit job descriptors.
2626 */
2627 SIMPLEQ_INIT(&sc->sc_txfreeq);
2628 SIMPLEQ_INIT(&sc->sc_txdirtyq);
2629 for (i = 0; i < SIP_TXQUEUELEN; i++) {
2630 txs = &sc->sc_txsoft[i];
2631 txs->txs_mbuf = NULL;
2632 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2633 }
2634
2635 /*
2636 * Initialize the receive descriptor and receive job
2637 * descriptor rings.
2638 */
2639 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
2640 rxs = &sc->sc_rxsoft[i];
2641 if (rxs->rxs_mbuf == NULL) {
2642 if ((error = sipcom_add_rxbuf(sc, i)) != 0) {
2643 printf("%s: unable to allocate or map rx "
2644 "buffer %d, error = %d\n",
2645 device_xname(sc->sc_dev), i, error);
2646 /*
2647 * XXX Should attempt to run with fewer receive
2648 * XXX buffers instead of just failing.
2649 */
2650 sipcom_rxdrain(sc);
2651 goto out;
2652 }
2653 } else
2654 sip_init_rxdesc(sc, i);
2655 }
2656 sc->sc_rxptr = 0;
2657 sc->sc_rxdiscard = 0;
2658 sip_rxchain_reset(sc);
2659
2660 /*
2661 * Set the configuration register; it's already initialized
2662 * in sip_attach().
2663 */
2664 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg);
2665
2666 /*
2667 * Initialize the prototype TXCFG register.
2668 */
2669 if (sc->sc_gigabit) {
2670 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512;
2671 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512;
2672 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) ||
2673 SIP_SIS900_REV(sc, SIS_REV_960) ||
2674 SIP_SIS900_REV(sc, SIS_REV_900B)) &&
2675 (sc->sc_cfg & CFG_EDBMASTEN)) {
2676 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64;
2677 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64;
2678 } else {
2679 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512;
2680 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512;
2681 }
2682
2683 sc->sc_txcfg |= TXCFG_ATP |
2684 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) |
2685 sc->sc_tx_drain_thresh;
2686 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg);
2687
2688 /*
2689 * Initialize the receive drain threshold if we have never
2690 * done so.
2691 */
2692 if (sc->sc_rx_drain_thresh == 0) {
2693 /*
2694 * XXX This value should be tuned. This is set to the
2695 * maximum of 248 bytes, and we may be able to improve
2696 * performance by decreasing it (although we should never
2697 * set this value lower than 2; 14 bytes are required to
2698 * filter the packet).
2699 */
2700 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK);
2701 }
2702
2703 /*
2704 * Initialize the prototype RXCFG register.
2705 */
2706 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK);
2707 /*
2708 * Accept long packets (including FCS) so we can handle
2709 * 802.1q-tagged frames and jumbo frames properly.
2710 */
2711 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) ||
2712 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU))
2713 sc->sc_rxcfg |= RXCFG_ALP;
2714
2715 /*
2716 * Checksum offloading is disabled if the user selects an MTU
2717 * larger than 8109. (FreeBSD says 8152, but there is emperical
2718 * evidence that >8109 does not work on some boards, such as the
2719 * Planex GN-1000TE).
2720 */
2721 if (sc->sc_gigabit && ifp->if_mtu > 8109 &&
2722 (ifp->if_capenable &
2723 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx|
2724 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx|
2725 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) {
2726 printf("%s: Checksum offloading does not work if MTU > 8109 - "
2727 "disabled.\n", device_xname(sc->sc_dev));
2728 ifp->if_capenable &=
2729 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx|
2730 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx|
2731 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx);
2732 ifp->if_csum_flags_tx = 0;
2733 ifp->if_csum_flags_rx = 0;
2734 }
2735
2736 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg);
2737
2738 if (sc->sc_gigabit)
2739 sipcom_dp83820_init(sc, ifp->if_capenable);
2740
2741 /*
2742 * Give the transmit and receive rings to the chip.
2743 */
2744 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext));
2745 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr));
2746
2747 /*
2748 * Initialize the interrupt mask.
2749 */
2750 sc->sc_imr = sc->sc_bits.b_isr_dperr |
2751 sc->sc_bits.b_isr_sserr |
2752 sc->sc_bits.b_isr_rmabt |
2753 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR |
2754 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC;
2755 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr);
2756
2757 /* Set up the receive filter. */
2758 (*sc->sc_model->sip_variant->sipv_set_filter)(sc);
2759
2760 /*
2761 * Tune sc_rx_flow_thresh.
2762 * XXX "More than 8KB" is too short for jumbo frames.
2763 * XXX TODO: Threshold value should be user-settable.
2764 */
2765 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 |
2766 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 |
2767 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK));
2768
2769 /*
2770 * Set the current media. Do this after initializing the prototype
2771 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow
2772 * control.
2773 */
2774 if ((error = ether_mediachange(ifp)) != 0)
2775 goto out;
2776
2777 /*
2778 * Set the interrupt hold-off timer to 100us.
2779 */
2780 if (sc->sc_gigabit)
2781 bus_space_write_4(st, sh, SIP_IHR, 0x01);
2782
2783 /*
2784 * Enable interrupts.
2785 */
2786 bus_space_write_4(st, sh, SIP_IER, IER_IE);
2787
2788 /*
2789 * Start the transmit and receive processes.
2790 */
2791 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE);
2792
2793 /*
2794 * Start the one second MII clock.
2795 */
2796 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc);
2797
2798 /*
2799 * ...all done!
2800 */
2801 ifp->if_flags |= IFF_RUNNING;
2802 ifp->if_flags &= ~IFF_OACTIVE;
2803 sc->sc_if_flags = ifp->if_flags;
2804 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable;
2805 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom);
2806 sc->sc_prev.if_capenable = ifp->if_capenable;
2807
2808 out:
2809 if (error)
2810 printf("%s: interface not running\n", device_xname(sc->sc_dev));
2811 return (error);
2812 }
2813
2814 /*
2815 * sip_drain:
2816 *
2817 * Drain the receive queue.
2818 */
2819 static void
2820 sipcom_rxdrain(struct sip_softc *sc)
2821 {
2822 struct sip_rxsoft *rxs;
2823 int i;
2824
2825 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
2826 rxs = &sc->sc_rxsoft[i];
2827 if (rxs->rxs_mbuf != NULL) {
2828 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2829 m_freem(rxs->rxs_mbuf);
2830 rxs->rxs_mbuf = NULL;
2831 }
2832 }
2833 }
2834
2835 /*
2836 * sip_stop: [ ifnet interface function ]
2837 *
2838 * Stop transmission on the interface.
2839 */
2840 static void
2841 sipcom_stop(struct ifnet *ifp, int disable)
2842 {
2843 struct sip_softc *sc = ifp->if_softc;
2844 bus_space_tag_t st = sc->sc_st;
2845 bus_space_handle_t sh = sc->sc_sh;
2846 struct sip_txsoft *txs;
2847 u_int32_t cmdsts = 0; /* DEBUG */
2848
2849 /*
2850 * Stop the one second clock.
2851 */
2852 callout_stop(&sc->sc_tick_ch);
2853
2854 /* Down the MII. */
2855 mii_down(&sc->sc_mii);
2856
2857 if (device_is_active(sc->sc_dev)) {
2858 /*
2859 * Disable interrupts.
2860 */
2861 bus_space_write_4(st, sh, SIP_IER, 0);
2862
2863 /*
2864 * Stop receiver and transmitter.
2865 */
2866 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD);
2867 }
2868
2869 /*
2870 * Release any queued transmit buffers.
2871 */
2872 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
2873 if ((ifp->if_flags & IFF_DEBUG) != 0 &&
2874 SIMPLEQ_NEXT(txs, txs_q) == NULL &&
2875 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) &
2876 CMDSTS_INTR) == 0)
2877 printf("%s: sip_stop: last descriptor does not "
2878 "have INTR bit set\n", device_xname(sc->sc_dev));
2879 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
2880 #ifdef DIAGNOSTIC
2881 if (txs->txs_mbuf == NULL) {
2882 printf("%s: dirty txsoft with no mbuf chain\n",
2883 device_xname(sc->sc_dev));
2884 panic("sip_stop");
2885 }
2886 #endif
2887 cmdsts |= /* DEBUG */
2888 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc]));
2889 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2890 m_freem(txs->txs_mbuf);
2891 txs->txs_mbuf = NULL;
2892 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2893 }
2894
2895 /*
2896 * Mark the interface down and cancel the watchdog timer.
2897 */
2898 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2899 ifp->if_timer = 0;
2900
2901 if (disable)
2902 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual);
2903
2904 if ((ifp->if_flags & IFF_DEBUG) != 0 &&
2905 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc)
2906 printf("%s: sip_stop: no INTR bits set in dirty tx "
2907 "descriptors\n", device_xname(sc->sc_dev));
2908 }
2909
2910 /*
2911 * sip_read_eeprom:
2912 *
2913 * Read data from the serial EEPROM.
2914 */
2915 static void
2916 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt,
2917 u_int16_t *data)
2918 {
2919 bus_space_tag_t st = sc->sc_st;
2920 bus_space_handle_t sh = sc->sc_sh;
2921 u_int16_t reg;
2922 int i, x;
2923
2924 for (i = 0; i < wordcnt; i++) {
2925 /* Send CHIP SELECT. */
2926 reg = EROMAR_EECS;
2927 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2928
2929 /* Shift in the READ opcode. */
2930 for (x = 3; x > 0; x--) {
2931 if (SIP_EEPROM_OPC_READ & (1 << (x - 1)))
2932 reg |= EROMAR_EEDI;
2933 else
2934 reg &= ~EROMAR_EEDI;
2935 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2936 bus_space_write_4(st, sh, SIP_EROMAR,
2937 reg | EROMAR_EESK);
2938 delay(4);
2939 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2940 delay(4);
2941 }
2942
2943 /* Shift in address. */
2944 for (x = 6; x > 0; x--) {
2945 if ((word + i) & (1 << (x - 1)))
2946 reg |= EROMAR_EEDI;
2947 else
2948 reg &= ~EROMAR_EEDI;
2949 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2950 bus_space_write_4(st, sh, SIP_EROMAR,
2951 reg | EROMAR_EESK);
2952 delay(4);
2953 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2954 delay(4);
2955 }
2956
2957 /* Shift out data. */
2958 reg = EROMAR_EECS;
2959 data[i] = 0;
2960 for (x = 16; x > 0; x--) {
2961 bus_space_write_4(st, sh, SIP_EROMAR,
2962 reg | EROMAR_EESK);
2963 delay(4);
2964 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO)
2965 data[i] |= (1 << (x - 1));
2966 bus_space_write_4(st, sh, SIP_EROMAR, reg);
2967 delay(4);
2968 }
2969
2970 /* Clear CHIP SELECT. */
2971 bus_space_write_4(st, sh, SIP_EROMAR, 0);
2972 delay(4);
2973 }
2974 }
2975
2976 /*
2977 * sipcom_add_rxbuf:
2978 *
2979 * Add a receive buffer to the indicated descriptor.
2980 */
2981 static int
2982 sipcom_add_rxbuf(struct sip_softc *sc, int idx)
2983 {
2984 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx];
2985 struct mbuf *m;
2986 int error;
2987
2988 MGETHDR(m, M_DONTWAIT, MT_DATA);
2989 if (m == NULL)
2990 return (ENOBUFS);
2991 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
2992
2993 MCLGET(m, M_DONTWAIT);
2994 if ((m->m_flags & M_EXT) == 0) {
2995 m_freem(m);
2996 return (ENOBUFS);
2997 }
2998
2999 /* XXX I don't believe this is necessary. --dyoung */
3000 if (sc->sc_gigabit)
3001 m->m_len = sc->sc_parm->p_rxbuf_len;
3002
3003 if (rxs->rxs_mbuf != NULL)
3004 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
3005
3006 rxs->rxs_mbuf = m;
3007
3008 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
3009 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
3010 BUS_DMA_READ|BUS_DMA_NOWAIT);
3011 if (error) {
3012 printf("%s: can't load rx DMA map %d, error = %d\n",
3013 device_xname(sc->sc_dev), idx, error);
3014 panic("%s", __func__); /* XXX */
3015 }
3016
3017 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3018 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3019
3020 sip_init_rxdesc(sc, idx);
3021
3022 return (0);
3023 }
3024
3025 /*
3026 * sip_sis900_set_filter:
3027 *
3028 * Set up the receive filter.
3029 */
3030 static void
3031 sipcom_sis900_set_filter(struct sip_softc *sc)
3032 {
3033 bus_space_tag_t st = sc->sc_st;
3034 bus_space_handle_t sh = sc->sc_sh;
3035 struct ethercom *ec = &sc->sc_ethercom;
3036 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3037 struct ether_multi *enm;
3038 const u_int8_t *cp;
3039 struct ether_multistep step;
3040 u_int32_t crc, mchash[16];
3041
3042 /*
3043 * Initialize the prototype RFCR.
3044 */
3045 sc->sc_rfcr = RFCR_RFEN;
3046 if (ifp->if_flags & IFF_BROADCAST)
3047 sc->sc_rfcr |= RFCR_AAB;
3048 if (ifp->if_flags & IFF_PROMISC) {
3049 sc->sc_rfcr |= RFCR_AAP;
3050 goto allmulti;
3051 }
3052
3053 /*
3054 * Set up the multicast address filter by passing all multicast
3055 * addresses through a CRC generator, and then using the high-order
3056 * 6 bits as an index into the 128 bit multicast hash table (only
3057 * the lower 16 bits of each 32 bit multicast hash register are
3058 * valid). The high order bits select the register, while the
3059 * rest of the bits select the bit within the register.
3060 */
3061
3062 memset(mchash, 0, sizeof(mchash));
3063
3064 /*
3065 * SiS900 (at least SiS963) requires us to register the address of
3066 * the PAUSE packet (01:80:c2:00:00:01) into the address filter.
3067 */
3068 crc = 0x0ed423f9;
3069
3070 if (SIP_SIS900_REV(sc, SIS_REV_635) ||
3071 SIP_SIS900_REV(sc, SIS_REV_960) ||
3072 SIP_SIS900_REV(sc, SIS_REV_900B)) {
3073 /* Just want the 8 most significant bits. */
3074 crc >>= 24;
3075 } else {
3076 /* Just want the 7 most significant bits. */
3077 crc >>= 25;
3078 }
3079
3080 /* Set the corresponding bit in the hash table. */
3081 mchash[crc >> 4] |= 1 << (crc & 0xf);
3082
3083 ETHER_FIRST_MULTI(step, ec, enm);
3084 while (enm != NULL) {
3085 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
3086 /*
3087 * We must listen to a range of multicast addresses.
3088 * For now, just accept all multicasts, rather than
3089 * trying to set only those filter bits needed to match
3090 * the range. (At this time, the only use of address
3091 * ranges is for IP multicast routing, for which the
3092 * range is big enough to require all bits set.)
3093 */
3094 goto allmulti;
3095 }
3096
3097 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
3098
3099 if (SIP_SIS900_REV(sc, SIS_REV_635) ||
3100 SIP_SIS900_REV(sc, SIS_REV_960) ||
3101 SIP_SIS900_REV(sc, SIS_REV_900B)) {
3102 /* Just want the 8 most significant bits. */
3103 crc >>= 24;
3104 } else {
3105 /* Just want the 7 most significant bits. */
3106 crc >>= 25;
3107 }
3108
3109 /* Set the corresponding bit in the hash table. */
3110 mchash[crc >> 4] |= 1 << (crc & 0xf);
3111
3112 ETHER_NEXT_MULTI(step, enm);
3113 }
3114
3115 ifp->if_flags &= ~IFF_ALLMULTI;
3116 goto setit;
3117
3118 allmulti:
3119 ifp->if_flags |= IFF_ALLMULTI;
3120 sc->sc_rfcr |= RFCR_AAM;
3121
3122 setit:
3123 #define FILTER_EMIT(addr, data) \
3124 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \
3125 delay(1); \
3126 bus_space_write_4(st, sh, SIP_RFDR, (data)); \
3127 delay(1)
3128
3129 /*
3130 * Disable receive filter, and program the node address.
3131 */
3132 cp = CLLADDR(ifp->if_sadl);
3133 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]);
3134 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]);
3135 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]);
3136
3137 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3138 /*
3139 * Program the multicast hash table.
3140 */
3141 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]);
3142 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]);
3143 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]);
3144 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]);
3145 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]);
3146 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]);
3147 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]);
3148 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]);
3149 if (SIP_SIS900_REV(sc, SIS_REV_635) ||
3150 SIP_SIS900_REV(sc, SIS_REV_960) ||
3151 SIP_SIS900_REV(sc, SIS_REV_900B)) {
3152 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]);
3153 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]);
3154 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]);
3155 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]);
3156 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]);
3157 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]);
3158 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]);
3159 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]);
3160 }
3161 }
3162 #undef FILTER_EMIT
3163
3164 /*
3165 * Re-enable the receiver filter.
3166 */
3167 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
3168 }
3169
3170 /*
3171 * sip_dp83815_set_filter:
3172 *
3173 * Set up the receive filter.
3174 */
3175 static void
3176 sipcom_dp83815_set_filter(struct sip_softc *sc)
3177 {
3178 bus_space_tag_t st = sc->sc_st;
3179 bus_space_handle_t sh = sc->sc_sh;
3180 struct ethercom *ec = &sc->sc_ethercom;
3181 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
3182 struct ether_multi *enm;
3183 const u_int8_t *cp;
3184 struct ether_multistep step;
3185 u_int32_t crc, hash, slot, bit;
3186 #define MCHASH_NWORDS_83820 128
3187 #define MCHASH_NWORDS_83815 32
3188 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815)
3189 u_int16_t mchash[MCHASH_NWORDS];
3190 int i;
3191
3192 /*
3193 * Initialize the prototype RFCR.
3194 * Enable the receive filter, and accept on
3195 * Perfect (destination address) Match
3196 * If IFF_BROADCAST, also accept all broadcast packets.
3197 * If IFF_PROMISC, accept all unicast packets (and later, set
3198 * IFF_ALLMULTI and accept all multicast, too).
3199 */
3200 sc->sc_rfcr = RFCR_RFEN | RFCR_APM;
3201 if (ifp->if_flags & IFF_BROADCAST)
3202 sc->sc_rfcr |= RFCR_AAB;
3203 if (ifp->if_flags & IFF_PROMISC) {
3204 sc->sc_rfcr |= RFCR_AAP;
3205 goto allmulti;
3206 }
3207
3208 /*
3209 * Set up the DP83820/DP83815 multicast address filter by
3210 * passing all multicast addresses through a CRC generator,
3211 * and then using the high-order 11/9 bits as an index into
3212 * the 2048/512 bit multicast hash table. The high-order
3213 * 7/5 bits select the slot, while the low-order 4 bits
3214 * select the bit within the slot. Note that only the low
3215 * 16-bits of each filter word are used, and there are
3216 * 128/32 filter words.
3217 */
3218
3219 memset(mchash, 0, sizeof(mchash));
3220
3221 ifp->if_flags &= ~IFF_ALLMULTI;
3222 ETHER_FIRST_MULTI(step, ec, enm);
3223 if (enm == NULL)
3224 goto setit;
3225 while (enm != NULL) {
3226 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
3227 /*
3228 * We must listen to a range of multicast addresses.
3229 * For now, just accept all multicasts, rather than
3230 * trying to set only those filter bits needed to match
3231 * the range. (At this time, the only use of address
3232 * ranges is for IP multicast routing, for which the
3233 * range is big enough to require all bits set.)
3234 */
3235 goto allmulti;
3236 }
3237
3238 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
3239
3240 if (sc->sc_gigabit) {
3241 /* Just want the 11 most significant bits. */
3242 hash = crc >> 21;
3243 } else {
3244 /* Just want the 9 most significant bits. */
3245 hash = crc >> 23;
3246 }
3247
3248 slot = hash >> 4;
3249 bit = hash & 0xf;
3250
3251 /* Set the corresponding bit in the hash table. */
3252 mchash[slot] |= 1 << bit;
3253
3254 ETHER_NEXT_MULTI(step, enm);
3255 }
3256 sc->sc_rfcr |= RFCR_MHEN;
3257 goto setit;
3258
3259 allmulti:
3260 ifp->if_flags |= IFF_ALLMULTI;
3261 sc->sc_rfcr |= RFCR_AAM;
3262
3263 setit:
3264 #define FILTER_EMIT(addr, data) \
3265 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \
3266 delay(1); \
3267 bus_space_write_4(st, sh, SIP_RFDR, (data)); \
3268 delay(1)
3269
3270 /*
3271 * Disable receive filter, and program the node address.
3272 */
3273 cp = CLLADDR(ifp->if_sadl);
3274 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]);
3275 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]);
3276 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]);
3277
3278 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3279 int nwords =
3280 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815;
3281 /*
3282 * Program the multicast hash table.
3283 */
3284 for (i = 0; i < nwords; i++) {
3285 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]);
3286 }
3287 }
3288 #undef FILTER_EMIT
3289 #undef MCHASH_NWORDS
3290 #undef MCHASH_NWORDS_83815
3291 #undef MCHASH_NWORDS_83820
3292
3293 /*
3294 * Re-enable the receiver filter.
3295 */
3296 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr);
3297 }
3298
3299 /*
3300 * sip_dp83820_mii_readreg: [mii interface function]
3301 *
3302 * Read a PHY register on the MII of the DP83820.
3303 */
3304 static int
3305 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg)
3306 {
3307 struct sip_softc *sc = device_private(self);
3308
3309 if (sc->sc_cfg & CFG_TBI_EN) {
3310 bus_addr_t tbireg;
3311 int rv;
3312
3313 if (phy != 0)
3314 return (0);
3315
3316 switch (reg) {
3317 case MII_BMCR: tbireg = SIP_TBICR; break;
3318 case MII_BMSR: tbireg = SIP_TBISR; break;
3319 case MII_ANAR: tbireg = SIP_TANAR; break;
3320 case MII_ANLPAR: tbireg = SIP_TANLPAR; break;
3321 case MII_ANER: tbireg = SIP_TANER; break;
3322 case MII_EXTSR:
3323 /*
3324 * Don't even bother reading the TESR register.
3325 * The manual documents that the device has
3326 * 1000baseX full/half capability, but the
3327 * register itself seems read back 0 on some
3328 * boards. Just hard-code the result.
3329 */
3330 return (EXTSR_1000XFDX|EXTSR_1000XHDX);
3331
3332 default:
3333 return (0);
3334 }
3335
3336 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff;
3337 if (tbireg == SIP_TBISR) {
3338 /* LINK and ACOMP are switched! */
3339 int val = rv;
3340
3341 rv = 0;
3342 if (val & TBISR_MR_LINK_STATUS)
3343 rv |= BMSR_LINK;
3344 if (val & TBISR_MR_AN_COMPLETE)
3345 rv |= BMSR_ACOMP;
3346
3347 /*
3348 * The manual claims this register reads back 0
3349 * on hard and soft reset. But we want to let
3350 * the gentbi driver know that we support auto-
3351 * negotiation, so hard-code this bit in the
3352 * result.
3353 */
3354 rv |= BMSR_ANEG | BMSR_EXTSTAT;
3355 }
3356
3357 return (rv);
3358 }
3359
3360 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg);
3361 }
3362
3363 /*
3364 * sip_dp83820_mii_writereg: [mii interface function]
3365 *
3366 * Write a PHY register on the MII of the DP83820.
3367 */
3368 static void
3369 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val)
3370 {
3371 struct sip_softc *sc = device_private(self);
3372
3373 if (sc->sc_cfg & CFG_TBI_EN) {
3374 bus_addr_t tbireg;
3375
3376 if (phy != 0)
3377 return;
3378
3379 switch (reg) {
3380 case MII_BMCR: tbireg = SIP_TBICR; break;
3381 case MII_ANAR: tbireg = SIP_TANAR; break;
3382 case MII_ANLPAR: tbireg = SIP_TANLPAR; break;
3383 default:
3384 return;
3385 }
3386
3387 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val);
3388 return;
3389 }
3390
3391 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val);
3392 }
3393
3394 /*
3395 * sip_dp83820_mii_statchg: [mii interface function]
3396 *
3397 * Callback from MII layer when media changes.
3398 */
3399 static void
3400 sipcom_dp83820_mii_statchg(device_t self)
3401 {
3402 struct sip_softc *sc = device_private(self);
3403 struct mii_data *mii = &sc->sc_mii;
3404 u_int32_t cfg, pcr;
3405
3406 /*
3407 * Get flow control negotiation result.
3408 */
3409 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
3410 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
3411 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
3412 mii->mii_media_active &= ~IFM_ETH_FMASK;
3413 }
3414
3415 /*
3416 * Update TXCFG for full-duplex operation.
3417 */
3418 if ((mii->mii_media_active & IFM_FDX) != 0)
3419 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3420 else
3421 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3422
3423 /*
3424 * Update RXCFG for full-duplex or loopback.
3425 */
3426 if ((mii->mii_media_active & IFM_FDX) != 0 ||
3427 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP)
3428 sc->sc_rxcfg |= RXCFG_ATX;
3429 else
3430 sc->sc_rxcfg &= ~RXCFG_ATX;
3431
3432 /*
3433 * Update CFG for MII/GMII.
3434 */
3435 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
3436 cfg = sc->sc_cfg | CFG_MODE_1000;
3437 else
3438 cfg = sc->sc_cfg;
3439
3440 /*
3441 * 802.3x flow control.
3442 */
3443 pcr = 0;
3444 if (sc->sc_flowflags & IFM_FLOW) {
3445 if (sc->sc_flowflags & IFM_ETH_TXPAUSE)
3446 pcr |= sc->sc_rx_flow_thresh;
3447 if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
3448 pcr |= PCR_PSEN | PCR_PS_MCAST;
3449 }
3450
3451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg);
3452 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg,
3453 sc->sc_txcfg);
3454 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg,
3455 sc->sc_rxcfg);
3456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr);
3457 }
3458
3459 /*
3460 * sip_mii_bitbang_read: [mii bit-bang interface function]
3461 *
3462 * Read the MII serial port for the MII bit-bang module.
3463 */
3464 static u_int32_t
3465 sipcom_mii_bitbang_read(device_t self)
3466 {
3467 struct sip_softc *sc = device_private(self);
3468
3469 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR));
3470 }
3471
3472 /*
3473 * sip_mii_bitbang_write: [mii big-bang interface function]
3474 *
3475 * Write the MII serial port for the MII bit-bang module.
3476 */
3477 static void
3478 sipcom_mii_bitbang_write(device_t self, u_int32_t val)
3479 {
3480 struct sip_softc *sc = device_private(self);
3481
3482 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val);
3483 }
3484
3485 /*
3486 * sip_sis900_mii_readreg: [mii interface function]
3487 *
3488 * Read a PHY register on the MII.
3489 */
3490 static int
3491 sipcom_sis900_mii_readreg(device_t self, int phy, int reg)
3492 {
3493 struct sip_softc *sc = device_private(self);
3494 u_int32_t enphy;
3495
3496 /*
3497 * The PHY of recent SiS chipsets is accessed through bitbang
3498 * operations.
3499 */
3500 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900)
3501 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops,
3502 phy, reg);
3503
3504 #ifndef SIS900_MII_RESTRICT
3505 /*
3506 * The SiS 900 has only an internal PHY on the MII. Only allow
3507 * MII address 0.
3508 */
3509 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
3510 return (0);
3511 #endif
3512
3513 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
3514 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) |
3515 ENPHY_RWCMD | ENPHY_ACCESS);
3516 do {
3517 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
3518 } while (enphy & ENPHY_ACCESS);
3519 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT);
3520 }
3521
3522 /*
3523 * sip_sis900_mii_writereg: [mii interface function]
3524 *
3525 * Write a PHY register on the MII.
3526 */
3527 static void
3528 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val)
3529 {
3530 struct sip_softc *sc = device_private(self);
3531 u_int32_t enphy;
3532
3533 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) {
3534 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops,
3535 phy, reg, val);
3536 return;
3537 }
3538
3539 #ifndef SIS900_MII_RESTRICT
3540 /*
3541 * The SiS 900 has only an internal PHY on the MII. Only allow
3542 * MII address 0.
3543 */
3544 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0)
3545 return;
3546 #endif
3547
3548 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY,
3549 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) |
3550 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS);
3551 do {
3552 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY);
3553 } while (enphy & ENPHY_ACCESS);
3554 }
3555
3556 /*
3557 * sip_sis900_mii_statchg: [mii interface function]
3558 *
3559 * Callback from MII layer when media changes.
3560 */
3561 static void
3562 sipcom_sis900_mii_statchg(device_t self)
3563 {
3564 struct sip_softc *sc = device_private(self);
3565 struct mii_data *mii = &sc->sc_mii;
3566 u_int32_t flowctl;
3567
3568 /*
3569 * Get flow control negotiation result.
3570 */
3571 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
3572 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
3573 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
3574 mii->mii_media_active &= ~IFM_ETH_FMASK;
3575 }
3576
3577 /*
3578 * Update TXCFG for full-duplex operation.
3579 */
3580 if ((mii->mii_media_active & IFM_FDX) != 0)
3581 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3582 else
3583 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3584
3585 /*
3586 * Update RXCFG for full-duplex or loopback.
3587 */
3588 if ((mii->mii_media_active & IFM_FDX) != 0 ||
3589 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP)
3590 sc->sc_rxcfg |= RXCFG_ATX;
3591 else
3592 sc->sc_rxcfg &= ~RXCFG_ATX;
3593
3594 /*
3595 * Update IMR for use of 802.3x flow control.
3596 */
3597 if (sc->sc_flowflags & IFM_FLOW) {
3598 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST);
3599 flowctl = FLOWCTL_FLOWEN;
3600 } else {
3601 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST);
3602 flowctl = 0;
3603 }
3604
3605 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg,
3606 sc->sc_txcfg);
3607 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg,
3608 sc->sc_rxcfg);
3609 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr);
3610 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl);
3611 }
3612
3613 /*
3614 * sip_dp83815_mii_readreg: [mii interface function]
3615 *
3616 * Read a PHY register on the MII.
3617 */
3618 static int
3619 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg)
3620 {
3621 struct sip_softc *sc = device_private(self);
3622 u_int32_t val;
3623
3624 /*
3625 * The DP83815 only has an internal PHY. Only allow
3626 * MII address 0.
3627 */
3628 if (phy != 0)
3629 return (0);
3630
3631 /*
3632 * Apparently, after a reset, the DP83815 can take a while
3633 * to respond. During this recovery period, the BMSR returns
3634 * a value of 0. Catch this -- it's not supposed to happen
3635 * (the BMSR has some hardcoded-to-1 bits), and wait for the
3636 * PHY to come back to life.
3637 *
3638 * This works out because the BMSR is the first register
3639 * read during the PHY probe process.
3640 */
3641 do {
3642 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg));
3643 } while (reg == MII_BMSR && val == 0);
3644
3645 return (val & 0xffff);
3646 }
3647
3648 /*
3649 * sip_dp83815_mii_writereg: [mii interface function]
3650 *
3651 * Write a PHY register to the MII.
3652 */
3653 static void
3654 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val)
3655 {
3656 struct sip_softc *sc = device_private(self);
3657
3658 /*
3659 * The DP83815 only has an internal PHY. Only allow
3660 * MII address 0.
3661 */
3662 if (phy != 0)
3663 return;
3664
3665 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val);
3666 }
3667
3668 /*
3669 * sip_dp83815_mii_statchg: [mii interface function]
3670 *
3671 * Callback from MII layer when media changes.
3672 */
3673 static void
3674 sipcom_dp83815_mii_statchg(device_t self)
3675 {
3676 struct sip_softc *sc = device_private(self);
3677
3678 /*
3679 * Update TXCFG for full-duplex operation.
3680 */
3681 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
3682 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI);
3683 else
3684 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI);
3685
3686 /*
3687 * Update RXCFG for full-duplex or loopback.
3688 */
3689 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 ||
3690 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP)
3691 sc->sc_rxcfg |= RXCFG_ATX;
3692 else
3693 sc->sc_rxcfg &= ~RXCFG_ATX;
3694
3695 /*
3696 * XXX 802.3x flow control.
3697 */
3698
3699 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg,
3700 sc->sc_txcfg);
3701 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg,
3702 sc->sc_rxcfg);
3703
3704 /*
3705 * Some DP83815s experience problems when used with short
3706 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This
3707 * sequence adjusts the DSP's signal attenuation to fix the
3708 * problem.
3709 */
3710 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) {
3711 uint32_t reg;
3712
3713 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001);
3714
3715 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);
3716 reg &= 0x0fff;
3717 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000);
3718 delay(100);
3719 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc);
3720 reg &= 0x00ff;
3721 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) {
3722 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc,
3723 0x00e8);
3724 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);
3725 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4,
3726 reg | 0x20);
3727 }
3728
3729 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0);
3730 }
3731 }
3732
3733 static void
3734 sipcom_dp83820_read_macaddr(struct sip_softc *sc,
3735 const struct pci_attach_args *pa, u_int8_t *enaddr)
3736 {
3737 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2];
3738 u_int8_t cksum, *e, match;
3739 int i;
3740
3741 /*
3742 * EEPROM data format for the DP83820 can be found in
3743 * the DP83820 manual, section 4.2.4.
3744 */
3745
3746 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data);
3747
3748 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8;
3749 match = ~(match - 1);
3750
3751 cksum = 0x55;
3752 e = (u_int8_t *) eeprom_data;
3753 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++)
3754 cksum += *e++;
3755
3756 if (cksum != match)
3757 printf("%s: Checksum (%x) mismatch (%x)",
3758 device_xname(sc->sc_dev), cksum, match);
3759
3760 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff;
3761 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8;
3762 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff;
3763 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8;
3764 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff;
3765 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8;
3766 }
3767
3768 static void
3769 sipcom_sis900_eeprom_delay(struct sip_softc *sc)
3770 {
3771 int i;
3772
3773 /*
3774 * FreeBSD goes from (300/33)+1 [10] to 0. There must be
3775 * a reason, but I don't know it.
3776 */
3777 for (i = 0; i < 10; i++)
3778 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR);
3779 }
3780
3781 static void
3782 sipcom_sis900_read_macaddr(struct sip_softc *sc,
3783 const struct pci_attach_args *pa, u_int8_t *enaddr)
3784 {
3785 u_int16_t myea[ETHER_ADDR_LEN / 2];
3786
3787 switch (sc->sc_rev) {
3788 case SIS_REV_630S:
3789 case SIS_REV_630E:
3790 case SIS_REV_630EA1:
3791 case SIS_REV_630ET:
3792 case SIS_REV_635:
3793 /*
3794 * The MAC address for the on-board Ethernet of
3795 * the SiS 630 chipset is in the NVRAM. Kick
3796 * the chip into re-loading it from NVRAM, and
3797 * read the MAC address out of the filter registers.
3798 */
3799 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD);
3800
3801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3802 RFCR_RFADDR_NODE0);
3803 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3804 0xffff;
3805
3806 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3807 RFCR_RFADDR_NODE2);
3808 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3809 0xffff;
3810
3811 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR,
3812 RFCR_RFADDR_NODE4);
3813 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) &
3814 0xffff;
3815 break;
3816
3817 case SIS_REV_960:
3818 {
3819 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \
3820 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y))
3821
3822 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \
3823 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y))
3824
3825 int waittime, i;
3826
3827 /* Allow to read EEPROM from LAN. It is shared
3828 * between a 1394 controller and the NIC and each
3829 * time we access it, we need to set SIS_EECMD_REQ.
3830 */
3831 SIS_SET_EROMAR(sc, EROMAR_REQ);
3832
3833 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */
3834 /* Force EEPROM to idle state. */
3835
3836 /*
3837 * XXX-cube This is ugly. I'll look for docs about it.
3838 */
3839 SIS_SET_EROMAR(sc, EROMAR_EECS);
3840 sipcom_sis900_eeprom_delay(sc);
3841 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */
3842 SIS_SET_EROMAR(sc, EROMAR_EESK);
3843 sipcom_sis900_eeprom_delay(sc);
3844 SIS_CLR_EROMAR(sc, EROMAR_EESK);
3845 sipcom_sis900_eeprom_delay(sc);
3846 }
3847 SIS_CLR_EROMAR(sc, EROMAR_EECS);
3848 sipcom_sis900_eeprom_delay(sc);
3849 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0);
3850
3851 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) {
3852 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1,
3853 sizeof(myea) / sizeof(myea[0]), myea);
3854 break;
3855 }
3856 DELAY(1);
3857 }
3858
3859 /*
3860 * Set SIS_EECTL_CLK to high, so a other master
3861 * can operate on the i2c bus.
3862 */
3863 SIS_SET_EROMAR(sc, EROMAR_EESK);
3864
3865 /* Refuse EEPROM access by LAN */
3866 SIS_SET_EROMAR(sc, EROMAR_DONE);
3867 } break;
3868
3869 default:
3870 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1,
3871 sizeof(myea) / sizeof(myea[0]), myea);
3872 }
3873
3874 enaddr[0] = myea[0] & 0xff;
3875 enaddr[1] = myea[0] >> 8;
3876 enaddr[2] = myea[1] & 0xff;
3877 enaddr[3] = myea[1] >> 8;
3878 enaddr[4] = myea[2] & 0xff;
3879 enaddr[5] = myea[2] >> 8;
3880 }
3881
3882 /* Table and macro to bit-reverse an octet. */
3883 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15};
3884 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf])
3885
3886 static void
3887 sipcom_dp83815_read_macaddr(struct sip_softc *sc,
3888 const struct pci_attach_args *pa, u_int8_t *enaddr)
3889 {
3890 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea;
3891 u_int8_t cksum, *e, match;
3892 int i;
3893
3894 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) /
3895 sizeof(eeprom_data[0]), eeprom_data);
3896
3897 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8;
3898 match = ~(match - 1);
3899
3900 cksum = 0x55;
3901 e = (u_int8_t *) eeprom_data;
3902 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) {
3903 cksum += *e++;
3904 }
3905 if (cksum != match) {
3906 printf("%s: Checksum (%x) mismatch (%x)",
3907 device_xname(sc->sc_dev), cksum, match);
3908 }
3909
3910 /*
3911 * Unrolled because it makes slightly more sense this way.
3912 * The DP83815 stores the MAC address in bit 0 of word 6
3913 * through bit 15 of word 8.
3914 */
3915 ea = &eeprom_data[6];
3916 enaddr[0] = ((*ea & 0x1) << 7);
3917 ea++;
3918 enaddr[0] |= ((*ea & 0xFE00) >> 9);
3919 enaddr[1] = ((*ea & 0x1FE) >> 1);
3920 enaddr[2] = ((*ea & 0x1) << 7);
3921 ea++;
3922 enaddr[2] |= ((*ea & 0xFE00) >> 9);
3923 enaddr[3] = ((*ea & 0x1FE) >> 1);
3924 enaddr[4] = ((*ea & 0x1) << 7);
3925 ea++;
3926 enaddr[4] |= ((*ea & 0xFE00) >> 9);
3927 enaddr[5] = ((*ea & 0x1FE) >> 1);
3928
3929 /*
3930 * In case that's not weird enough, we also need to reverse
3931 * the bits in each byte. This all actually makes more sense
3932 * if you think about the EEPROM storage as an array of bits
3933 * being shifted into bytes, but that's not how we're looking
3934 * at it here...
3935 */
3936 for (i = 0; i < 6 ;i++)
3937 enaddr[i] = bbr(enaddr[i]);
3938 }
3939
3940 /*
3941 * sip_mediastatus: [ifmedia interface function]
3942 *
3943 * Get the current interface media status.
3944 */
3945 static void
3946 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
3947 {
3948 struct sip_softc *sc = ifp->if_softc;
3949
3950 if (!device_is_active(sc->sc_dev)) {
3951 ifmr->ifm_active = IFM_ETHER | IFM_NONE;
3952 ifmr->ifm_status = 0;
3953 return;
3954 }
3955 ether_mediastatus(ifp, ifmr);
3956 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) |
3957 sc->sc_flowflags;
3958 }
NetBSD on the FriendlyARM MINI2440