1 /* $NetBSD: if_sipreg.h,v 1.18 2007/12/15 05:46:21 dyoung Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * Copyright (c) 1999 Network Computer, Inc.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. Neither the name of Network Computer, Inc. nor the names of its
45 * contributors may be used to endorse or promote products derived
46 * from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
61 #ifndef _DEV_PCI_IF_SIPREG_H_
62 #define _DEV_PCI_IF_SIPREG_H_
65 * Register description for the Silicon Integrated Systems SiS 900,
66 * SiS 7016, National Semiconductor DP83815 10/100, and National
67 * Semiconduction DP83820 10/100/1000 PCI Ethernet controller.
69 * Written by Jason R. Thorpe for Network Computer, Inc.
73 * Transmit FIFO size. Used to compute the transmit drain threshold.
75 * On the SiS 900, the transmit FIFO is arranged as a 512 32-bit memory
78 * On the DP83820, we have an 8KB transmit FIFO.
80 #define DP83820_SIP_TXFIFO_SIZE 8192
81 #define OTHER_SIP_TXFIFO_SIZE (512 * 4)
84 * The SiS900 uses a single descriptor format for both transmit
85 * and receive descriptor chains.
87 * Note the DP83820 can use 64-bit DMA addresses for link and bufptr.
88 * However, we do not yet support that.
90 * For transmit, buffers need not be aligned. For receive, buffers
91 * must be aligned to 4-byte (8-byte on DP83820) boundaries.
94 u_int32_t sipd_link
; /* link to next descriptor */
95 uint32_t sipd_cbs
[2]; /* command/status and pointer to
98 u_int32_t sipd_extsts
; /* extended status */
102 * CMDSTS bits common to transmit and receive.
104 #define CMDSTS_OWN 0x80000000 /* owned by consumer */
105 #define CMDSTS_MORE 0x40000000 /* more descriptors */
106 #define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */
107 #define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */
108 #define CMDSTS_OK 0x08000000 /* packet ok */
109 #define DP83820_CMDSTS_SIZE_MASK 0x0000ffff /* packet size */
110 #define OTHER_CMDSTS_SIZE_MASK 0x000007ff /* packet size */
112 #define CMDSTS_SIZE(sc, x) ((x) & sc->sc_bits.b_cmdsts_size_mask)
115 * CMDSTS bits for transmit.
117 #define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */
118 #define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */
119 #define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */
120 #define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */
121 #define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */
122 #define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */
123 #define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */
124 #define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */
126 #define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16)
129 * CMDSTS bits for receive.
131 #define CMDSTS_Rx_RXA 0x04000000 /* receive abort */
132 #define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */
133 #define CMDSTS_Rx_DEST 0x01800000 /* destination class */
134 #define CMDSTS_Rx_LONG 0x00400000 /* packet too long */
135 #define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */
136 #define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */
137 #define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */
138 #define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */
139 #define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */
141 #define CMDSTS_Rx_IRL 0x00010000 /* in-range length error */
143 #define CMDSTS_Rx_COL 0x00010000 /* collision activity */
146 #define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */
147 #define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */
148 #define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */
149 #define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */
154 #define EXTSTS_Rx_UDPERR 0x00400000 /* UDP checksum error */
155 #define EXTSTS_UDPPKT 0x00200000 /* perform UDP checksum */
156 #define EXTSTS_Rx_TCPERR 0x00100000 /* TCP checksum error */
157 #define EXTSTS_TCPPKT 0x00080000 /* perform TCP checksum */
158 #define EXTSTS_Rx_IPERR 0x00040000 /* IP header checksum error */
159 #define EXTSTS_IPPKT 0x00020000 /* perform IP header checksum */
160 #define EXTSTS_VPKT 0x00010000 /* insert VLAN tag */
161 #define EXTSTS_VTCI 0x0000ffff /* VLAN tag control information */
164 * PCI Configuration space registers.
166 #define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00)
168 #define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04)
171 #define SIP_PCI_CFGMA1 (PCI_MAPREG_START + 0x08)
173 #define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */
175 #define SIP_PCI_CFGPMC 0x40 /* power management cap. */
177 #define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */
180 * MAC Operation Registers
182 #define SIP_CR 0x00 /* command register */
185 #define CR_RXPRI3 0x00010000 /* Rx priority queue select */
186 #define CR_RXPRI2 0x00008000 /* Rx priority queue select */
187 #define CR_RXPRI1 0x00004000 /* Rx priority queue select */
188 #define CR_RXPRI0 0x00002000 /* Rx priority queue select */
189 #define CR_TXPRI3 0x00001000 /* Tx priority queue select */
190 #define CR_TXPRI2 0x00000800 /* Tx priority queue select */
191 #define CR_TXPRI1 0x00000400 /* Tx priority queue select */
192 #define CR_TXPRI0 0x00000200 /* Tx priority queue select */
194 #define CR_RLD 0x00000400 /* reload from NVRAM */
195 #define CR_RST 0x00000100 /* software reset */
196 #define CR_SWI 0x00000080 /* software interrupt */
197 #define CR_RXR 0x00000020 /* receiver reset */
198 #define CR_TXR 0x00000010 /* transmit reset */
199 #define CR_RXD 0x00000008 /* receiver disable */
200 #define CR_RXE 0x00000004 /* receiver enable */
201 #define CR_TXD 0x00000002 /* transmit disable */
202 #define CR_TXE 0x00000001 /* transmit enable */
204 #define SIP_CFG 0x04 /* configuration register */
205 #define CFG_LNKSTS 0x80000000 /* link status (83815) */
207 #define CFG_SPEED1000 0x40000000 /* 1000Mb/s input pin */
208 #define CFG83820_SPEED100 0x20000000 /* 100Mb/s input pin */
209 #define CFG_DUPSTS 0x10000000 /* full-duplex status */
210 #define CFG_TBI_EN 0x01000000 /* ten-bit interface enable */
211 #define CFG_MODE_1000 0x00400000 /* 1000Mb/s mode enable */
212 #define CFG_PINT_DUP 0x00100000 /* interrupt on PHY DUP change */
213 #define CFG_PINT_LNK 0x00080000 /* interrupt on PHY LNK change */
214 #define CFG_PINT_SPD 0x00040000 /* interrupt on PHY SPD change */
215 #define CFG_TMRTEST 0x00020000 /* timer test mode */
216 #define CFG_MRM_DIS 0x00010000 /* MRM disable */
217 #define CFG_MWI_DIS 0x00008000 /* MWI disable */
218 #define CFG_T64ADDR 0x00004000 /* target 64-bit addressing enable */
219 #define CFG_PCI64_DET 0x00002000 /* 64-bit PCI bus detected */
220 #define CFG_DATA64_EN 0x00001000 /* 64-bit data enable */
221 #define CFG_M64ADDR 0x00000800 /* master 64-bit addressing enable */
223 #define CFG83815_SPEED100 0x40000000 /* 100Mb/s (83815) */
224 #define CFG_FDUP 0x20000000 /* full duplex (83815) */
225 #define CFG_POL 0x10000000 /* 10Mb/s polarity (83815) */
226 #define CFG_ANEG_DN 0x08000000 /* autonegotiation done (83815) */
227 #define CFG_PHY_CFG 0x00fc0000 /* PHY configuration (83815) */
228 #define CFG_PINT_ACEN 0x00020000 /* PHY interrupt auto clear (83815) */
229 #define CFG_PAUSE_ADV 0x00010000 /* pause advertise (83815) */
230 #define CFG_ANEG_SEL 0x0000e000 /* autonegotiation select (83815) */
232 #define CFG_PHY_RST 0x00000400 /* PHY reset (83815) */
233 #define CFG_PHY_DIS 0x00000200 /* PHY disable (83815) */
235 #define CFG_EXTSTS_EN 0x00000100 /* extended status enable */
237 #define CFG_EUPHCOMP 0x00000100 /* 83810 descriptor compat (83815) */
239 #define CFG_EDBMASTEN 0x00002000 /* 635,900B ?? from linux driver */
240 #define CFG_RNDCNT 0x00000400 /* 635,900B ?? from linux driver */
241 #define CFG_FAIRBO 0x00000200 /* 635,900B ?? from linux driver */
242 #define CFG_REQALG 0x00000080 /* PCI bus request alg. */
243 #define CFG_SB 0x00000040 /* single backoff */
244 #define CFG_POW 0x00000020 /* program out of window timer */
245 #define CFG_EXD 0x00000010 /* excessive defferal timer disable */
246 #define CFG_PESEL 0x00000008 /* parity error detection action */
248 #define CFG_BROM_DIS 0x00000004 /* boot ROM disable */
249 #define CFG_EXT_125 0x00000002 /* external 125MHz reference select */
251 #define CFG_BEM 0x00000001 /* big-endian mode */
253 #define SIP_EROMAR 0x08 /* EEPROM access register */
254 #define EROMAR_REQ 0x00000400 /* SiS 96x specific */
255 #define EROMAR_DONE 0x00000200 /* SiS 96x specific */
256 #define EROMAR_GNT 0x00000100 /* SiS 96x specific */
257 #define EROMAR_MDC 0x00000040 /* MII clock */
258 #define EROMAR_MDDIR 0x00000020 /* MII direction (1 == MAC->PHY) */
259 #define EROMAR_MDIO 0x00000010 /* MII data */
260 #define EROMAR_EECS 0x00000008 /* chip select */
261 #define EROMAR_EESK 0x00000004 /* clock */
262 #define EROMAR_EEDO 0x00000002 /* data out */
263 #define EROMAR_EEDI 0x00000001 /* data in */
265 #define SIP_PTSCR 0x0c /* PCI test control register */
266 #define PTSCR_RBIST_RST 0x00002000 /* SRAM BIST reset */
267 #define PTSCR_RBIST_EN 0x00000400 /* SRAM BIST enable */
268 #define PTSCR_RBIST_DONE 0x00000200 /* SRAM BIST done */
269 #define PTSCR_RBIST_RX1FAIL 0x00000100 /* Rx status FIFO BIST fail */
270 #define PTSCR_RBIST_RX0FAIL 0x00000080 /* Rx data FIFO BIST fail */
271 #define PTSCR_RBIST_TX0FAIL 0x00000020 /* Tx data FIFO BIST fail */
272 #define PTSCR_RBIST_HFFAIL 0x00000010 /* hash filter BIST fail */
273 #define PTSCR_RBIST_RXFAIL 0x00000008 /* Rx filter BIST failed */
274 #define PTSCR_EELOAD_EN 0x00000004 /* EEPROM load initiate */
275 #define PTSCR_EEBIST_EN 0x00000002 /* EEPROM BIST enable */
276 #define PTSCR_EEBIST_FAIL 0x00000001 /* EEPROM BIST failed */
277 #define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */
278 #define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */
279 #define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */
280 #define PTSCR_BMTEN 0x00000200 /* bus master test enable */
281 #define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */
282 #define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */
283 #define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */
284 #define PTSCR_SRAMADR 0x0000001f /* status RAM address */
286 #define SIP_ISR 0x10 /* interrupt status register */
288 #define ISR_TXDESC3 0x40000000 /* Tx queue 3 */
289 #define ISR_TXDESC2 0x20000000 /* Tx queue 2 */
290 #define ISR_TXDESC1 0x10000000 /* Tx queue 1 */
291 #define ISR_TXDESC0 0x08000000 /* Tx queue 0 */
292 #define ISR_RXDESC3 0x04000000 /* Rx queue 3 */
293 #define ISR_RXDESC2 0x02000000 /* Rx queue 2 */
294 #define ISR_RXDESC1 0x01000000 /* Rx queue 1 */
295 #define ISR_RXDESC0 0x00800000 /* Rx queue 0 */
297 /* non-DP83820 only */
298 #define ISR_WAKEEVT 0x10000000 /* wake up event */
302 #define ISR_TXRCMP 0x00400000 /* transmit reset complete */
303 #define ISR_RXRCMP 0x00200000 /* receive reset complete */
304 #define ISR_DPERR 0x00100000 /* detected parity error */
305 #define ISR_SSERR 0x00080000 /* signalled system error */
306 #define ISR_RMABT 0x00040000 /* received master abort */
307 #define ISR_RTABT 0x00020000 /* received target abort */
309 #define ISR_TXRCMP 0x02000000 /* transmit reset complete */
310 #define ISR_RXRCMP 0x01000000 /* receive reset complete */
311 #define ISR_DPERR 0x00800000 /* detected parity error */
312 #define ISR_SSERR 0x00400000 /* signalled system error */
313 #define ISR_RMABT 0x00200000 /* received master abort */
314 #define ISR_RTABT 0x00100000 /* received target abort */
319 #define ISR_PAUSE_END 0x08000000 /* end of transmission pause */
320 #define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */
322 #define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */
323 #define ISR_HIBERR 0x00008000 /* high bits error set */
326 #define ISR_PHY 0x00004000 /* PHY interrupt */
327 #define ISR_PME 0x00002000 /* power management event */
329 #define ISR_SWI 0x00001000 /* software interrupt */
332 #define ISR_MIB 0x00000800 /* MIB service */
334 #define ISR_TXURN 0x00000400 /* Tx underrun */
335 #define ISR_TXIDLE 0x00000200 /* Tx idle */
336 #define ISR_TXERR 0x00000100 /* Tx error */
337 #define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */
338 #define ISR_TXOK 0x00000040 /* Tx okay */
339 #define ISR_RXORN 0x00000020 /* Rx overrun */
340 #define ISR_RXIDLE 0x00000010 /* Rx idle */
341 #define ISR_RXEARLY 0x00000008 /* Rx early */
342 #define ISR_RXERR 0x00000004 /* Rx error */
343 #define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */
344 #define ISR_RXOK 0x00000001 /* Rx okay */
346 #define SIP_IMR 0x14 /* interrupt mask register */
347 /* See bits in SIP_ISR */
349 #define SIP_IER 0x18 /* interrupt enable register */
350 #define IER_IE 0x00000001 /* master interrupt enable */
353 #define SIP_IHR 0x1c /* interrupt hold-off register */
354 #define IHR_IHCTL 0x00000100 /* interrupt hold-off control */
355 #define IHR_IH 0x000000ff /* interrupt hold-off timer (100us) */
357 #define SIP_ENPHY 0x1c /* enhanced PHY access register */
358 #define ENPHY_PHYDATA 0xffff0000 /* PHY data */
359 #define ENPHY_DATA_SHIFT 16
360 #define ENPHY_PHYADDR 0x0000f800 /* PHY number (7016 only) */
361 #define ENPHY_PHYADDR_SHIFT 11
362 #define ENPHY_REGADDR 0x000007c0 /* PHY register */
363 #define ENPHY_REGADDR_SHIFT 6
364 #define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */
365 #define ENPHY_ACCESS 0x00000010 /* PHY access enable */
368 #define SIP_TXDP 0x20 /* transmit descriptor pointer reg */
371 #define SIP_TXDP_HI 0x24 /* transmit descriptor pointer (high) reg */
373 #define DP83820_SIP_TXCFG 0x28 /* transmit configuration register */
374 #define OTHER_SIP_TXCFG 0x24 /* transmit configuration register */
376 #define TXCFG_CSI 0x80000000 /* carrier sense ignore */
377 #define TXCFG_HBI 0x40000000 /* heartbeat ignore */
378 #define TXCFG_MLB 0x20000000 /* MAC loopback */
379 #define TXCFG_ATP 0x10000000 /* automatic transmit padding */
380 #define TXCFG_MXDMA 0x00700000 /* max DMA burst size */
383 #define TXCFG_ECRETRY 0x008000000 /* excessive collision retry enable */
384 #define TXCFG_BRST_DIS 0x00080000 /* 1000Mb/s burst disable */
387 #define TXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */
390 #define TXCFG_MXDMA_8 0x00100000 /* 8 bytes */
391 #define TXCFG_MXDMA_16 0x00200000 /* 16 bytes */
392 #define TXCFG_MXDMA_32 0x00300000 /* 32 bytes */
393 #define TXCFG_MXDMA_64 0x00400000 /* 64 bytes */
394 #define TXCFG_MXDMA_128 0x00500000 /* 128 bytes */
395 #define TXCFG_MXDMA_256 0x00600000 /* 256 bytes */
396 #define TXCFG_MXDMA_512 0x00700000 /* 512 bytes */
397 #define TXCFG_FLTH_MASK 0x0000ff00 /* Fx fill threshold */
398 #define TXCFG_DRTH_MASK 0x000000ff /* Tx drain threshold */
400 #define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */
401 #define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */
402 #define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */
403 #define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */
404 #define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */
405 #define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */
406 #define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */
407 #define TXCFG_FLTH_MASK 0x00003f00 /* Tx fill threshold */
408 #define TXCFG_DRTH_MASK 0x0000003f /* Tx drain threshold */
412 /* non-DP83820 only */
413 #define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */
415 #define SIP_GPIOR 0x2c /* general purpose i/o register */
416 #define GPIOR_GP5_IN 0x00004000 /* GP 5 in */
417 #define GPIOR_GP4_IN 0x00002000 /* GP 4 in */
418 #define GPIOR_GP3_IN 0x00001000 /* GP 3 in */
419 #define GPIOR_GP2_IN 0x00000800 /* GP 2 in */
420 #define GPIOR_GP1_IN 0x00000400 /* GP 1 in */
421 #define GPIOR_GP5_OE 0x00000200 /* GP 5 out enable */
422 #define GPIOR_GP4_OE 0x00000100 /* GP 4 out enable */
423 #define GPIOR_GP3_OE 0x00000080 /* GP 3 out enable */
424 #define GPIOR_GP2_OE 0x00000040 /* GP 2 out enable */
425 #define GPIOR_GP1_OE 0x00000020 /* GP 1 out enable */
426 #define GPIOR_GP5_OUT 0x00000010 /* GP 5 out */
427 #define GPIOR_GP4_OUT 0x00000008 /* GP 4 out */
428 #define GPIOR_GP3_OUT 0x00000004 /* GP 3 out */
429 #define GPIOR_GP2_OUT 0x00000002 /* GP 2 out */
430 #define GPIOR_GP1_OUT 0x00000001 /* GP 1 out */
432 #define SIP_RXDP 0x30 /* receive descriptor pointer reg */
435 #define SIP_RXDP_HI 0x34 /* receive descriptor pointer (high) reg */
437 #define DP83820_SIP_RXCFG 0x38 /* receive configuration register */
438 #define OTHER_SIP_RXCFG 0x34 /* receive configuration register */
439 #define RXCFG_AEP 0x80000000 /* accept error packets */
440 #define RXCFG_ARP 0x40000000 /* accept runt packets */
442 #define RXCFG_STRIPCRC 0x20000000 /* strip CRC */
444 #define RXCFG_ATX 0x10000000 /* accept transmit packets */
445 #define RXCFG_ALP 0x08000000 /* accept long packets */
448 #define RXCFG_AIRL 0x04000000 /* accept in-range length err packets */
450 #define RXCFG_MXDMA 0x00700000 /* max DMA burst size */
453 #define RXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */
457 #define RXCFG_MXDMA_8 0x00100000 /* 8 bytes */
458 #define RXCFG_MXDMA_16 0x00200000 /* 16 bytes */
459 #define RXCFG_MXDMA_32 0x00300000 /* 32 bytes */
460 #define RXCFG_MXDMA_64 0x00400000 /* 64 bytes */
461 #define RXCFG_MXDMA_128 0x00500000 /* 128 bytes */
462 #define RXCFG_MXDMA_256 0x00600000 /* 256 bytes */
463 #define RXCFG_MXDMA_512 0x00700000 /* 512 bytes */
465 #define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */
466 #define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */
467 #define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */
468 #define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */
469 #define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */
470 #define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */
471 #define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */
475 /* non-DP83820 only */
476 #define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */
477 #define RXCFG_DRTH_MASK 0x0000003e
480 #define SIP_PQCR 0x3c /* priority queueing control register */
481 #define PQCR_RXPQ_4 0x0000000c /* 4 Rx queues */
482 #define PQCR_RXPQ_3 0x00000008 /* 3 Rx queues */
483 #define PQCR_RXPQ_2 0x00000004 /* 2 Rx queues */
484 #define PQCR_TXFAIR 0x00000002 /* Tx fairness enable */
485 #define PQCR_TXPQEN 0x00000001 /* Tx priority queueing enable */
488 #define SIP83815_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */
489 #define CCSR_PMESTS 0x00008000 /* PME status */
490 #define CCSR_PMEEN 0x00000100 /* PME enable */
491 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
494 #define SIP_FLOWCTL 0x38 /* flow control register */
495 #define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */
496 #define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */
498 #define SIP_NS_WCSR 0x40 /* WoL control/status register (83815/83820) */
500 #define SIP_NS_PCR 0x44 /* pause control/status reg (83815/83820) */
501 #define PCR_PSEN 0x80000000 /* pause enable */
502 #define PCR_PS_MCAST 0x40000000 /* pause on multicast */
503 #define PCR_PS_DA 0x20000000 /* pause on DA */
504 #define PCR_PS_ACT 0x10000000 /* pause active */
505 #define PCR_PS_RCVD 0x08000000 /* pause packet recieved */
507 #define PCR_PS_STHI_8 0x03000000 /* Status FIFO Hi Threshold (8packets) */
508 #define PCR_PS_STHI_4 0x02000000 /* Status FIFO Hi Threshold (4packets) */
509 #define PCR_PS_STHI_2 0x01000000 /* Status FIFO Hi Threshold (2packets) */
510 #define PCR_PS_STHI_0 0x00000000 /* Status FIFO Hi Threshold (disable) */
511 #define PCR_PS_STLO_8 0x00c00000 /* Status FIFO Lo Threshold (8packets) */
512 #define PCR_PS_STLO_4 0x00800000 /* Status FIFO Lo Threshold (4packets) */
513 #define PCR_PS_STLO_2 0x00400000 /* Status FIFO Lo Threshold (2packets) */
514 #define PCR_PS_STLO_0 0x00000000 /* Status FIFO Lo Threshold (disable) */
515 #define PCR_PS_FFHI_8 0x00300000 /* Data FIFO Hi Threshold (8Kbyte) */
516 #define PCR_PS_FFHI_4 0x00200000 /* Data FIFO Hi Threshold (4Kbyte) */
517 #define PCR_PS_FFHI_2 0x00100000 /* Data FIFO Hi Threshold (2Kbyte) */
518 #define PCR_PS_FFHI_0 0x00000000 /* Data FIFO Hi Threshold (disable) */
519 #define PCR_PS_FFLO_8 0x000c0000 /* Data FIFO Lo Threshold (8Kbyte) */
520 #define PCR_PS_FFLO_4 0x00080000 /* Data FIFO Lo Threshold (4Kbyte) */
521 #define PCR_PS_FFLO_2 0x00040000 /* Data FIFO Lo Threshold (2Kbyte) */
522 #define PCR_PS_FFLO_0 0x00000000 /* Data FIFO Lo Threshold (disable) */
523 #define PCR_PS_TX 0x00020000 /* Transmit PAUSE frame manually */
525 #define PCR_PSNEG 0x00200000 /* Pause Negoticated (83815) */
526 #define PCR_MLD_EN 0x00010000 /* Manual Load Enable (83815) */
528 #define PCR_PAUSE_CNT_MASK 0x0000ffff /* pause count mask */
529 #define PCR_PAUSE_CNT 65535 /* pause count (512bit-time) */
531 #define SIP_RFCR 0x48 /* receive filter control register */
532 #define RFCR_RFEN 0x80000000 /* Rx filter enable */
533 #define RFCR_AAB 0x40000000 /* accept all broadcast */
534 #define RFCR_AAM 0x20000000 /* accept all multicast */
535 #define RFCR_AAP 0x10000000 /* accept all physical */
536 #define RFCR_APM 0x08000000 /* accept perfect match (83815) */
537 #define RFCR_APAT 0x07800000 /* accept pattern match (83815) */
538 #define RFCR_AARP 0x00400000 /* accept ARP (83815) */
539 #define RFCR_MHEN 0x00200000 /* multicast hash enable (83815) */
540 #define RFCR_UHEN 0x00100000 /* unicast hash enable (83815) */
541 #define RFCR_ULM 0x00080000 /* U/L bit mask (83815) */
542 #define RFCR_NS_RFADDR 0x000003ff /* Rx filter ext reg address (83815) */
543 #define RFCR_RFADDR 0x000f0000 /* Rx filter address */
544 #define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */
545 #define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */
546 #define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */
547 #define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */
548 #define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */
549 #define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */
550 #define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */
551 #define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */
552 #define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */
553 #define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */
554 #define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */
555 /* For SiS900B and 635/735 only */
556 #define RFCR_RFADDR_MC8 0x000c0000 /* multicast hash word 8 */
557 #define RFCR_RFADDR_MC9 0x000d0000 /* multicast hash word 9 */
558 #define RFCR_RFADDR_MC10 0x000e0000 /* multicast hash word 10 */
559 #define RFCR_RFADDR_MC11 0x000f0000 /* multicast hash word 11 */
560 #define RFCR_RFADDR_MC12 0x00100000 /* multicast hash word 12 */
561 #define RFCR_RFADDR_MC13 0x00110000 /* multicast hash word 13 */
562 #define RFCR_RFADDR_MC14 0x00120000 /* multicast hash word 14 */
563 #define RFCR_RFADDR_MC15 0x00130000 /* multicast hash word 15 */
565 #define RFCR_NS_RFADDR_PMATCH0 0x0000 /* perfect match octets 1-0 */
566 #define RFCR_NS_RFADDR_PMATCH2 0x0002 /* perfect match octets 3-2 */
567 #define RFCR_NS_RFADDR_PMATCH4 0x0004 /* perfect match octets 5-4 */
568 #define RFCR_NS_RFADDR_PCOUNT 0x0006 /* pattern count */
571 #define RFCR_NS_RFADDR_PCOUNT2 0x0008 /* pattern count 2, 3 */
572 #define RFCR_NS_RFADDR_SOPAS0 0x000a /* SecureOn 0, 1 */
573 #define RFCR_NS_RFADDR_SOPAS2 0x000c /* SecureOn 2, 3 */
574 #define RFCR_NS_RFADDR_SOPAS4 0x000e /* SecureOn 4, 5 */
575 #define RFCR_NS_RFADDR_PATMEM 0x0200 /* pattern memory */
577 #define DP83820_RFCR_NS_RFADDR_FILTMEM 0x0100 /* hash memory */
578 #define OTHER_RFCR_NS_RFADDR_FILTMEM 0x0200 /* filter memory (hash/pattern) */
580 #define SIP_RFDR 0x4c /* receive filter data register */
581 #define RFDR_BMASK 0x00030000 /* byte mask (83815) */
582 #define RFDR_DATA 0x0000ffff /* data bits */
584 #define SIP_NS_BRAR 0x50 /* boot rom address (83815) */
585 #define BRAR_AUTOINC 0x80000000 /* autoincrement */
586 #define BRAR_ADDR 0x0000ffff /* address */
588 #define SIP_NS_BRDR 0x54 /* boot rom data (83815) */
590 #define SIP_NS_SRR 0x58 /* silicon revision register (83815) */
592 #define SRR_REV_B 0x00000103
594 #define SRR_REV_A 0x00000101
595 #define SRR_REV_B_1 0x00000200
596 #define SRR_REV_B_2 0x00000201
597 #define SRR_REV_B_3 0x00000203
598 #define SRR_REV_C_1 0x00000300
599 #define SRR_REV_C_2 0x00000302
602 #define SIP_NS_MIBC 0x5c /* mib control register (83815) */
603 #define MIBC_MIBS 0x00000008 /* mib counter strobe */
604 #define MIBC_ACLR 0x00000004 /* clear all counters */
605 #define MIBC_FRZ 0x00000002 /* freeze all counters */
606 #define MIBC_WRN 0x00000001 /* warning test indicator */
608 #define SIP_NS_MIB(mibreg) /* mib data registers (83815) */ \
610 #define MIB_RXErroredPkts 0x00
611 #define MIB_RXFCSErrors 0x04
612 #define MIB_RXMsdPktErrors 0x08
613 #define MIB_RXFAErrors 0x0c
614 #define MIB_RXSymbolErrors 0x10
615 #define MIB_RXFrameTooLong 0x14
617 #define MIB_RXIRLErrors 0x18
618 #define MIB_RXBadOpcodes 0x1c
619 #define MIB_RXPauseFrames 0x20
620 #define MIB_TXPauseFrames 0x24
621 #define MIB_TXSQEErrors 0x28
623 #define MIB_RXTXSQEErrors 0x18
627 #define SIP_NS_PHY(miireg) /* PHY registers (83815) */ \
628 (0x80 + ((miireg) << 2))
631 #define SIP_TXDP1 0xa0 /* transmit descriptor pointer (pri 1) */
633 #define SIP_TXDP2 0xa4 /* transmit descriptor pointer (pri 2) */
635 #define SIP_TXDP3 0xa8 /* transmit descriptor pointer (pri 3) */
637 #define SIP_RXDP1 0xb0 /* receive descriptor pointer (pri 1) */
639 #define SIP_RXDP2 0xb4 /* receive descriptor pointer (pri 2) */
641 #define SIP_RXDP3 0xb8 /* receive descriptor pointer (pri 3) */
643 #define SIP_VRCR 0xbc /* VLAN/IP receive control register */
644 #define VRCR_RUDPE 0x00000080 /* reject UDP checksum errors */
645 #define VRCR_RTCPE 0x00000040 /* reject TCP checksum errors */
646 #define VRCR_RIPE 0x00000020 /* reject IP checksum errors */
647 #define VRCR_IPEN 0x00000010 /* IP checksum enable */
648 #define VRCR_DUTF 0x00000008 /* discard untagged frames */
649 #define VRCR_DVTF 0x00000004 /* discard VLAN tagged frames */
650 #define VRCR_VTREN 0x00000002 /* VLAN tag removal enable */
651 #define VRCR_VTDEN 0x00000001 /* VLAN tag detection enable */
653 #define SIP_VTCR 0xc0 /* VLAN/IP transmit control register */
654 #define VTCR_PPCHK 0x00000008 /* per-packet checksum generation */
655 #define VTCR_GCHK 0x00000004 /* global checksum generation */
656 #define VTCR_VPPTI 0x00000002 /* VLAN per-packet tag insertion */
657 #define VTCR_VGTI 0x00000001 /* VLAN global tag insertion */
659 #define SIP_VDR 0xc4 /* VLAN data register */
660 #define VDR_VTCI 0xffff0000 /* VLAN tag control information */
661 #define VDR_VTYPE 0x0000ffff /* VLAN type field */
663 #define SIP83820_NS_CCSR 0xcc /* CLKRUN control/status register (83820) */
665 #define CCSR_PMESTS 0x00008000 /* PME status */
666 #define CCSR_PMEEN 0x00000100 /* PME enable */
667 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
670 #define SIP_TBICR 0xe0 /* TBI control register */
671 #define TBICR_MR_LOOPBACK 0x00004000 /* TBI PCS loopback enable */
672 #define TBICR_MR_AN_ENABLE 0x00001000 /* TBI autonegotiation enable */
673 #define TBICR_MR_RESTART_AN 0x00000200 /* restart TBI autoneogtiation */
675 #define SIP_TBISR 0xe4 /* TBI status register */
676 #define TBISR_MR_LINK_STATUS 0x00000020 /* TBI link status */
677 #define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI autonegotiation complete */
679 #define SIP_TANAR 0xe8 /* TBI autoneg adv. register */
680 #define TANAR_NP 0x00008000 /* next page exchange required */
681 #define TANAR_RF2 0x00002000 /* remote fault 2 */
682 #define TANAR_RF1 0x00001000 /* remote fault 1 */
683 #define TANAR_PS2 0x00000100 /* pause encoding 2 */
684 #define TANAR_PS1 0x00000080 /* pause encoding 1 */
685 #define TANAR_HALF_DUP 0x00000040 /* adv. half duplex */
686 #define TANAR_FULL_DUP 0x00000020 /* adv. full duplex */
688 #define SIP_TANLPAR 0xec /* TBI autoneg link partner ability register */
691 #define SIP_TANER 0xf0 /* TBI autoneg expansion register */
692 #define TANER_NPA 0x00000004 /* we support next page function */
693 #define TANER_PR 0x00000002 /* page received from link partner */
695 #define SIP_TESR 0xf4 /* TBI extended status register */
696 #define TESR_1000FDX 0x00008000 /* we support 1000base FDX */
697 #define TESR_1000HDX 0x00004000 /* we support 1000base HDX */
699 #define SIP_PMCTL 0xb0 /* power management control register */
700 #define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */
701 #define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */
702 #define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */
703 #define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */
704 #define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */
705 #define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */
706 #define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */
707 #define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */
708 #define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */
709 #define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */
710 #define PMCTL_LINKON 0x00000002 /* link on monitor enable */
711 #define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */
713 #define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */
714 #define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */
715 #define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */
716 #define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */
717 #define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */
718 #define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */
719 #define PMEVT_ONEVT 0x00000002 /* link on event */
720 #define PMEVT_LOSSEVT 0x00000001 /* link loss event */
722 #define SIP_WAKECRC 0xbc /* wake-up frame CRC register */
724 #define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */
725 #define SIP_WAKEMASK1 0xc4
726 #define SIP_WAKEMASK2 0xc8
727 #define SIP_WAKEMASK3 0xcc
728 #define SIP_WAKEMASK4 0xe0
729 #define SIP_WAKEMASK5 0xe4
730 #define SIP_WAKEMASK6 0xe8
731 #define SIP_WAKEMASK7 0xec
735 * Revision codes for the SiS 630 chipset built-in Ethernet.
737 #define SIS_REV_900B 0x03
738 #define SIS_REV_630E 0x81
739 #define SIS_REV_630S 0x82
740 #define SIS_REV_630EA1 0x83
741 #define SIS_REV_630ET 0x84
742 #define SIS_REV_635 0x90 /* same for 735 (745?) */
743 #define SIS_REV_960 0x91
746 * MII operations for recent SiS chipsets
748 #define SIS_MII_STARTDELIM 0x01
749 #define SIS_MII_READOP 0x02
750 #define SIS_MII_WRITEOP 0x01
751 #define SIS_MII_TURNAROUND 0x02
754 * Serial EEPROM opcodes, including the start bit.
756 #define SIP_EEPROM_OPC_ERASE 0x04
757 #define SIP_EEPROM_OPC_WRITE 0x05
758 #define SIP_EEPROM_OPC_READ 0x06
761 * Serial EEPROM address map (byte address) for the SiS900.
763 #define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */
764 #define SIP_EEPROM_MASK 0x02 /* `enable' mask */
765 #define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */
766 #define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */
767 #define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */
768 #define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */
769 #define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */
770 #define SIP_EEPROM_reserved 0x0e /* reserved */
771 #define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */
772 #define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */
773 #define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */
774 #define SIP_EEPROM_CHECKSUM 0x16 /* checksum */
777 * Serial EEPROM data (byte addresses) for the DP83815.
779 #define SIP_DP83815_EEPROM_CHECKSUM 0x16 /* checksum */
780 #define SIP_DP83815_EEPROM_LENGTH 0x18 /* length of EEPROM data */
783 * Serial EEPROM data (byte addresses) for the DP83820.
785 #define SIP_DP83820_EEPROM_SUBSYSTEM_ID 0x00 /* PCI subsystem ID */
786 #define SIP_DP83820_EEPROM_SUBVENDOR_ID 0x02 /* PCI subvendor ID */
787 #define SIP_DP83820_EEPROM_CFGINT 0x04 /* PCI INT [31:16] */
788 #define SIP_DP83820_EEPROM_CONFIG0 0x06 /* configuration word 0 */
789 #define SIP_DP83820_EEPROM_CONFIG1 0x08 /* configuration word 1 */
790 #define SIP_DP83820_EEPROM_CONFIG2 0x0a /* configuration word 2 */
791 #define SIP_DP83820_EEPROM_CONFIG3 0x0c /* configuration word 3 */
792 #define SIP_DP83820_EEPROM_SOPAS0 0x0e /* SecureOn [47:32] */
793 #define SIP_DP83820_EEPROM_SOPAS1 0x10 /* SecureOn [31:16] */
794 #define SIP_DP83820_EEPROM_SOPAS2 0x12 /* SecureOn [15:0] */
795 #define SIP_DP83820_EEPROM_PMATCH0 0x14 /* MAC [47:32] */
796 #define SIP_DP83820_EEPROM_PMATCH1 0x16 /* MAC [31:16] */
797 #define SIP_DP83820_EEPROM_PMATCH2 0x18 /* MAC [15:0] */
798 #define SIP_DP83820_EEPROM_CHECKSUM 0x1a /* checksum */
799 #define SIP_DP83820_EEPROM_LENGTH 0x1c /* length of EEPROM data */
801 #define DP83820_CONFIG2_CFG_EXT_125 (1U << 0)
802 #define DP83820_CONFIG2_CFG_M64ADDR (1U << 1)
803 #define DP83820_CONFIG2_CFG_DATA64_EN (1U << 2)
804 #define DP83820_CONFIG2_CFG_T64ADDR (1U << 3)
805 #define DP83820_CONFIG2_CFG_MWI_DIS (1U << 4)
806 #define DP83820_CONFIG2_CFG_MRM_DIS (1U << 5)
807 #define DP83820_CONFIG2_CFG_MODE_1000 (1U << 7)
808 #define DP83820_CONFIG2_CFG_TBI_EN (1U << 9)
810 #endif /* _DEV_PCI_IF_SIPREG_H_ */
