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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_tireg.h
blobcc966e36c10984f38b01bb4f2966b6fe261240c4
1 /* $NetBSD: if_tireg.h,v 1.18 2007/03/04 06:02:23 christos Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * FreeBSD Id: if_tireg.h,v 1.9 1999/07/27 03:54:48 wpaul Exp
35 */
36
37 /*
38 * Tigon register offsets. These are memory mapped registers
39 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
40 * Each register must be accessed using 32 bit operations.
41 *
42 * All reegisters are accessed through a 16K shared memory block.
43 * The first group of registers are actually copies of the PCI
44 * configuration space registers.
45 */
46
47 /*
48 * Tigon configuration and control registers.
49 */
50 #define TI_MISC_HOST_CTL 0x040
51 #define TI_MISC_LOCAL_CTL 0x044
52 #define TI_SEM_AB 0x048 /* Tigon 2 only */
53 #define TI_MISC_CONF 0x050 /* Tigon 2 only */
54 #define TI_TIMER_BITS 0x054
55 #define TI_TIMERREF 0x058
56 #define TI_PCI_STATE 0x05C
57 #define TI_MAIN_EVENT_A 0x060
58 #define TI_MAILBOX_EVENT_A 0x064
59 #define TI_WINBASE 0x068
60 #define TI_WINDATA 0x06C
61 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */
62 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */
63 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */
64 #define TI_SERIAL 0x07C
65
66 /*
67 * Misc host control bits.
68 */
69 #define TI_MHC_INTSTATE 0x00000001
70 #define TI_MHC_CLEARINT 0x00000002
71 #define TI_MHC_RESET 0x00000008
72 #define TI_MHC_BYTE_SWAP_ENB 0x00000010
73 #define TI_MHC_WORD_SWAP_ENB 0x00000020
74 #define TI_MHC_MASK_INTS 0x00000040
75 #define TI_MHC_CHIP_REV_MASK 0xF0000000
76
77 #define TI_MHC_BIGENDIAN_INIT \
78 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
79
80 #define TI_MHC_LITTLEENDIAN_INIT \
81 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT)
82
83 /*
84 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2.
85 * Rev 5 is also the Tigon 2, but is a broken version which was never
86 * used in any actual hardware, so we ignore it.
87 */
88 #define TI_REV_TIGON_I 0x40000000
89 #define TI_REV_TIGON_II 0x60000000
90
91 /*
92 * Firmware revision that we want.
93 */
94 #define TI_FIRMWARE_MAJOR 0xc
95 #define TI_FIRMWARE_MINOR 0x4
96 #define TI_FIRMWARE_FIX 0xd
97
98 /*
99 * Miscelaneous Local Control register.
100 */
101 #define TI_MLC_EE_WRITE_ENB 0x00000010
102 #define TI_MLC_SRAM_BANK_256K 0x00000200
103 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */
104 #define TI_MLC_LOCALADDR_21 0x00004000
105 #define TI_MLC_LOCALADDR_22 0x00008000
106 #define TI_MLC_SBUS_WRITEERR 0x00080000
107 #define TI_MLC_EE_CLK 0x00100000
108 #define TI_MLC_EE_TXEN 0x00200000
109 #define TI_MLC_EE_DOUT 0x00400000
110 #define TI_MLC_EE_DIN 0x00800000
111
112 /*
113 * Offset of MAC address inside EEPROM.
114 */
115 #define TI_EE_MAC_OFFSET 0x8c
116
117 #define TI_DMA_ASSIST 0x11C
118 #define TI_CPU_STATE 0x140
119 #define TI_CPU_PROGRAM_COUNTER 0x144
120 #define TI_SRAM_ADDR 0x154
121 #define TI_SRAM_DATA 0x158
122 #define TI_GEN_0 0x180
123 #define TI_GEN_X 0x1FC
124 #define TI_MAC_TX_STATE 0x200
125 #define TI_MAC_RX_STATE 0x220
126 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */
127 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */
128 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */
129 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */
130 #define TI_GEN_B_0 0x280 /* Tigon 2 only */
131 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */
132
133 /*
134 * Misc config register.
135 */
136 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */
137
138 /*
139 * PCI state register.
140 */
141 #define TI_PCISTATE_FORCE_RESET 0x00000001
142 #define TI_PCISTATE_PROVIDE_LEN 0x00000002
143 #define TI_PCISTATE_READ_MAXDMA 0x0000001C
144 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0
145 #define TI_PCISTATE_MINDMA 0x0000FF00
146 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000
147 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000
148 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000
149 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000
150 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */
151 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */
152 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */
153 #define TI_PCISTATE_READ_CMD 0x0F000000
154 #define TI_PCISTATE_WRITE_CMD 0xF0000000
155
156 #define TI_PCI_READMAX_4 0x04
157 #define TI_PCI_READMAX_16 0x08
158 #define TI_PCI_READMAX_32 0x0C
159 #define TI_PCI_READMAX_64 0x10
160 #define TI_PCI_READMAX_128 0x14
161 #define TI_PCI_READMAX_256 0x18
162 #define TI_PCI_READMAX_1024 0x1C
163
164 #define TI_PCI_WRITEMAX_4 0x20
165 #define TI_PCI_WRITEMAX_16 0x40
166 #define TI_PCI_WRITEMAX_32 0x60
167 #define TI_PCI_WRITEMAX_64 0x80
168 #define TI_PCI_WRITEMAX_128 0xA0
169 #define TI_PCI_WRITEMAX_256 0xC0
170 #define TI_PCI_WRITEMAX_1024 0xE0
171
172 #define TI_PCI_READ_CMD 0x06000000
173 #define TI_PCI_WRITE_CMD 0x70000000
174
175 /*
176 * DMA state register.
177 */
178 #define TI_DMASTATE_ENABLE 0x00000001
179 #define TI_DMASTATE_PAUSE 0x00000002
180
181 /*
182 * CPU state register.
183 */
184 #define TI_CPUSTATE_RESET 0x00000001
185 #define TI_CPUSTATE_STEP 0x00000002
186 #define TI_CPUSTATE_ROMFAIL 0x00000010
187 #define TI_CPUSTATE_HALT 0x00010000
188 /*
189 * MAC TX state register
190 */
191 #define TI_TXSTATE_RESET 0x00000001
192 #define TI_TXSTATE_ENB 0x00000002
193 #define TI_TXSTATE_STOP 0x00000004
194
195 /*
196 * MAC RX state register
197 */
198 #define TI_RXSTATE_RESET 0x00000001
199 #define TI_RXSTATE_ENB 0x00000002
200 #define TI_RXSTATE_STOP 0x00000004
201
202 /*
203 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes
204 * split into 64 bit registers. Only the lower 32 bits of each mailbox
205 * are used.
206 */
207 #define TI_MB_HOSTINTR_HI 0x500
208 #define TI_MB_HOSTINTR_LO 0x504
209 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO
210 #define TI_MB_CMDPROD_IDX_HI 0x508
211 #define TI_MB_CMDPROD_IDX_LO 0x50C
212 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO
213 #define TI_MB_SENDPROD_IDX_HI 0x510
214 #define TI_MB_SENDPROD_IDX_LO 0x514
215 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO
216 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */
217 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */
218 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO
219 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */
220 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */
221 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO
222 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */
223 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */
224 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO
225 #define TI_MB_RSVD 0x530
226
227 /*
228 * Tigon 2 general communication registers. These are 64 and 32 bit
229 * registers which are only valid after the firmware has been
230 * loaded and started. They actually exist in NIC memory but are
231 * mapped into the host memory via the shared memory region.
232 *
233 * The NIC internally maps these registers starting at address 0,
234 * so to determine the NIC address of any of these registers, we
235 * subtract 0x600 (the address of the first register).
236 */
237
238 #define TI_GCR_BASE 0x600
239 #define TI_GCR_MACADDR 0x600
240 #define TI_GCR_PAR0 0x600
241 #define TI_GCR_PAR1 0x604
242 #define TI_GCR_GENINFO_HI 0x608
243 #define TI_GCR_GENINFO_LO 0x60C
244 #define TI_GCR_MCASTADDR 0x610 /* obsolete */
245 #define TI_GCR_MAR0 0x610 /* obsolete */
246 #define TI_GCR_MAR1 0x614 /* obsolete */
247 #define TI_GCR_OPMODE 0x618
248 #define TI_GCR_DMA_READCFG 0x61C
249 #define TI_GCR_DMA_WRITECFG 0x620
250 #define TI_GCR_TX_BUFFER_RATIO 0x624
251 #define TI_GCR_EVENTCONS_IDX 0x628
252 #define TI_GCR_CMDCONS_IDX 0x62C
253 #define TI_GCR_TUNEPARMS 0x630
254 #define TI_GCR_RX_COAL_TICKS 0x630
255 #define TI_GCR_TX_COAL_TICKS 0x634
256 #define TI_GCR_STAT_TICKS 0x638
257 #define TI_GCR_TX_MAX_COAL_BD 0x63C
258 #define TI_GCR_RX_MAX_COAL_BD 0x640
259 #define TI_GCR_NIC_TRACING 0x644
260 #define TI_GCR_GLINK 0x648
261 #define TI_GCR_LINK 0x64C
262 #define TI_GCR_NICTRACE_PTR 0x650
263 #define TI_GCR_NICTRACE_START 0x654
264 #define TI_GCR_NICTRACE_LEN 0x658
265 #define TI_GCR_IFINDEX 0x65C
266 #define TI_GCR_IFMTU 0x660
267 #define TI_GCR_MASK_INTRS 0x664
268 #define TI_GCR_GLINK_STAT 0x668
269 #define TI_GCR_LINK_STAT 0x66C
270 #define TI_GCR_RXRETURNCONS_IDX 0x680
271 #define TI_GCR_CMDRING 0x700
272
273 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE);
274
275 /*
276 * Local memory window. The local memory window is a 2K shared
277 * memory region which can be used to access the NIC's internal
278 * SRAM. The window can be mapped to a given 2K region using
279 * the TI_WINDOW_BASE register.
280 */
281 #define TI_WINDOW 0x800
282 #define TI_WINLEN 0x800
283
284 #define TI_TICKS_PER_SEC 1000000
285
286 /*
287 * Operation mode register.
288 */
289 #define TI_OPMODE_BYTESWAP_BD 0x00000002
290 #define TI_OPMODE_WORDSWAP_BD 0x00000004
291 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */
292 #define TI_OPMODE_BYTESWAP_DATA 0x00000010
293 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040
294 #define TI_OPMODE_SBUS 0x00000100
295 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200
296 #define TI_OPMODE_INCLUDE_CRC 0x00000400
297 #define TI_OPMODE_RX_BADFRAMES 0x00000800
298 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000
299 #define TI_OPMODE_NO_TX_INTRS 0x00002000
300 #define TI_OPMODE_NO_RX_INTRS 0x00004000
301 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */
302
303 /*
304 * DMA configuration thresholds.
305 */
306 #define TI_DMA_STATE_THRESH_16W 0x00000100
307 #define TI_DMA_STATE_THRESH_8W 0x00000080
308 #define TI_DMA_STATE_THRESH_4W 0x00000040
309 #define TI_DMA_STATE_THRESH_2W 0x00000020
310 #define TI_DMA_STATE_THRESH_1W 0x00000010
311
312 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008
313
314 /*
315 * Gigabit link status bits.
316 */
317 #define TI_GLNK_SENSE_NO_BEG 0x00002000
318 #define TI_GLNK_LOOPBACK 0x00004000
319 #define TI_GLNK_PREF 0x00008000
320 #define TI_GLNK_1000MB 0x00040000
321 #define TI_GLNK_FULL_DUPLEX 0x00080000
322 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
323 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000
324 #define TI_GLNK_AUTONEGENB 0x20000000
325 #define TI_GLNK_ENB 0x40000000
326
327 /*
328 * Link status bits.
329 */
330 #define TI_LNK_LOOPBACK 0x00004000
331 #define TI_LNK_PREF 0x00008000
332 #define TI_LNK_10MB 0x00010000
333 #define TI_LNK_100MB 0x00020000
334 #define TI_LNK_1000MB 0x00040000
335 #define TI_LNK_FULL_DUPLEX 0x00080000
336 #define TI_LNK_HALF_DUPLEX 0x00100000
337 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */
338 #define TI_LNK_RX_FLOWCTL_Y 0x00800000
339 #define TI_LNK_AUTONEGENB 0x20000000
340 #define TI_LNK_ENB 0x40000000
341
342 /*
343 * Ring size constants.
344 */
345 #define TI_EVENT_RING_CNT 256
346 #define TI_CMD_RING_CNT 64
347 #define TI_STD_RX_RING_CNT 512
348 #define TI_JUMBO_RX_RING_CNT 256
349 #define TI_MINI_RX_RING_CNT 1024
350 #define TI_RETURN_RING_CNT 2048
351
352 /*
353 * Possible TX ring sizes.
354 */
355 #define TI_TX_RING_CNT_128 128
356 #define TI_TX_RING_BASE_128 0x3800
357
358 #define TI_TX_RING_CNT_256 256
359 #define TI_TX_RING_BASE_256 0x3000
360
361 #define TI_TX_RING_CNT_512 512
362 #define TI_TX_RING_BASE_512 0x2000
363
364 #define TI_TX_RING_CNT TI_TX_RING_CNT_512
365 #define TI_TX_RING_BASE TI_TX_RING_BASE_512
366
367 /*
368 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1
369 * is limited to 2MB total, and in general I think most adapters have
370 * around 1MB. We use this value for zeroing the NIC's SRAM, so to
371 * be safe we use the largest possible value (zeroing memory that
372 * isn't there doesn't hurt anything).
373 */
374 #define TI_MEM_MAX 0x7FFFFF
375
376 /*
377 * Even on the alpha, pci addresses are 32-bit quantities
378 */
379
380 #ifdef __64_bit_pci_addressing__
381 typedef struct {
382 u_int64_t ti_addr;
383 } ti_hostaddr;
384 #define TI_HOSTADDR(x) x.ti_addr
385 #else
386 typedef struct {
387 u_int32_t ti_addr_hi;
388 u_int32_t ti_addr_lo;
389 } ti_hostaddr;
390 #define TI_HOSTADDR(x) x.ti_addr_lo
391 #endif
392
393 /*
394 * Ring control block structure. The rules for the max_len field
395 * are as follows:
396 *
397 * For the send ring, max_len indicates the number of entries in the
398 * ring (128, 256 or 512).
399 *
400 * For the standard receive ring, max_len indicates the threshold
401 * used to decide when a frame should be put in the jumbo receive ring
402 * instead of the standard one.
403 *
404 * For the mini ring, max_len indicates the size of the buffers in the
405 * ring. This is the value used to decide when a frame is small enough
406 * to be placed in the mini ring.
407 *
408 * For the return receive ring, max_len indicates the number of entries
409 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as
410 * 2048 for backwards compatibility). The value 1024 can only be used
411 * if the mini ring is disabled.
412 */
413 struct ti_rcb {
414 ti_hostaddr ti_hostaddr;
415 #if BYTE_ORDER == BIG_ENDIAN
416 u_int16_t ti_max_len;
417 u_int16_t ti_flags;
418 #else
419 u_int16_t ti_flags;
420 u_int16_t ti_max_len;
421 #endif
422 u_int32_t ti_unused;
423 };
424
425 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001
426 #define TI_RCB_FLAG_IP_CKSUM 0x00000002
427 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008
428 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010
429 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020
430 #define TI_RCB_FLAG_HOST_RING 0x00000040
431 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080
432 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100
433 #define TI_RCB_FLAG_RING_DISABLED 0x00000200
434
435 struct ti_producer {
436 u_int32_t ti_idx;
437 u_int32_t ti_unused;
438 };
439
440 /*
441 * Tigon statistics counters.
442 */
443 struct ti_stats {
444 /*
445 * MAC stats, taken from RFC 1643, ethernet-like MIB
446 */
447 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */
448 volatile u_int32_t dot3StatsFCSErrors; /* 1 */
449 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */
450 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */
451 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */
452 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */
453 volatile u_int32_t dot3StatsLateCollisions; /* 6 */
454 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */
455 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */
456 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */
457 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */
458 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */
459 /*
460 * interface stats, taken from RFC 1213, MIB-II, interfaces group
461 */
462 volatile u_int32_t ifIndex; /* 12 */
463 volatile u_int32_t ifType; /* 13 */
464 volatile u_int32_t ifMtu; /* 14 */
465 volatile u_int32_t ifSpeed; /* 15 */
466 volatile u_int32_t ifAdminStatus; /* 16 */
467 #define IF_ADMIN_STATUS_UP 1
468 #define IF_ADMIN_STATUS_DOWN 2
469 #define IF_ADMIN_STATUS_TESTING 3
470 volatile u_int32_t ifOperStatus; /* 17 */
471 #define IF_OPER_STATUS_UP 1
472 #define IF_OPER_STATUS_DOWN 2
473 #define IF_OPER_STATUS_TESTING 3
474 #define IF_OPER_STATUS_UNKNOWN 4
475 #define IF_OPER_STATUS_DORMANT 5
476 volatile u_int32_t ifLastChange; /* 18 */
477 volatile u_int32_t ifInDiscards; /* 19 */
478 volatile u_int32_t ifInErrors; /* 20 */
479 volatile u_int32_t ifInUnknownProtos; /* 21 */
480 volatile u_int32_t ifOutDiscards; /* 22 */
481 volatile u_int32_t ifOutErrors; /* 23 */
482 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */
483 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */
484 volatile u_int8_t ifDescr[32]; /* 27 - 34 */
485 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */
486 /*
487 * more interface stats, taken from RFC 1573, MIB-IIupdate,
488 * interfaces group
489 */
490 volatile u_int64_t ifHCInOctets; /* 36 - 37 */
491 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */
492 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */
493 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */
494 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */
495 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */
496 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */
497 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */
498 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */
499 volatile u_int32_t ifHighSpeed; /* 53 */
500 volatile u_int32_t ifPromiscuousMode; /* 54 */
501 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */
502 /*
503 * Host Commands
504 */
505 volatile u_int32_t nicCmdsHostState; /* 56 */
506 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */
507 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */
508 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */
509 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */
510 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */
511 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */
512 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */
513 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */
514 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */
515 volatile u_int32_t nicCmdsClearProfile; /* 66 */
516 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */
517 volatile u_int32_t nicCmdsClearStats; /* 68 */
518 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */
519 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */
520 volatile u_int32_t nicCmdsRefreshStats; /* 71 */
521 volatile u_int32_t nicCmdsUnknown; /* 72 */
522 /*
523 * NIC Events
524 */
525 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */
526 volatile u_int32_t nicEventsStatsUpdated; /* 74 */
527 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */
528 volatile u_int32_t nicEventsError; /* 76 */
529 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */
530 volatile u_int32_t nicEventsResetJumboRing; /* 78 */
531 /*
532 * Ring manipulation
533 */
534 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */
535 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */
536 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */
537 /*
538 * Interrupts
539 */
540 volatile u_int32_t nicInterrupts; /* 82 */
541 volatile u_int32_t nicAvoidedInterrupts; /* 83 */
542 /*
543 * BD Coalescing Thresholds
544 */
545 volatile u_int32_t nicEventThresholdHit; /* 84 */
546 volatile u_int32_t nicSendThresholdHit; /* 85 */
547 volatile u_int32_t nicRecvThresholdHit; /* 86 */
548 /*
549 * DMA Attentions
550 */
551 volatile u_int32_t nicDmaRdOverrun; /* 87 */
552 volatile u_int32_t nicDmaRdUnderrun; /* 88 */
553 volatile u_int32_t nicDmaWrOverrun; /* 89 */
554 volatile u_int32_t nicDmaWrUnderrun; /* 90 */
555 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */
556 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */
557 /*
558 * NIC Resources
559 */
560 volatile u_int32_t nicDmaWriteRingFull; /* 93 */
561 volatile u_int32_t nicDmaReadRingFull; /* 94 */
562 volatile u_int32_t nicEventRingFull; /* 95 */
563 volatile u_int32_t nicEventProducerRingFull; /* 96 */
564 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */
565 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */
566 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */
567 volatile u_int32_t nicNoMoreRxBDs; /* 100 */
568 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */
569 volatile u_int32_t nicSendBDs; /* current count 102 */
570 volatile u_int32_t nicRecvBDs; /* current count 103 */
571 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */
572 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */
573 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */
574 volatile u_int32_t nicTotalSendBDs; /* current count 107 */
575 volatile u_int32_t nicJumboSpillOver; /* 108 */
576 volatile u_int32_t nicSbusHangCleared; /* 109 */
577 volatile u_int32_t nicEnqEventDelayed; /* 110 */
578 /*
579 * Stats from MAC rx completion
580 */
581 volatile u_int32_t nicMacRxLateColls; /* 111 */
582 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */
583 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */
584 volatile u_int32_t nicMacRxMacAbort; /* 114 */
585 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */
586 /*
587 * Stats from the mac_stats area
588 */
589 volatile u_int32_t nicMacRxDropUla; /* 116 */
590 volatile u_int32_t nicMacRxDropMcast; /* 117 */
591 volatile u_int32_t nicMacRxFlowControl; /* 118 */
592 volatile u_int32_t nicMacRxDropSpace; /* 119 */
593 volatile u_int32_t nicMacRxColls; /* 120 */
594 /*
595 * MAC RX Attentions
596 */
597 volatile u_int32_t nicMacRxTotalAttns; /* 121 */
598 volatile u_int32_t nicMacRxLinkAttns; /* 122 */
599 volatile u_int32_t nicMacRxSyncAttns; /* 123 */
600 volatile u_int32_t nicMacRxConfigAttns; /* 124 */
601 volatile u_int32_t nicMacReset; /* 125 */
602 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */
603 volatile u_int32_t nicMacRxBufAttns; /* 127 */
604 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */
605 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */
606 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */
607 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */
608 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */
609 /*
610 * Stats from the mac_stats area
611 */
612 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */
613 /*
614 * MAC TX Attentions
615 */
616 volatile u_int32_t nicMacTxTotalAttns; /* 134 */
617 /*
618 * NIC Profile
619 */
620 volatile u_int32_t nicProfile[32]; /* 135 */
621 /*
622 * Pat to 1024 bytes.
623 */
624 u_int32_t pad[75];
625 };
626 /*
627 * Tigon general information block. This resides in host memory
628 * and contains the status counters, ring control blocks and
629 * producer pointers.
630 */
631
632 struct ti_gib {
633 struct ti_stats ti_stats;
634 struct ti_rcb ti_ev_rcb;
635 struct ti_rcb ti_cmd_rcb;
636 struct ti_rcb ti_tx_rcb;
637 struct ti_rcb ti_std_rx_rcb;
638 struct ti_rcb ti_jumbo_rx_rcb;
639 struct ti_rcb ti_mini_rx_rcb;
640 struct ti_rcb ti_return_rcb;
641 ti_hostaddr ti_ev_prodidx_ptr;
642 ti_hostaddr ti_return_prodidx_ptr;
643 ti_hostaddr ti_tx_considx_ptr;
644 ti_hostaddr ti_refresh_stats_ptr;
645 };
646
647 /*
648 * Buffer descriptor structures. There are basically three types
649 * of structures: normal receive descriptors, extended receive
650 * descriptors and transmit descriptors. The extended receive
651 * descriptors are optionally used only for the jumbo receive ring.
652 */
653
654 struct ti_rx_desc {
655 ti_hostaddr ti_addr;
656 #if BYTE_ORDER == BIG_ENDIAN
657 u_int16_t ti_idx;
658 u_int16_t ti_len;
659 #else
660 u_int16_t ti_len;
661 u_int16_t ti_idx;
662 #endif
663 #if BYTE_ORDER == BIG_ENDIAN
664 u_int16_t ti_type;
665 u_int16_t ti_flags;
666 #else
667 u_int16_t ti_flags;
668 u_int16_t ti_type;
669 #endif
670 #if BYTE_ORDER == BIG_ENDIAN
671 u_int16_t ti_ip_cksum;
672 u_int16_t ti_tcp_udp_cksum;
673 #else
674 u_int16_t ti_tcp_udp_cksum;
675 u_int16_t ti_ip_cksum;
676 #endif
677 #if BYTE_ORDER == BIG_ENDIAN
678 u_int16_t ti_error_flags;
679 u_int16_t ti_vlan_tag;
680 #else
681 u_int16_t ti_vlan_tag;
682 u_int16_t ti_error_flags;
683 #endif
684 u_int32_t ti_rsvd;
685 u_int32_t ti_opaque;
686 };
687
688 struct ti_rx_desc_ext {
689 ti_hostaddr ti_addr1;
690 ti_hostaddr ti_addr2;
691 ti_hostaddr ti_addr3;
692 #if BYTE_ORDER == BIG_ENDIAN
693 u_int16_t ti_len1;
694 u_int16_t ti_len2;
695 #else
696 u_int16_t ti_len2;
697 u_int16_t ti_len1;
698 #endif
699 #if BYTE_ORDER == BIG_ENDIAN
700 u_int16_t ti_len3;
701 u_int16_t ti_rsvd0;
702 #else
703 u_int16_t ti_rsvd0;
704 u_int16_t ti_len3;
705 #endif
706 ti_hostaddr ti_addr0;
707 #if BYTE_ORDER == BIG_ENDIAN
708 u_int16_t ti_idx;
709 u_int16_t ti_len0;
710 #else
711 u_int16_t ti_len0;
712 u_int16_t ti_idx;
713 #endif
714 #if BYTE_ORDER == BIG_ENDIAN
715 u_int16_t ti_type;
716 u_int16_t ti_flags;
717 #else
718 u_int16_t ti_flags;
719 u_int16_t ti_type;
720 #endif
721 #if BYTE_ORDER == BIG_ENDIAN
722 u_int16_t ti_ip_cksum;
723 u_int16_t ti_tcp_udp_cksum;
724 #else
725 u_int16_t ti_tcp_udp_cksum;
726 u_int16_t ti_ip_cksum;
727 #endif
728 #if BYTE_ORDER == BIG_ENDIAN
729 u_int16_t ti_error_flags;
730 u_int16_t ti_vlan_tag;
731 #else
732 u_int16_t ti_vlan_tag;
733 u_int16_t ti_error_flags;
734 #endif
735 u_int32_t ti_rsvd1;
736 u_int32_t ti_opaque;
737 };
738
739 /*
740 * Transmit descriptors are, mercifully, very small.
741 */
742 struct ti_tx_desc {
743 ti_hostaddr ti_addr;
744 #if BYTE_ORDER == BIG_ENDIAN
745 u_int16_t ti_len;
746 u_int16_t ti_flags;
747 #else
748 u_int16_t ti_flags;
749 u_int16_t ti_len;
750 #endif
751 #if BYTE_ORDER == BIG_ENDIAN
752 u_int16_t ti_rsvd;
753 u_int16_t ti_vlan_tag;
754 #else
755 u_int16_t ti_vlan_tag;
756 u_int16_t ti_rsvd;
757 #endif
758 };
759
760 /*
761 * NOTE! On the Alpha, we have an alignment constraint.
762 * The first thing in the packet is a 14-byte Ethernet header.
763 * This means that the packet is misaligned. To compensate,
764 * we actually offset the data 2 bytes into the cluster. This
765 * alignes the packet after the Ethernet header at a 32-bit
766 * boundary.
767 */
768
769 #define ETHER_ALIGN 2
770
771 #define TI_PAGE_SIZE PAGE_SIZE
772
773 /*
774 * Buffer descriptor error flags.
775 */
776 #define TI_BDERR_CRC 0x0001
777 #define TI_BDERR_COLLDETECT 0x0002
778 #define TI_BDERR_LINKLOST 0x0004
779 #define TI_BDERR_DECODE 0x0008
780 #define TI_BDERR_ODD_NIBBLES 0x0010
781 #define TI_BDERR_MAC_ABRT 0x0020
782 #define TI_BDERR_RUNT 0x0040
783 #define TI_BDERR_TRUNC 0x0080
784 #define TI_BDERR_GIANT 0x0100
785
786 /*
787 * Buffer descriptor flags.
788 */
789 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001
790 #define TI_BDFLAG_IP_CKSUM 0x0002
791 #define TI_BDFLAG_END 0x0004
792 #define TI_BDFLAG_MORE 0x0008
793 #define TI_BDFLAG_JUMBO_RING 0x0010
794 #define TI_BDFLAG_UCAST_PKT 0x0020
795 #define TI_BDFLAG_MCAST_PKT 0x0040
796 #define TI_BDFLAG_BCAST_PKT 0x0060
797 #define TI_BDFLAG_IP_FRAG 0x0080
798 #define TI_BDFLAG_IP_FRAG_END 0x0100
799 #define TI_BDFLAG_VLAN_TAG 0x0200
800 #define TI_BDFLAG_ERROR 0x0400
801 #define TI_BDFLAG_COAL_NOW 0x0800
802 #define TI_BDFLAG_MINI_RING 0x1000
803
804 /*
805 * Descriptor type flags. I think these only have meaning for
806 * the Tigon 1. I had to extract them from the sample driver source
807 * since they aren't in the manual.
808 */
809 #define TI_BDTYPE_TYPE_NULL 0x0000
810 #define TI_BDTYPE_SEND_BD 0x0001
811 #define TI_BDTYPE_RECV_BD 0x0002
812 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003
813 #define TI_BDTYPE_RECV_BD_LAST 0x0004
814 #define TI_BDTYPE_SEND_DATA 0x0005
815 #define TI_BDTYPE_SEND_DATA_LAST 0x0006
816 #define TI_BDTYPE_RECV_DATA 0x0007
817 #define TI_BDTYPE_RECV_DATA_LAST 0x000b
818 #define TI_BDTYPE_EVENT_RUPT 0x000c
819 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d
820 #define TI_BDTYPE_ODD_START 0x000e
821 #define TI_BDTYPE_UPDATE_STATS 0x000f
822 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010
823 #define TI_BDTYPE_EVENT_PROD 0x0011
824 #define TI_BDTYPE_TX_CONS 0x0012
825 #define TI_BDTYPE_RX_PROD 0x0013
826 #define TI_BDTYPE_REFRESH_STATS 0x0014
827 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015
828 #define TI_BDTYPE_SEND_DATA_COAL 0x0016
829 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017
830 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018
831 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019
832
833 /*
834 * Tigon command structure.
835 */
836 struct ti_cmd_desc {
837 u_int32_t ti_cmdx;
838 };
839
840 #define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff)
841 #define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff)
842 #define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff)
843
844 #define TI_CMD_HOST_STATE 0x01
845 #define TI_CMD_CODE_STACK_UP 0x01
846 #define TI_CMD_CODE_STACK_DOWN 0x02
847
848 /*
849 * This command enables software address filtering. It's a workaround
850 * for a bug in the Tigon 1 and not implemented for the Tigon 2.
851 */
852 #define TI_CMD_FDR_FILTERING 0x02
853 #define TI_CMD_CODE_FILT_ENB 0x01
854 #define TI_CMD_CODE_FILT_DIS 0x02
855
856 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */
857 #define TI_CMD_UPDATE_GENCOM 0x04
858 #define TI_CMD_RESET_JUMBO_RING 0x05
859 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06
860 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */
861 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */
862
863 #define TI_CMD_SET_PROMISC_MODE 0x0A
864 #define TI_CMD_CODE_PROMISC_ENB 0x01
865 #define TI_CMD_CODE_PROMISC_DIS 0x02
866
867 #define TI_CMD_LINK_NEGOTIATION 0x0B
868 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00
869 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01
870 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02
871
872 #define TI_CMD_SET_MAC_ADDR 0x0C
873 #define TI_CMD_CLR_PROFILE 0x0D
874
875 #define TI_CMD_SET_ALLMULTI 0x0E
876 #define TI_CMD_CODE_ALLMULTI_ENB 0x01
877 #define TI_CMD_CODE_ALLMULTI_DIS 0x02
878
879 #define TI_CMD_CLR_STATS 0x0F
880 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */
881 #define TI_CMD_RFRSH_STATS 0x11
882
883 #define TI_CMD_EXT_ADD_MCAST 0x12
884 #define TI_CMD_EXT_DEL_MCAST 0x13
885
886 /*
887 * Utility macros to make issuing commands a little simpler. Assumes
888 * that 'sc' and 'cmd' are in local scope.
889 */
890 #define TI_DO_CMD(x, y, z) do { \
891 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \
892 ti_cmd(sc, &cmd); \
893 } while(0)
894
895 #define TI_DO_CMD_EXT(x, y, z, v, w) do { \
896 cmd.ti_cmdx = (((x) << 24) | ((y) << 12) | ((z))); \
897 ti_cmd_ext(sc, &cmd, (v), (w)); \
898 } while(0)
899
900 /*
901 * Other utility macros.
902 */
903 #define TI_INC(x, y) do { (x) = ((x) + 1) % (y); } while(0)
904
905 #define TI_UPDATE_JUMBOPROD(x, y) do { \
906 if ((x)->ti_hwrev == TI_HWREV_TIGON) \
907 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \
908 else \
909 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \
910 } while(0)
911
912 #define TI_UPDATE_MINIPROD(x, y) \
913 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y)
914
915 #define TI_UPDATE_STDPROD(x, y) do { \
916 if ((x)->ti_hwrev == TI_HWREV_TIGON) \
917 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \
918 else \
919 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \
920 } while(0)
921
922
923 /*
924 * Tigon event structure.
925 */
926 struct ti_event_desc {
927 u_int32_t ti_eventx;
928 u_int32_t ti_rsvd;
929 };
930
931 #define TI_EVENT_EVENT(e) (((((e)->ti_eventx)) >> 24) & 0xff)
932 #define TI_EVENT_CODE(e) (((((e)->ti_eventx)) >> 12) & 0xfff)
933 #define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff)
934
935 /*
936 * Tigon events.
937 */
938 #define TI_EV_FIRMWARE_UP 0x01
939 #define TI_EV_STATS_UPDATED 0x04
940
941 #define TI_EV_LINKSTAT_CHANGED 0x06
942 #define TI_EV_CODE_GIG_LINK_UP 0x01
943 #define TI_EV_CODE_LINK_DOWN 0x02
944 #define TI_EV_CODE_LINK_UP 0x03
945
946 #define TI_EV_ERROR 0x07
947 #define TI_EV_CODE_ERR_INVAL_CMD 0x01
948 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02
949 #define TI_EV_CODE_ERR_BADCFG 0x03
950
951 #define TI_EV_MCAST_UPDATED 0x08
952 #define TI_EV_CODE_MCAST_ADD 0x01
953 #define TI_EV_CODE_MCAST_DEL 0x02
954
955 #define TI_EV_RESET_JUMBO_RING 0x09
956 /*
957 * Register access macros. The Tigon always uses memory mapped register
958 * accesses and all registers must be accessed with 32 bit operations.
959 * The Tigon can operate in big-endian mode, so we always write to the
960 * registers in native byte order. We assume that all big-endian hosts
961 * with a PCI bus have __BUS_SPACE_HAS_STREAM_METHODS defined.
962 */
963
964 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
965 #define CSR_WRITE_4(sc, reg, val) \
966 bus_space_write_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)
967
968 #define CSR_READ_4(sc, reg) \
969 bus_space_read_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg)
970 #else
971 #define CSR_WRITE_4(sc, reg, val) \
972 bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)
973
974 #define CSR_READ_4(sc, reg) \
975 bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, reg)
976 #endif
977
978 #define TI_SETBIT(sc, reg, x) \
979 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
980 #define TI_CLRBIT(sc, reg, x) \
981 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
982
983 /*
984 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
985 * values are tuneable. They control the actual amount of buffers
986 * allocated for the standard, mini and jumbo receive rings.
987 */
988
989 #ifndef TI_SSLOTS
990 #define TI_SSLOTS 256
991 #endif
992 #ifndef TI_MSLOTS
993 #define TI_MSLOTS 256
994 #endif
995 #ifndef TI_JSLOTS
996 #define TI_JSLOTS 384
997 #endif
998 #define TI_RSLOTS 128
999
1000 #define TI_JRAWLEN (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN + sizeof(u_int64_t))
1001 #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \
1002 (TI_JRAWLEN % sizeof(u_int64_t))))
1003 #define TI_JPAGESZ PAGE_SIZE
1004 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ)
1005 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID)
1006
1007 /*
1008 * Ring structures. Most of these reside in host memory and we tell
1009 * the NIC where they are via the ring control blocks. The exceptions
1010 * are the tx and command rings, which live in NIC memory and which
1011 * we access via the shared memory window.
1012 */
1013 struct ti_ring_data {
1014 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT];
1015 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT];
1016 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT];
1017 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT];
1018 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT];
1019 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT];
1020 /*
1021 * Make sure producer structures are aligned on 32-byte cache
1022 * line boundaries.
1023 */
1024 struct ti_producer ti_ev_prodidx_r;
1025 u_int32_t ti_pad0[6];
1026 struct ti_producer ti_return_prodidx_r;
1027 u_int32_t ti_pad1[6];
1028 struct ti_producer ti_tx_considx_r;
1029 u_int32_t ti_pad2[6];
1030 struct ti_gib ti_info;
1031 };
1032
1033 #define TI_CDOFF(x) offsetof(struct ti_ring_data, x)
1034 #define TI_CDRXSTDOFF(x) TI_CDOFF(ti_rx_std_ring[(x)])
1035 #define TI_CDRXJUMBOOFF(x) TI_CDOFF(ti_rx_jumbo_ring[(x)])
1036 #define TI_CDRXMINIOFF(x) TI_CDOFF(ti_rx_mini_ring[(x)])
1037 #define TI_CDRXRTNOFF(x) TI_CDOFF(ti_rx_return_ring[(x)])
1038 #define TI_CDEVENTOFF(x) TI_CDOFF(ti_event_ring[(x)])
1039 #define TI_CDTXOFF(x) TI_CDOFF(ti_tx_ring[(x)])
1040 #define TI_CDEVPRODOFF TI_CDOFF(ti_ev_prodidx_r)
1041 #define TI_CDRTNPRODOFF TI_CDOFF(ti_return_prodidx_r)
1042 #define TI_CDTXCONSOFF TI_CDOFF(ti_tx_considx_r)
1043 #define TI_CDGIBOFF TI_CDOFF(ti_info)
1044 #define TI_CDSTATSOFF TI_CDOFF(ti_info.ti_stats)
1045
1046 /*
1047 * Mbuf pointers. We need these to keep track of the virtual addresses
1048 * of our mbuf chains since we can only convert from physical to virtual,
1049 * not the other way around.
1050 */
1051 struct ti_chain_data {
1052 struct mbuf *ti_tx_chain[TI_TX_RING_CNT];
1053 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT];
1054 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT];
1055 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT];
1056 /* Stick the jumbo mem management stuff here too. */
1057 void * ti_jslots[TI_JSLOTS];
1058 void *ti_jumbo_buf;
1059 };
1060
1061 struct ti_type {
1062 u_int16_t ti_vid;
1063 u_int16_t ti_did;
1064 const char *ti_name;
1065 };
1066
1067 #define TI_HWREV_TIGON 0x01
1068 #define TI_HWREV_TIGON_II 0x02
1069 #define TI_TIMEOUT 1000
1070 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */
1071
1072 struct ti_mc_entry {
1073 struct ether_addr mc_addr;
1074 SIMPLEQ_ENTRY(ti_mc_entry) mc_entries;
1075 };
1076
1077 struct ti_jpool_entry {
1078 int slot;
1079 SIMPLEQ_ENTRY(ti_jpool_entry) jpool_entries;
1080 };
1081
1082 struct txdmamap_pool_entry {
1083 bus_dmamap_t dmamap;
1084 SIMPLEQ_ENTRY(txdmamap_pool_entry) link;
1085 };
1086
1087 struct ti_softc {
1088 struct device sc_dev;
1089 struct ethercom ethercom; /* interface info */
1090 bus_space_handle_t ti_bhandle;
1091 char *ti_vhandle;
1092 bus_space_tag_t ti_btag;
1093 void *ti_intrhand;
1094
1095 struct ifmedia ifmedia; /* media info */
1096
1097 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */
1098 u_int8_t ti_copper; /* 1000baseT card */
1099 u_int8_t ti_linkstat; /* Link state */
1100 struct ti_ring_data *ti_rdata; /* rings */
1101 #define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r
1102 #define ti_return_prodidx ti_rdata->ti_return_prodidx_r
1103 #define ti_tx_considx ti_rdata->ti_tx_considx_r
1104
1105 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */
1106
1107 struct ti_chain_data ti_cdata; /* mbufs */
1108
1109 /*
1110 * Function pointers to deal with Tigon 1 vs. Tigon 2 differences.
1111 */
1112 int (*sc_tx_encap)(struct ti_softc *,
1113 struct mbuf *, uint32_t *);
1114 void (*sc_tx_eof)(struct ti_softc *);
1115
1116 u_int16_t ti_tx_saved_considx;
1117 u_int16_t ti_rx_saved_considx;
1118 u_int16_t ti_ev_saved_considx;
1119 u_int16_t ti_cmd_saved_prodidx;
1120 u_int16_t ti_std; /* current std ring head */
1121 u_int16_t ti_mini; /* current mini ring head */
1122 u_int16_t ti_jumbo; /* current jumo ring head */
1123 SIMPLEQ_HEAD(, ti_mc_entry) ti_mc_listhead;
1124 SIMPLEQ_HEAD(, ti_jpool_entry) ti_jfree_listhead;
1125 SIMPLEQ_HEAD(, ti_jpool_entry) ti_jinuse_listhead;
1126 u_int32_t ti_stat_ticks;
1127 u_int32_t ti_rx_coal_ticks;
1128 u_int32_t ti_tx_coal_ticks;
1129 u_int32_t ti_rx_max_coal_bds;
1130 u_int32_t ti_tx_max_coal_bds;
1131 u_int32_t ti_tx_buf_ratio;
1132 int ti_if_flags;
1133 int ti_txcnt;
1134 void *sc_ih;
1135 bus_dma_tag_t sc_dmat;
1136 bus_dmamap_t info_dmamap; /* holds ti_rdata */
1137 u_int32_t info_dmaaddr; /* XXX 64-bit PCI addresses? */
1138 bus_dmamap_t jumbo_dmamap;
1139 u_int32_t jumbo_dmaaddr; /* XXX 64-bit PCI addresses? */
1140 bus_dmamap_t mini_dmamap[TI_MINI_RX_RING_CNT];
1141 bus_dmamap_t std_dmamap[TI_STD_RX_RING_CNT];
1142 SIMPLEQ_HEAD(, txdmamap_pool_entry) txdma_list;
1143 struct txdmamap_pool_entry *txdma[TI_TX_RING_CNT];
1144 };
1145
1146 #define TI_CDRXSTDADDR(sc, x) ((sc)->info_dmaaddr + TI_CDRXSTDOFF((x)))
1147 #define TI_CDRXJUMBOADDR(sc, x) ((sc)->info_dmaaddr + TI_CDRXJUMBOOFF((x)))
1148 #define TI_CDRXMINIADDR(sc, x) ((sc)->info_dmaaddr + TI_CDRXMINIOFF((x)))
1149 #define TI_CDRXRTNADDR(sc, x) ((sc)->info_dmaaddr + TI_CDRXRTNOFF((x)))
1150 #define TI_CDEVENTADDR(sc, x) ((sc)->info_dmaaddr + TI_CDEVENTOFF((x)))
1151 #define TI_CDTXADDR(sc, x) ((sc)->info_dmaaddr + TI_CDTXOFF((x)))
1152 #define TI_CDEVPRODADDR(sc) ((sc)->info_dmaaddr + TI_CDEVPRODOFF)
1153 #define TI_CDRTNPRODADDR(sc) ((sc)->info_dmaaddr + TI_CDRTNPRODOFF)
1154 #define TI_CDTXCONSADDR(sc) ((sc)->info_dmaaddr + TI_CDTXCONSOFF)
1155 #define TI_CDGIBADDR(sc) ((sc)->info_dmaaddr + TI_CDGIBOFF)
1156 #define TI_CDSTATSADDR(sc) ((sc)->info_dmaaddr + TI_CDSTATSOFF)
1157
1158 #define TI_CDRXSTDSYNC(sc, x, ops) \
1159 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1160 TI_CDRXSTDOFF((x)), sizeof(struct ti_rx_desc), (ops))
1161
1162 #define TI_CDRXJUMBOSYNC(sc, x, ops) \
1163 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1164 TI_CDRXJUMBOOFF((x)), sizeof(struct ti_rx_desc), (ops))
1165
1166 #define TI_CDRXMINISYNC(sc, x, ops) \
1167 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1168 TI_CDRXMINIOFF((x)), sizeof(struct ti_rx_desc), (ops))
1169
1170 #define TI_CDRXRTNSYNC(sc, x, ops) \
1171 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1172 TI_CDRXRTNOFF((x)), sizeof(struct ti_rx_desc), (ops))
1173
1174 #define TI_CDEVENTSYNC(sc, x, ops) \
1175 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1176 TI_CDEVENTOFF((x)), sizeof(struct ti_event_desc), (ops))
1177
1178 #define TI_CDTXSYNC(sc, x, n, ops) \
1179 do { \
1180 int __x, __n; \
1181 \
1182 __x = (x); \
1183 __n = (n); \
1184 \
1185 /* If it will wrap around, sync to the end of the ring. */ \
1186 if ((__x + __n) > TI_TX_RING_CNT) { \
1187 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1188 TI_CDTXOFF(__x), sizeof(struct ti_tx_desc) * \
1189 (TI_TX_RING_CNT - __x), (ops)); \
1190 __n -= (TI_TX_RING_CNT - __x); \
1191 __x = 0; \
1192 } \
1193 \
1194 /* Now sync whatever is left. */ \
1195 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1196 TI_CDTXOFF(__x), sizeof(struct ti_tx_desc) * (__n), (ops)); \
1197 } while (/*CONSTCOND*/0)
1198
1199 #define TI_CEVPRODSYNC(sc, ops) \
1200 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1201 TI_CDEVPRODOFF, sizeof(struct ti_producer), (ops))
1202
1203 #define TI_CDRTNPRODSYNC(sc, ops) \
1204 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1205 TI_CDRTNPRODOFF, sizeof(struct ti_producer), (ops))
1206
1207 #define TI_CDTXCONSSYNC(sc, ops) \
1208 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1209 TI_CDTXCONSOFF, sizeof(struct ti_producer), (ops))
1210
1211 #define TI_CDGIBSYNC(sc, ops) \
1212 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1213 TI_CDGIBOFF, sizeof(struct ti_gib), (ops))
1214
1215 #define TI_CDSTATSSYNC(sc, ops) \
1216 bus_dmamap_sync((sc)->sc_dmat, (sc)->info_dmamap, \
1217 TI_CDSTATSOFF, sizeof(struct ti_stats), (ops))
1218
1219 /*
1220 * Microchip Technology 24Cxx EEPROM control bytes
1221 */
1222 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
1223 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
1224
1225 /*
1226 * Note that EEPROM_START leaves transmission enabled.
1227 */
1228 #define EEPROM_START() do { \
1229 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\
1230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \
1231 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\
1232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\
1233 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \
1234 } while(0)
1235
1236 /*
1237 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so
1238 * that no further data can be written to the EEPROM I/O pin.
1239 */
1240 #define EEPROM_STOP() do { \
1241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \
1242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \
1243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \
1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \
1245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \
1246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \
1247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ \
1248 } while(0)
NetBSD on the FriendlyARM MINI2440