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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_tl.c
bloba19a1c6487bda719e0c0249fcd1df8246129ce4d
1 /* $NetBSD: if_tl.c,v 1.92 2009/09/05 13:50:15 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * Texas Instruments ThunderLAN ethernet controller
29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A)
30 * available from www.ti.com
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.92 2009/09/05 13:50:15 tsutsui Exp $");
35
36 #undef TLDEBUG
37 #define TL_PRIV_STATS
38 #undef TLDEBUG_RX
39 #undef TLDEBUG_TX
40 #undef TLDEBUG_ADDR
41
42 #include "opt_inet.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/mbuf.h>
47 #include <sys/protosw.h>
48 #include <sys/socket.h>
49 #include <sys/ioctl.h>
50 #include <sys/errno.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */
54 #include <sys/device.h>
55
56 #include <net/if.h>
57 #if defined(SIOCSIFMEDIA)
58 #include <net/if_media.h>
59 #endif
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/route.h>
63 #include <net/netisr.h>
64
65 #include "bpfilter.h"
66 #if NBPFILTER > 0
67 #include <net/bpf.h>
68 #include <net/bpfdesc.h>
69 #endif
70
71 #include "rnd.h"
72 #if NRND > 0
73 #include <sys/rnd.h>
74 #endif
75
76 #ifdef INET
77 #include <netinet/in.h>
78 #include <netinet/in_systm.h>
79 #include <netinet/in_var.h>
80 #include <netinet/ip.h>
81 #endif
82
83
84 #if defined(__NetBSD__)
85 #include <net/if_ether.h>
86 #include <uvm/uvm_extern.h>
87 #if defined(INET)
88 #include <netinet/if_inarp.h>
89 #endif
90
91 #include <sys/bus.h>
92 #include <sys/intr.h>
93
94 #include <dev/pci/pcireg.h>
95 #include <dev/pci/pcivar.h>
96 #include <dev/pci/pcidevs.h>
97
98 #include <dev/i2c/i2cvar.h>
99 #include <dev/i2c/i2c_bitbang.h>
100 #include <dev/i2c/at24cxxvar.h>
101
102 #include <dev/mii/mii.h>
103 #include <dev/mii/miivar.h>
104
105 #include <dev/mii/tlphyvar.h>
106
107 #include <dev/pci/if_tlregs.h>
108 #include <dev/pci/if_tlvar.h>
109 #endif /* __NetBSD__ */
110
111 /* number of transmit/receive buffers */
112 #ifndef TL_NBUF
113 #define TL_NBUF 32
114 #endif
115
116 static int tl_pci_match(device_t, cfdata_t, void *);
117 static void tl_pci_attach(device_t, device_t, void *);
118 static int tl_intr(void *);
119
120 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
121 static int tl_mediachange(struct ifnet *);
122 static void tl_ifwatchdog(struct ifnet *);
123 static bool tl_shutdown(device_t, int);
124
125 static void tl_ifstart(struct ifnet *);
126 static void tl_reset(tl_softc_t *);
127 static int tl_init(struct ifnet *);
128 static void tl_stop(struct ifnet *, int);
129 static void tl_restart(void *);
130 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *);
131 static void tl_read_stats(tl_softc_t *);
132 static void tl_ticks(void *);
133 static int tl_multicast_hash(uint8_t *);
134 static void tl_addr_filter(tl_softc_t *);
135
136 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t);
137 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t);
138 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t);
139 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t);
140
141 void tl_mii_sync(struct tl_softc *);
142 void tl_mii_sendbits(struct tl_softc *, uint32_t, int);
143
144
145 #if defined(TLDEBUG_RX)
146 static void ether_printheader(struct ether_header *);
147 #endif
148
149 int tl_mii_read(device_t, int, int);
150 void tl_mii_write(device_t, int, int, int);
151
152 void tl_statchg(device_t);
153
154 /* I2C glue */
155 static int tl_i2c_acquire_bus(void *, int);
156 static void tl_i2c_release_bus(void *, int);
157 static int tl_i2c_send_start(void *, int);
158 static int tl_i2c_send_stop(void *, int);
159 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int);
160 static int tl_i2c_read_byte(void *, uint8_t *, int);
161 static int tl_i2c_write_byte(void *, uint8_t, int);
162
163 /* I2C bit-bang glue */
164 static void tl_i2cbb_set_bits(void *, uint32_t);
165 static void tl_i2cbb_set_dir(void *, uint32_t);
166 static uint32_t tl_i2cbb_read(void *);
167 static const struct i2c_bitbang_ops tl_i2cbb_ops = {
168 tl_i2cbb_set_bits,
169 tl_i2cbb_set_dir,
170 tl_i2cbb_read,
171 {
172 TL_NETSIO_EDATA, /* SDA */
173 TL_NETSIO_ECLOCK, /* SCL */
174 TL_NETSIO_ETXEN, /* SDA is output */
175 0, /* SDA is input */
176 }
177 };
178
179 static inline void netsio_clr(tl_softc_t *, uint8_t);
180 static inline void netsio_set(tl_softc_t *, uint8_t);
181 static inline uint8_t netsio_read(tl_softc_t *, uint8_t);
182
183 static inline void
184 netsio_clr(tl_softc_t *sc, uint8_t bits)
185 {
186
187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits));
189 }
190
191 static inline void
192 netsio_set(tl_softc_t *sc, uint8_t bits)
193 {
194
195 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
196 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits);
197 }
198
199 static inline uint8_t
200 netsio_read(tl_softc_t *sc, uint8_t bits)
201 {
202
203 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits;
204 }
205
206 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t),
207 tl_pci_match, tl_pci_attach, NULL, NULL);
208
209 static const struct tl_product_desc tl_compaq_products[] = {
210 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T,
211 "Compaq Netelligent 10/100 TX" },
212 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T,
213 "Integrated Compaq Netelligent 10/100 TX" },
214 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5,
215 "Compaq Netelligent 10 T" },
216 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2,
217 "Compaq Netelligent 10 T/2 UTP/Coax" },
218 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2,
219 "Compaq Integrated NetFlex 3/P" },
220 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T,
221 "Compaq ProLiant Integrated Netelligent 10/100 TX" },
222 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
223 "Compaq Dual Port Netelligent 10/100 TX" },
224 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
225 "Compaq Deskpro 4000 5233MMX" },
226 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2,
227 "Compaq NetFlex 3/P w/ BNC" },
228 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5,
229 "Compaq NetFlex 3/P" },
230 { 0, 0, NULL },
231 };
232
233 static const struct tl_product_desc tl_ti_products[] = {
234 /*
235 * Built-in Ethernet on the TI TravelMate 5000
236 * docking station; better product description?
237 */
238 { PCI_PRODUCT_TI_TLAN, 0,
239 "Texas Instruments ThunderLAN" },
240 { 0, 0, NULL },
241 };
242
243 struct tl_vendor_desc {
244 uint32_t tv_vendor;
245 const struct tl_product_desc *tv_products;
246 };
247
248 const struct tl_vendor_desc tl_vendors[] = {
249 { PCI_VENDOR_COMPAQ, tl_compaq_products },
250 { PCI_VENDOR_TI, tl_ti_products },
251 { 0, NULL },
252 };
253
254 static const struct tl_product_desc *tl_lookup_product(uint32_t);
255
256 static const struct tl_product_desc *
257 tl_lookup_product(uint32_t id)
258 {
259 const struct tl_product_desc *tp;
260 const struct tl_vendor_desc *tv;
261
262 for (tv = tl_vendors; tv->tv_products != NULL; tv++)
263 if (PCI_VENDOR(id) == tv->tv_vendor)
264 break;
265
266 if ((tp = tv->tv_products) == NULL)
267 return NULL;
268
269 for (; tp->tp_desc != NULL; tp++)
270 if (PCI_PRODUCT(id) == tp->tp_product)
271 break;
272
273 if (tp->tp_desc == NULL)
274 return NULL;
275
276 return tp;
277 }
278
279 static int
280 tl_pci_match(device_t parent, cfdata_t cf, void *aux)
281 {
282 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
283
284 if (tl_lookup_product(pa->pa_id) != NULL)
285 return 1;
286
287 return 0;
288 }
289
290 static void
291 tl_pci_attach(device_t parent, device_t self, void *aux)
292 {
293 tl_softc_t *sc = device_private(self);
294 struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
295 const struct tl_product_desc *tp;
296 struct ifnet * const ifp = &sc->tl_if;
297 bus_space_tag_t iot, memt;
298 bus_space_handle_t ioh, memh;
299 pci_intr_handle_t intrhandle;
300 const char *intrstr;
301 int ioh_valid, memh_valid;
302 int reg_io, reg_mem;
303 pcireg_t reg10, reg14;
304 pcireg_t csr;
305
306 sc->sc_dev = self;
307 aprint_normal("\n");
308
309 callout_init(&sc->tl_tick_ch, 0);
310 callout_init(&sc->tl_restart_ch, 0);
311
312 tp = tl_lookup_product(pa->pa_id);
313 if (tp == NULL)
314 panic("%s: impossible", __func__);
315 sc->tl_product = tp;
316
317 /*
318 * Map the card space. First we have to find the I/O and MEM
319 * registers. I/O is supposed to be at 0x10, MEM at 0x14,
320 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed.
321 * The ThunderLAN manual is not consistent about this either (there
322 * are both cases in code examples).
323 */
324 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10);
325 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14);
326 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO)
327 reg_io = 0x10;
328 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO)
329 reg_io = 0x14;
330 else
331 reg_io = 0;
332 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM)
333 reg_mem = 0x10;
334 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM)
335 reg_mem = 0x14;
336 else
337 reg_mem = 0;
338
339 if (reg_io != 0)
340 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO,
341 0, &iot, &ioh, NULL, NULL) == 0);
342 else
343 ioh_valid = 0;
344 if (reg_mem != 0)
345 memh_valid = (pci_mapreg_map(pa, PCI_CBMA,
346 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
347 0, &memt, &memh, NULL, NULL) == 0);
348 else
349 memh_valid = 0;
350
351 if (ioh_valid) {
352 sc->tl_bustag = iot;
353 sc->tl_bushandle = ioh;
354 } else if (memh_valid) {
355 sc->tl_bustag = memt;
356 sc->tl_bushandle = memh;
357 } else {
358 aprint_error_dev(self, "unable to map device registers\n");
359 return;
360 }
361 sc->tl_dmatag = pa->pa_dmat;
362
363 /* Enable the device. */
364 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
365 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
366 csr | PCI_COMMAND_MASTER_ENABLE);
367
368 aprint_normal_dev(self, "%s\n", tp->tp_desc);
369
370 tl_reset(sc);
371
372 /* fill in the i2c tag */
373 sc->sc_i2c.ic_cookie = sc;
374 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus;
375 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus;
376 sc->sc_i2c.ic_send_start = tl_i2c_send_start;
377 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop;
378 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer;
379 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte;
380 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte;
381
382 #ifdef TLDEBUG
383 aprint_debug_dev(self, "default values of INTreg: 0x%x\n",
384 tl_intreg_read(sc, TL_INT_Defaults));
385 #endif
386
387 /* read mac addr */
388 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */,
389 sc->tl_enaddr, ETHER_ADDR_LEN)) {
390 aprint_error_dev(self, "error reading Ethernet address\n");
391 return;
392 }
393 aprint_normal_dev(self, "Ethernet address %s\n",
394 ether_sprintf(sc->tl_enaddr));
395
396 /* Map and establish interrupts */
397 if (pci_intr_map(pa, &intrhandle)) {
398 aprint_error_dev(self, "couldn't map interrupt\n");
399 return;
400 }
401 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
402 sc->tl_if.if_softc = sc;
403 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET,
404 tl_intr, sc);
405 if (sc->tl_ih == NULL) {
406 aprint_error_dev(self, "couldn't establish interrupt");
407 if (intrstr != NULL)
408 aprint_error(" at %s", intrstr);
409 aprint_error("\n");
410 return;
411 }
412 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
413
414 /* init these pointers, so that tl_shutdown won't try to read them */
415 sc->Rx_list = NULL;
416 sc->Tx_list = NULL;
417
418 /* allocate DMA-safe memory for control structs */
419 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
420 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 ||
421 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs,
422 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl,
423 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
424 aprint_error_dev(self, "can't allocate DMA memory for lists\n");
425 return;
426 }
427
428 /*
429 * Initialize our media structures and probe the MII.
430 *
431 * Note that we don't care about the media instance. We
432 * are expecting to have multiple PHYs on the 10/100 cards,
433 * and on those cards we exclude the internal PHY from providing
434 * 10baseT. By ignoring the instance, it allows us to not have
435 * to specify it on the command line when switching media.
436 */
437 sc->tl_mii.mii_ifp = ifp;
438 sc->tl_mii.mii_readreg = tl_mii_read;
439 sc->tl_mii.mii_writereg = tl_mii_write;
440 sc->tl_mii.mii_statchg = tl_statchg;
441 sc->tl_ec.ec_mii = &sc->tl_mii;
442 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange,
443 ether_mediastatus);
444 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY,
445 MII_OFFSET_ANY, 0);
446 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) {
447 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
448 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE);
449 } else
450 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO);
451
452 /*
453 * We can support 802.1Q VLAN-sized frames.
454 */
455 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
456
457 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
458 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
459 ifp->if_ioctl = tl_ifioctl;
460 ifp->if_start = tl_ifstart;
461 ifp->if_watchdog = tl_ifwatchdog;
462 ifp->if_init = tl_init;
463 ifp->if_stop = tl_stop;
464 ifp->if_timer = 0;
465 IFQ_SET_READY(&ifp->if_snd);
466 if_attach(ifp);
467 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr);
468
469 /*
470 * Add shutdown hook so that DMA is disabled prior to reboot.
471 * Not doing reboot before the driver initializes.
472 */
473 if (pmf_device_register1(self, NULL, NULL, tl_shutdown))
474 pmf_class_network_register(self, ifp);
475 else
476 aprint_error_dev(self, "couldn't establish power handler\n");
477
478 #if NRND > 0
479 rnd_attach_source(&sc->rnd_source, device_xname(self),
480 RND_TYPE_NET, 0);
481 #endif
482 }
483
484 static void
485 tl_reset(tl_softc_t *sc)
486 {
487 int i;
488
489 /* read stats */
490 if (sc->tl_if.if_flags & IFF_RUNNING) {
491 callout_stop(&sc->tl_tick_ch);
492 tl_read_stats(sc);
493 }
494 /* Reset adapter */
495 TL_HR_WRITE(sc, TL_HOST_CMD,
496 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst);
497 DELAY(100000);
498 /* Disable interrupts */
499 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
500 /* setup aregs & hash */
501 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
502 tl_intreg_write(sc, i, 0);
503 #ifdef TLDEBUG_ADDR
504 printf("Areg & hash registers: \n");
505 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
506 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
507 #endif
508 /* Setup NetConfig */
509 tl_intreg_write(sc, TL_INT_NetConfig,
510 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN);
511 /* Bsize: accept default */
512 /* TX commit in Acommit: accept default */
513 /* Load Ld_tmr and Ld_thr */
514 /* Ld_tmr = 3 */
515 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr);
516 /* Ld_thr = 0 */
517 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr);
518 /* Unreset MII */
519 netsio_set(sc, TL_NETSIO_NMRST);
520 DELAY(100000);
521 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
522 }
523
524 static bool
525 tl_shutdown(device_t self, int howto)
526 {
527 tl_softc_t *sc = device_private(self);
528 struct ifnet *ifp = &sc->tl_if;
529
530 tl_stop(ifp, 1);
531
532 return true;
533 }
534
535 static void
536 tl_stop(struct ifnet *ifp, int disable)
537 {
538 tl_softc_t *sc = ifp->if_softc;
539 struct Tx_list *Tx;
540 int i;
541
542 if ((ifp->if_flags & IFF_RUNNING) == 0)
543 return;
544 /* disable interrupts */
545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
546 /* stop TX and RX channels */
547 TL_HR_WRITE(sc, TL_HOST_CMD,
548 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes);
549 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP);
550 DELAY(100000);
551
552 /* stop statistics reading loop, read stats */
553 callout_stop(&sc->tl_tick_ch);
554 tl_read_stats(sc);
555
556 /* Down the MII. */
557 mii_down(&sc->tl_mii);
558
559 /* deallocate memory allocations */
560 if (sc->Rx_list) {
561 for (i = 0; i< TL_NBUF; i++) {
562 if (sc->Rx_list[i].m) {
563 bus_dmamap_unload(sc->tl_dmatag,
564 sc->Rx_list[i].m_dmamap);
565 m_freem(sc->Rx_list[i].m);
566 }
567 bus_dmamap_destroy(sc->tl_dmatag,
568 sc->Rx_list[i].m_dmamap);
569 sc->Rx_list[i].m = NULL;
570 }
571 free(sc->Rx_list, M_DEVBUF);
572 sc->Rx_list = NULL;
573 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap);
574 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap);
575 sc->hw_Rx_list = NULL;
576 while ((Tx = sc->active_Tx) != NULL) {
577 Tx->hw_list->stat = 0;
578 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
579 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap);
580 m_freem(Tx->m);
581 sc->active_Tx = Tx->next;
582 Tx->next = sc->Free_Tx;
583 sc->Free_Tx = Tx;
584 }
585 sc->last_Tx = NULL;
586 free(sc->Tx_list, M_DEVBUF);
587 sc->Tx_list = NULL;
588 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap);
589 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap);
590 sc->hw_Tx_list = NULL;
591 }
592 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
593 ifp->if_timer = 0;
594 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
595 }
596
597 static void
598 tl_restart(void *v)
599 {
600
601 tl_init(v);
602 }
603
604 static int
605 tl_init(struct ifnet *ifp)
606 {
607 tl_softc_t *sc = ifp->if_softc;
608 int i, s, error;
609 bus_size_t boundary;
610 prop_number_t prop_boundary;
611 const char *errstring;
612 char *nullbuf;
613
614 s = splnet();
615 /* cancel any pending IO */
616 tl_stop(ifp, 1);
617 tl_reset(sc);
618 if ((sc->tl_if.if_flags & IFF_UP) == 0) {
619 splx(s);
620 return 0;
621 }
622 /* Set various register to reasonable value */
623 /* setup NetCmd in promisc mode if needed */
624 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0;
625 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd,
626 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i);
627 /* Max receive size : MCLBYTES */
628 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff);
629 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH,
630 (MCLBYTES >> 8) & 0xff);
631
632 /* init MAC addr */
633 for (i = 0; i < ETHER_ADDR_LEN; i++)
634 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]);
635 /* add multicast filters */
636 tl_addr_filter(sc);
637 #ifdef TLDEBUG_ADDR
638 printf("Wrote Mac addr, Areg & hash registers are now: \n");
639 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
640 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
641 #endif
642
643 /* Pre-allocate receivers mbuf, make the lists */
644 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF,
645 M_NOWAIT|M_ZERO);
646 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF,
647 M_NOWAIT|M_ZERO);
648 if (sc->Rx_list == NULL || sc->Tx_list == NULL) {
649 errstring = "out of memory for lists";
650 error = ENOMEM;
651 goto bad;
652 }
653
654 /*
655 * Some boards (Set Engineering GFE) do not permit DMA transfers
656 * across page boundaries.
657 */
658 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev),
659 "tl-dma-page-boundary");
660 if (prop_boundary != NULL) {
661 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER);
662 boundary = (bus_size_t)prop_number_integer_value(prop_boundary);
663 } else {
664 boundary = 0;
665 }
666
667 error = bus_dmamap_create(sc->tl_dmatag,
668 sizeof(struct tl_Rx_list) * TL_NBUF, 1,
669 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK,
670 &sc->Rx_dmamap);
671 if (error == 0)
672 error = bus_dmamap_create(sc->tl_dmatag,
673 sizeof(struct tl_Tx_list) * TL_NBUF, 1,
674 sizeof(struct tl_Tx_list) * TL_NBUF, boundary,
675 BUS_DMA_WAITOK, &sc->Tx_dmamap);
676 if (error == 0)
677 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1,
678 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK,
679 &sc->null_dmamap);
680 if (error) {
681 errstring = "can't allocate DMA maps for lists";
682 goto bad;
683 }
684 memset(sc->ctrl, 0, PAGE_SIZE);
685 sc->hw_Rx_list = (void *)sc->ctrl;
686 sc->hw_Tx_list =
687 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF);
688 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF +
689 sizeof(struct tl_Tx_list) * TL_NBUF;
690 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap,
691 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL,
692 BUS_DMA_WAITOK);
693 if (error == 0)
694 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap,
695 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL,
696 BUS_DMA_WAITOK);
697 if (error == 0)
698 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap,
699 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK);
700 if (error) {
701 errstring = "can't DMA map DMA memory for lists";
702 goto bad;
703 }
704 for (i = 0; i < TL_NBUF; i++) {
705 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
706 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
707 &sc->Rx_list[i].m_dmamap);
708 if (error == 0) {
709 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
710 TL_NSEG, MCLBYTES, boundary,
711 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
712 &sc->Tx_list[i].m_dmamap);
713 }
714 if (error) {
715 errstring = "can't allocate DMA maps for mbufs";
716 goto bad;
717 }
718 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i];
719 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr
720 + sizeof(struct tl_Rx_list) * i;
721 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i];
722 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr
723 + sizeof(struct tl_Tx_list) * i;
724 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) {
725 errstring = "out of mbuf for receive list";
726 error = ENOMEM;
727 goto bad;
728 }
729 if (i > 0) { /* chain the list */
730 sc->Rx_list[i - 1].next = &sc->Rx_list[i];
731 sc->hw_Rx_list[i - 1].fwd =
732 htole32(sc->Rx_list[i].hw_listaddr);
733 sc->Tx_list[i - 1].next = &sc->Tx_list[i];
734 }
735 }
736 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0;
737 sc->Rx_list[TL_NBUF - 1].next = NULL;
738 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0;
739 sc->Tx_list[TL_NBUF - 1].next = NULL;
740
741 sc->active_Rx = &sc->Rx_list[0];
742 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1];
743 sc->active_Tx = sc->last_Tx = NULL;
744 sc->Free_Tx = &sc->Tx_list[0];
745 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
746 sizeof(struct tl_Rx_list) * TL_NBUF,
747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
748 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
749 sizeof(struct tl_Tx_list) * TL_NBUF,
750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
751 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX,
752 BUS_DMASYNC_PREWRITE);
753
754 /* set media */
755 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO)
756 error = 0;
757 else if (error != 0) {
758 errstring = "could not set media";
759 goto bad;
760 }
761
762 /* start ticks calls */
763 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
764 /* write address of Rx list and enable interrupts */
765 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr);
766 TL_HR_WRITE(sc, TL_HOST_CMD,
767 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn);
768 sc->tl_if.if_flags |= IFF_RUNNING;
769 sc->tl_if.if_flags &= ~IFF_OACTIVE;
770 splx(s);
771 return 0;
772 bad:
773 printf("%s: %s\n", device_xname(sc->sc_dev), errstring);
774 splx(s);
775 return error;
776 }
777
778
779 static uint32_t
780 tl_intreg_read(tl_softc_t *sc, uint32_t reg)
781 {
782
783 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
784 return TL_HR_READ(sc, TL_HOST_DIO_DATA);
785 }
786
787 static uint8_t
788 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg)
789 {
790
791 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
792 (reg & (~0x07)) & TL_HOST_DIOADR_MASK);
793 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07));
794 }
795
796 static void
797 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val)
798 {
799
800 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
801 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val);
802 }
803
804 static void
805 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val)
806 {
807
808 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
809 (reg & (~0x03)) & TL_HOST_DIOADR_MASK);
810 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val);
811 }
812
813 void
814 tl_mii_sync(struct tl_softc *sc)
815 {
816 int i;
817
818 netsio_clr(sc, TL_NETSIO_MTXEN);
819 for (i = 0; i < 32; i++) {
820 netsio_clr(sc, TL_NETSIO_MCLK);
821 netsio_set(sc, TL_NETSIO_MCLK);
822 }
823 }
824
825 void
826 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits)
827 {
828 int i;
829
830 netsio_set(sc, TL_NETSIO_MTXEN);
831 for (i = 1 << (nbits - 1); i; i = i >> 1) {
832 netsio_clr(sc, TL_NETSIO_MCLK);
833 netsio_read(sc, TL_NETSIO_MCLK);
834 if (data & i)
835 netsio_set(sc, TL_NETSIO_MDATA);
836 else
837 netsio_clr(sc, TL_NETSIO_MDATA);
838 netsio_set(sc, TL_NETSIO_MCLK);
839 netsio_read(sc, TL_NETSIO_MCLK);
840 }
841 }
842
843 int
844 tl_mii_read(device_t self, int phy, int reg)
845 {
846 struct tl_softc *sc = device_private(self);
847 int val = 0, i, err;
848
849 /*
850 * Read the PHY register by manually driving the MII control lines.
851 */
852
853 tl_mii_sync(sc);
854 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
855 tl_mii_sendbits(sc, MII_COMMAND_READ, 2);
856 tl_mii_sendbits(sc, phy, 5);
857 tl_mii_sendbits(sc, reg, 5);
858
859 netsio_clr(sc, TL_NETSIO_MTXEN);
860 netsio_clr(sc, TL_NETSIO_MCLK);
861 netsio_set(sc, TL_NETSIO_MCLK);
862 netsio_clr(sc, TL_NETSIO_MCLK);
863
864 err = netsio_read(sc, TL_NETSIO_MDATA);
865 netsio_set(sc, TL_NETSIO_MCLK);
866
867 /* Even if an error occurs, must still clock out the cycle. */
868 for (i = 0; i < 16; i++) {
869 val <<= 1;
870 netsio_clr(sc, TL_NETSIO_MCLK);
871 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA))
872 val |= 1;
873 netsio_set(sc, TL_NETSIO_MCLK);
874 }
875 netsio_clr(sc, TL_NETSIO_MCLK);
876 netsio_set(sc, TL_NETSIO_MCLK);
877
878 return err ? 0 : val;
879 }
880
881 void
882 tl_mii_write(device_t self, int phy, int reg, int val)
883 {
884 struct tl_softc *sc = device_private(self);
885
886 /*
887 * Write the PHY register by manually driving the MII control lines.
888 */
889
890 tl_mii_sync(sc);
891 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
892 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
893 tl_mii_sendbits(sc, phy, 5);
894 tl_mii_sendbits(sc, reg, 5);
895 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2);
896 tl_mii_sendbits(sc, val, 16);
897
898 netsio_clr(sc, TL_NETSIO_MCLK);
899 netsio_set(sc, TL_NETSIO_MCLK);
900 }
901
902 void
903 tl_statchg(device_t self)
904 {
905 tl_softc_t *sc = device_private(self);
906 uint32_t reg;
907
908 #ifdef TLDEBUG
909 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media);
910 #endif
911
912 /*
913 * We must keep the ThunderLAN and the PHY in sync as
914 * to the status of full-duplex!
915 */
916 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd);
917 if (sc->tl_mii.mii_media_active & IFM_FDX)
918 reg |= TL_NETCOMMAND_DUPLEX;
919 else
920 reg &= ~TL_NETCOMMAND_DUPLEX;
921 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg);
922 }
923
924 /********** I2C glue **********/
925
926 static int
927 tl_i2c_acquire_bus(void *cookie, int flags)
928 {
929
930 /* private bus */
931 return 0;
932 }
933
934 static void
935 tl_i2c_release_bus(void *cookie, int flags)
936 {
937
938 /* private bus */
939 }
940
941 static int
942 tl_i2c_send_start(void *cookie, int flags)
943 {
944
945 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops);
946 }
947
948 static int
949 tl_i2c_send_stop(void *cookie, int flags)
950 {
951
952 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops);
953 }
954
955 static int
956 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
957 {
958
959 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops);
960 }
961
962 static int
963 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
964 {
965
966 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops);
967 }
968
969 static int
970 tl_i2c_write_byte(void *cookie, uint8_t val, int flags)
971 {
972
973 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops);
974 }
975
976 /********** I2C bit-bang glue **********/
977
978 static void
979 tl_i2cbb_set_bits(void *cookie, uint32_t bits)
980 {
981 struct tl_softc *sc = cookie;
982 uint8_t reg;
983
984 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
985 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits;
986 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
987 }
988
989 static void
990 tl_i2cbb_set_dir(void *cookie, uint32_t bits)
991 {
992 struct tl_softc *sc = cookie;
993 uint8_t reg;
994
995 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
996 reg = (reg & ~TL_NETSIO_ETXEN) | bits;
997 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
998 }
999
1000 static uint32_t
1001 tl_i2cbb_read(void *cookie)
1002 {
1003
1004 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio);
1005 }
1006
1007 /********** End of I2C stuff **********/
1008
1009 static int
1010 tl_intr(void *v)
1011 {
1012 tl_softc_t *sc = v;
1013 struct ifnet *ifp = &sc->tl_if;
1014 struct Rx_list *Rx;
1015 struct Tx_list *Tx;
1016 struct mbuf *m;
1017 uint32_t int_type, int_reg;
1018 int ack = 0;
1019 int size;
1020
1021 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR);
1022 int_type = int_reg & TL_INTR_MASK;
1023 if (int_type == 0)
1024 return 0;
1025 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX)
1026 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev),
1027 int_type, int_reg);
1028 #endif
1029 /* disable interrupts */
1030 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
1031 switch(int_type & TL_INTR_MASK) {
1032 case TL_INTR_RxEOF:
1033 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1034 sizeof(struct tl_Rx_list) * TL_NBUF,
1035 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1036 while(le32toh(sc->active_Rx->hw_list->stat) &
1037 TL_RX_CSTAT_CPLT) {
1038 /* dequeue and requeue at end of list */
1039 ack++;
1040 Rx = sc->active_Rx;
1041 sc->active_Rx = Rx->next;
1042 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1043 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1044 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap);
1045 m = Rx->m;
1046 size = le32toh(Rx->hw_list->stat) >> 16;
1047 #ifdef TLDEBUG_RX
1048 printf("%s: RX list complete, Rx %p, size=%d\n",
1049 __func__, Rx, size);
1050 #endif
1051 if (tl_add_RxBuff(sc, Rx, m) == 0) {
1052 /*
1053 * No new mbuf, reuse the same. This means
1054 * that this packet
1055 * is lost
1056 */
1057 m = NULL;
1058 #ifdef TL_PRIV_STATS
1059 sc->ierr_nomem++;
1060 #endif
1061 #ifdef TLDEBUG
1062 printf("%s: out of mbuf, lost input packet\n",
1063 device_xname(sc->sc_dev));
1064 #endif
1065 }
1066 Rx->next = NULL;
1067 Rx->hw_list->fwd = 0;
1068 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr);
1069 sc->last_Rx->next = Rx;
1070 sc->last_Rx = Rx;
1071
1072 /* deliver packet */
1073 if (m) {
1074 if (size < sizeof(struct ether_header)) {
1075 m_freem(m);
1076 continue;
1077 }
1078 m->m_pkthdr.rcvif = ifp;
1079 m->m_pkthdr.len = m->m_len = size;
1080 #ifdef TLDEBUG_RX
1081 {
1082 struct ether_header *eh =
1083 mtod(m, struct ether_header *);
1084 printf("%s: Rx packet:\n", __func__);
1085 ether_printheader(eh);
1086 }
1087 #endif
1088 #if NBPFILTER > 0
1089 if (ifp->if_bpf)
1090 bpf_mtap(ifp->if_bpf, m);
1091 #endif /* NBPFILTER > 0 */
1092 (*ifp->if_input)(ifp, m);
1093 }
1094 }
1095 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1096 sizeof(struct tl_Rx_list) * TL_NBUF,
1097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1098 #ifdef TLDEBUG_RX
1099 printf("TL_INTR_RxEOF: ack %d\n", ack);
1100 #else
1101 if (ack == 0) {
1102 printf("%s: EOF intr without anything to read !\n",
1103 device_xname(sc->sc_dev));
1104 tl_reset(sc);
1105 /* schedule reinit of the board */
1106 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1107 return 1;
1108 }
1109 #endif
1110 break;
1111 case TL_INTR_RxEOC:
1112 ack++;
1113 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1114 sizeof(struct tl_Rx_list) * TL_NBUF,
1115 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1116 #ifdef TLDEBUG_RX
1117 printf("TL_INTR_RxEOC: ack %d\n", ack);
1118 #endif
1119 #ifdef DIAGNOSTIC
1120 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) {
1121 printf("%s: Rx EOC interrupt and active Tx list not "
1122 "cleared\n", device_xname(sc->sc_dev));
1123 return 0;
1124 } else
1125 #endif
1126 {
1127 /*
1128 * write address of Rx list and send Rx GO command, ack
1129 * interrupt and enable interrupts in one command
1130 */
1131 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr);
1132 TL_HR_WRITE(sc, TL_HOST_CMD,
1133 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type |
1134 HOST_CMD_ACK | HOST_CMD_IntOn);
1135 return 1;
1136 }
1137 case TL_INTR_TxEOF:
1138 case TL_INTR_TxEOC:
1139 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1140 sizeof(struct tl_Tx_list) * TL_NBUF,
1141 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1142 while ((Tx = sc->active_Tx) != NULL) {
1143 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0)
1144 break;
1145 ack++;
1146 #ifdef TLDEBUG_TX
1147 printf("TL_INTR_TxEOC: list 0x%x done\n",
1148 (int)Tx->hw_listaddr);
1149 #endif
1150 Tx->hw_list->stat = 0;
1151 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1152 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1153 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1154 m_freem(Tx->m);
1155 Tx->m = NULL;
1156 sc->active_Tx = Tx->next;
1157 if (sc->active_Tx == NULL)
1158 sc->last_Tx = NULL;
1159 Tx->next = sc->Free_Tx;
1160 sc->Free_Tx = Tx;
1161 }
1162 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1163 sizeof(struct tl_Tx_list) * TL_NBUF,
1164 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1165 /* if this was an EOC, ACK immediatly */
1166 if (ack)
1167 sc->tl_if.if_flags &= ~IFF_OACTIVE;
1168 if (int_type == TL_INTR_TxEOC) {
1169 #ifdef TLDEBUG_TX
1170 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n",
1171 ack);
1172 #endif
1173 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type |
1174 HOST_CMD_ACK | HOST_CMD_IntOn);
1175 if (sc->active_Tx != NULL) {
1176 /* needs a Tx go command */
1177 TL_HR_WRITE(sc, TL_HOST_CH_PARM,
1178 sc->active_Tx->hw_listaddr);
1179 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1180 }
1181 sc->tl_if.if_timer = 0;
1182 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1183 tl_ifstart(&sc->tl_if);
1184 return 1;
1185 }
1186 #ifdef TLDEBUG
1187 else {
1188 printf("TL_INTR_TxEOF: ack %d\n", ack);
1189 }
1190 #endif
1191 sc->tl_if.if_timer = 0;
1192 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1193 tl_ifstart(&sc->tl_if);
1194 break;
1195 case TL_INTR_Stat:
1196 ack++;
1197 #ifdef TLDEBUG
1198 printf("TL_INTR_Stat: ack %d\n", ack);
1199 #endif
1200 tl_read_stats(sc);
1201 break;
1202 case TL_INTR_Adc:
1203 if (int_reg & TL_INTVec_MASK) {
1204 /* adapter check conditions */
1205 printf("%s: check condition, intvect=0x%x, "
1206 "ch_param=0x%x\n", device_xname(sc->sc_dev),
1207 int_reg & TL_INTVec_MASK,
1208 TL_HR_READ(sc, TL_HOST_CH_PARM));
1209 tl_reset(sc);
1210 /* schedule reinit of the board */
1211 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1212 return 1;
1213 } else {
1214 uint8_t netstat;
1215 /* Network status */
1216 netstat =
1217 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts);
1218 printf("%s: network status, NetSts=%x\n",
1219 device_xname(sc->sc_dev), netstat);
1220 /* Ack interrupts */
1221 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts,
1222 netstat);
1223 ack++;
1224 }
1225 break;
1226 default:
1227 printf("%s: unhandled interrupt code %x!\n",
1228 device_xname(sc->sc_dev), int_type);
1229 ack++;
1230 }
1231
1232 if (ack) {
1233 /* Ack the interrupt and enable interrupts */
1234 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK |
1235 HOST_CMD_IntOn);
1236 #if NRND > 0
1237 if (RND_ENABLED(&sc->rnd_source))
1238 rnd_add_uint32(&sc->rnd_source, int_reg);
1239 #endif
1240 return 1;
1241 }
1242 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */
1243 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn);
1244 return 0;
1245 }
1246
1247 static int
1248 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1249 {
1250 struct tl_softc *sc = ifp->if_softc;
1251 int s, error;
1252
1253 s = splnet();
1254 error = ether_ioctl(ifp, cmd, data);
1255 if (error == ENETRESET) {
1256 if (ifp->if_flags & IFF_RUNNING)
1257 tl_addr_filter(sc);
1258 error = 0;
1259 }
1260 splx(s);
1261 return error;
1262 }
1263
1264 static void
1265 tl_ifstart(struct ifnet *ifp)
1266 {
1267 tl_softc_t *sc = ifp->if_softc;
1268 struct mbuf *mb_head;
1269 struct Tx_list *Tx;
1270 int segment, size;
1271 int again, error;
1272
1273 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1274 return;
1275 txloop:
1276 /* If we don't have more space ... */
1277 if (sc->Free_Tx == NULL) {
1278 #ifdef TLDEBUG
1279 printf("%s: No free TX list\n", __func__);
1280 #endif
1281 sc->tl_if.if_flags |= IFF_OACTIVE;
1282 return;
1283 }
1284 /* Grab a paquet for output */
1285 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1286 if (mb_head == NULL) {
1287 #ifdef TLDEBUG_TX
1288 printf("%s: nothing to send\n", __func__);
1289 #endif
1290 return;
1291 }
1292 Tx = sc->Free_Tx;
1293 sc->Free_Tx = Tx->next;
1294 Tx->next = NULL;
1295 again = 0;
1296 /*
1297 * Go through each of the mbufs in the chain and initialize
1298 * the transmit list descriptors with the physical address
1299 * and size of the mbuf.
1300 */
1301 tbdinit:
1302 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list));
1303 Tx->m = mb_head;
1304 size = mb_head->m_pkthdr.len;
1305 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head,
1306 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX &&
1307 Tx->m_dmamap->dm_nsegs == TL_NSEG)) {
1308 struct mbuf *mn;
1309 /*
1310 * We ran out of segments, or we will. We have to recopy this
1311 * mbuf chain first.
1312 */
1313 if (error == 0)
1314 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1315 if (again) {
1316 /* already copyed, can't do much more */
1317 m_freem(mb_head);
1318 goto bad;
1319 }
1320 again = 1;
1321 #ifdef TLDEBUG_TX
1322 printf("%s: need to copy mbuf\n", __func__);
1323 #endif
1324 #ifdef TL_PRIV_STATS
1325 sc->oerr_mcopy++;
1326 #endif
1327 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1328 if (mn == NULL) {
1329 m_freem(mb_head);
1330 goto bad;
1331 }
1332 if (mb_head->m_pkthdr.len > MHLEN) {
1333 MCLGET(mn, M_DONTWAIT);
1334 if ((mn->m_flags & M_EXT) == 0) {
1335 m_freem(mn);
1336 m_freem(mb_head);
1337 goto bad;
1338 }
1339 }
1340 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1341 mtod(mn, void *));
1342 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1343 m_freem(mb_head);
1344 mb_head = mn;
1345 goto tbdinit;
1346 }
1347 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) {
1348 Tx->hw_list->seg[segment].data_addr =
1349 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr);
1350 Tx->hw_list->seg[segment].data_count =
1351 htole32(Tx->m_dmamap->dm_segs[segment].ds_len);
1352 }
1353 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1354 Tx->m_dmamap->dm_mapsize,
1355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1356 /* We are at end of mbuf chain. check the size and
1357 * see if it needs to be extended
1358 */
1359 if (size < ETHER_MIN_TX) {
1360 #ifdef DIAGNOSTIC
1361 if (segment >= TL_NSEG) {
1362 panic("%s: to much segmets (%d)", __func__, segment);
1363 }
1364 #endif
1365 /*
1366 * add the nullbuf in the seg
1367 */
1368 Tx->hw_list->seg[segment].data_count =
1369 htole32(ETHER_MIN_TX - size);
1370 Tx->hw_list->seg[segment].data_addr =
1371 htole32(sc->null_dmamap->dm_segs[0].ds_addr);
1372 size = ETHER_MIN_TX;
1373 segment++;
1374 }
1375 /* The list is done, finish the list init */
1376 Tx->hw_list->seg[segment - 1].data_count |=
1377 htole32(TL_LAST_SEG);
1378 Tx->hw_list->stat = htole32((size << 16) | 0x3000);
1379 #ifdef TLDEBUG_TX
1380 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev),
1381 le32toh(Tx->hw_list->stat));
1382 #if 0
1383 for (segment = 0; segment < TL_NSEG; segment++) {
1384 printf(" seg %d addr 0x%x len 0x%x\n",
1385 segment,
1386 le32toh(Tx->hw_list->seg[segment].data_addr),
1387 le32toh(Tx->hw_list->seg[segment].data_count));
1388 }
1389 #endif
1390 #endif
1391 if (sc->active_Tx == NULL) {
1392 sc->active_Tx = sc->last_Tx = Tx;
1393 #ifdef TLDEBUG_TX
1394 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev),
1395 (int)Tx->hw_listaddr);
1396 #endif
1397 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1398 sizeof(struct tl_Tx_list) * TL_NBUF,
1399 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1400 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr);
1401 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1402 } else {
1403 #ifdef TLDEBUG_TX
1404 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev),
1405 (int)Tx->hw_listaddr);
1406 #endif
1407 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr);
1408 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1409 sizeof(struct tl_Tx_list) * TL_NBUF,
1410 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1411 sc->last_Tx->next = Tx;
1412 sc->last_Tx = Tx;
1413 #ifdef DIAGNOSTIC
1414 if (sc->last_Tx->hw_list->fwd & 0x7)
1415 printf("%s: physical addr 0x%x of list not properly "
1416 "aligned\n",
1417 device_xname(sc->sc_dev),
1418 sc->last_Rx->hw_list->fwd);
1419 #endif
1420 }
1421 #if NBPFILTER > 0
1422 /* Pass packet to bpf if there is a listener */
1423 if (ifp->if_bpf)
1424 bpf_mtap(ifp->if_bpf, mb_head);
1425 #endif
1426 /*
1427 * Set a 5 second timer just in case we don't hear from the card again.
1428 */
1429 ifp->if_timer = 5;
1430 goto txloop;
1431 bad:
1432 #ifdef TLDEBUG
1433 printf("%s: Out of mbuf, Tx pkt lost\n", __func__);
1434 #endif
1435 Tx->next = sc->Free_Tx;
1436 sc->Free_Tx = Tx;
1437 }
1438
1439 static void
1440 tl_ifwatchdog(struct ifnet *ifp)
1441 {
1442 tl_softc_t *sc = ifp->if_softc;
1443
1444 if ((ifp->if_flags & IFF_RUNNING) == 0)
1445 return;
1446 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1447 ifp->if_oerrors++;
1448 tl_init(ifp);
1449 }
1450
1451 static int
1452 tl_mediachange(struct ifnet *ifp)
1453 {
1454
1455 if (ifp->if_flags & IFF_UP)
1456 tl_init(ifp);
1457 return 0;
1458 }
1459
1460 static int
1461 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm)
1462 {
1463 struct mbuf *m;
1464 int error;
1465
1466 MGETHDR(m, M_DONTWAIT, MT_DATA);
1467 if (m != NULL) {
1468 MCLGET(m, M_DONTWAIT);
1469 if ((m->m_flags & M_EXT) == 0) {
1470 m_freem(m);
1471 if (oldm == NULL)
1472 return 0;
1473 m = oldm;
1474 m->m_data = m->m_ext.ext_buf;
1475 }
1476 } else {
1477 if (oldm == NULL)
1478 return 0;
1479 m = oldm;
1480 m->m_data = m->m_ext.ext_buf;
1481 }
1482
1483 /* (re)init the Rx_list struct */
1484
1485 Rx->m = m;
1486 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap,
1487 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
1488 printf("%s: bus_dmamap_load() failed (error %d) for "
1489 "tl_add_RxBuff ", device_xname(sc->sc_dev), error);
1490 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES);
1491 m_freem(m);
1492 Rx->m = NULL;
1493 return 0;
1494 }
1495 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1496 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1497 /*
1498 * Move the data pointer up so that the incoming data packet
1499 * will be 32-bit aligned.
1500 */
1501 m->m_data += 2;
1502
1503 Rx->hw_list->stat =
1504 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000);
1505 Rx->hw_list->seg.data_count =
1506 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2);
1507 Rx->hw_list->seg.data_addr =
1508 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2);
1509 return (m != oldm);
1510 }
1511
1512 static void
1513 tl_ticks(void *v)
1514 {
1515 tl_softc_t *sc = v;
1516
1517 tl_read_stats(sc);
1518
1519 /* Tick the MII. */
1520 mii_tick(&sc->tl_mii);
1521
1522 /* read statistics every seconds */
1523 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
1524 }
1525
1526 static void
1527 tl_read_stats(tl_softc_t *sc)
1528 {
1529 uint32_t reg;
1530 int ierr_overr;
1531 int ierr_code;
1532 int ierr_crc;
1533 int oerr_underr;
1534 int oerr_deferred;
1535 int oerr_coll;
1536 int oerr_multicoll;
1537 int oerr_exesscoll;
1538 int oerr_latecoll;
1539 int oerr_carrloss;
1540 struct ifnet *ifp = &sc->tl_if;
1541
1542 reg = tl_intreg_read(sc, TL_INT_STATS_TX);
1543 ifp->if_opackets += reg & 0x00ffffff;
1544 oerr_underr = reg >> 24;
1545
1546 reg = tl_intreg_read(sc, TL_INT_STATS_RX);
1547 ifp->if_ipackets += reg & 0x00ffffff;
1548 ierr_overr = reg >> 24;
1549
1550 reg = tl_intreg_read(sc, TL_INT_STATS_FERR);
1551 ierr_crc = (reg & TL_FERR_CRC) >> 16;
1552 ierr_code = (reg & TL_FERR_CODE) >> 24;
1553 oerr_deferred = (reg & TL_FERR_DEF);
1554
1555 reg = tl_intreg_read(sc, TL_INT_STATS_COLL);
1556 oerr_multicoll = (reg & TL_COL_MULTI);
1557 oerr_coll = (reg & TL_COL_SINGLE) >> 16;
1558
1559 reg = tl_intreg_read(sc, TL_INT_LERR);
1560 oerr_exesscoll = (reg & TL_LERR_ECOLL);
1561 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8;
1562 oerr_carrloss = (reg & TL_LERR_CL) >> 16;
1563
1564
1565 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll +
1566 oerr_carrloss;
1567 ifp->if_collisions += oerr_coll + oerr_multicoll;
1568 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc;
1569
1570 if (ierr_overr)
1571 printf("%s: receiver ring buffer overrun\n",
1572 device_xname(sc->sc_dev));
1573 if (oerr_underr)
1574 printf("%s: transmit buffer underrun\n",
1575 device_xname(sc->sc_dev));
1576 #ifdef TL_PRIV_STATS
1577 sc->ierr_overr += ierr_overr;
1578 sc->ierr_code += ierr_code;
1579 sc->ierr_crc += ierr_crc;
1580 sc->oerr_underr += oerr_underr;
1581 sc->oerr_deferred += oerr_deferred;
1582 sc->oerr_coll += oerr_coll;
1583 sc->oerr_multicoll += oerr_multicoll;
1584 sc->oerr_exesscoll += oerr_exesscoll;
1585 sc->oerr_latecoll += oerr_latecoll;
1586 sc->oerr_carrloss += oerr_carrloss;
1587 #endif
1588 }
1589
1590 static void
1591 tl_addr_filter(tl_softc_t *sc)
1592 {
1593 struct ether_multistep step;
1594 struct ether_multi *enm;
1595 uint32_t hash[2] = {0, 0};
1596 int i;
1597
1598 sc->tl_if.if_flags &= ~IFF_ALLMULTI;
1599 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm);
1600 while (enm != NULL) {
1601 #ifdef TLDEBUG
1602 printf("%s: addrs %s %s\n", __func__,
1603 ether_sprintf(enm->enm_addrlo),
1604 ether_sprintf(enm->enm_addrhi));
1605 #endif
1606 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1607 i = tl_multicast_hash(enm->enm_addrlo);
1608 hash[i / 32] |= 1 << (i%32);
1609 } else {
1610 hash[0] = hash[1] = 0xffffffff;
1611 sc->tl_if.if_flags |= IFF_ALLMULTI;
1612 break;
1613 }
1614 ETHER_NEXT_MULTI(step, enm);
1615 }
1616 #ifdef TLDEBUG
1617 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1618 #endif
1619 tl_intreg_write(sc, TL_INT_HASH1, hash[0]);
1620 tl_intreg_write(sc, TL_INT_HASH2, hash[1]);
1621 }
1622
1623 static int
1624 tl_multicast_hash(uint8_t *a)
1625 {
1626 int hash;
1627
1628 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1629 #define xor8(a,b,c,d,e,f,g,h) \
1630 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \
1631 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1632
1633 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1634 DA(a,36), DA(a,42));
1635 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1636 DA(a,37), DA(a,43)) << 1;
1637 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1638 DA(a,38), DA(a,44)) << 2;
1639 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1640 DA(a,39), DA(a,45)) << 3;
1641 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1642 DA(a,40), DA(a,46)) << 4;
1643 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1644 DA(a,41), DA(a,47)) << 5;
1645
1646 return hash;
1647 }
1648
1649 #if defined(TLDEBUG_RX)
1650 void
1651 ether_printheader(struct ether_header *eh)
1652 {
1653 uint8_t *c = (uint8_t *)eh;
1654 int i;
1655
1656 for (i = 0; i < sizeof(struct ether_header); i++)
1657 printf("%02x ", (u_int)c[i]);
1658 printf("\n");
1659 }
1660 #endif
NetBSD on the FriendlyARM MINI2440