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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / ifpci.c
blob96ce62fd57086c9c2b88b0f48b8f1f28ff1dc947
1 /* $NetBSD: ifpci.c,v 1.29 2009/11/26 15:17:10 njoly Exp $ */
2 /*
3 * Copyright (c) 1999 Gary Jennejohn. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 * 4. Altered versions must be plainly marked as such, and must not be
18 * misrepresented as being the original software and/or documentation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 *---------------------------------------------------------------------------
33 * a lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
34 *---------------------------------------------------------------------------
35 *
36 * Fritz!Card PCI driver
37 * ------------------------------------------------
38 *
39 * $Id: ifpci.c,v 1.30 2009/12/06 23:14:05 dyoung Exp $
40 *
41 * last edit-date: [Fri Jan 5 11:38:58 2001]
42 *
43 *---------------------------------------------------------------------------*/
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: ifpci.c,v 1.29 2009/11/26 15:17:10 njoly Exp $");
47
48
49 #include <sys/param.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/systm.h>
53 #include <sys/mbuf.h>
54
55 #include <sys/bus.h>
56 #include <sys/device.h>
57
58 #include <sys/socket.h>
59 #include <net/if.h>
60
61 #include <sys/callout.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66 #include <netisdn/i4b_debug.h>
67 #include <netisdn/i4b_ioctl.h>
68
69 #include <netisdn/i4b_global.h>
70 #include <netisdn/i4b_l2.h>
71 #include <netisdn/i4b_l1l2.h>
72 #include <netisdn/i4b_trace.h>
73 #include <netisdn/i4b_mbuf.h>
74
75 #include <dev/ic/isic_l1.h>
76 #include <dev/ic/isac.h>
77 #include <dev/ic/hscx.h>
78
79 #include <dev/pci/isic_pci.h>
80
81 /* PCI config map to use (only one in this driver) */
82 #define FRITZPCI_PORT0_IO_MAPOFF PCI_MAPREG_START+4
83 #define FRITZPCI_PORT0_MEM_MAPOFF PCI_MAPREG_START
84
85 static isdn_link_t *avma1pp_ret_linktab(void *token, int channel);
86 static void avma1pp_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc);
87
88 void n_connect_request(struct call_desc *cd);
89 void n_connect_response(struct call_desc *cd, int response, int cause);
90 void n_disconnect_request(struct call_desc *cd, int cause);
91 void n_alert_request(struct call_desc *cd);
92 void n_mgmt_command(struct isdn_l3_driver *drv, int cmd, void *parm);
93
94 extern const struct isdn_layer1_isdnif_driver isic_std_driver;
95
96 const struct isdn_l3_driver_functions
97 ifpci_l3_driver = {
98 avma1pp_ret_linktab,
99 avma1pp_set_link,
100 n_connect_request,
101 n_connect_response,
102 n_disconnect_request,
103 n_alert_request,
104 NULL,
105 NULL,
106 n_mgmt_command
107 };
108
109 struct ifpci_softc {
110 struct isic_softc sc_isic; /* parent class */
111
112 /* PCI-specific goo */
113 void *sc_ih; /* interrupt handler */
114 bus_addr_t sc_base;
115 bus_size_t sc_size;
116 pci_chipset_tag_t sc_pc;
117 };
118
119 /* prototypes */
120 static void avma1pp_disable(struct isic_softc *);
121 static int isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc);
122
123 static int avma1pp_intr(void*);
124 static void avma1pp_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size);
125 static void avma1pp_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size);
126 static void avma1pp_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data);
127 static u_int8_t avma1pp_read_reg(struct isic_softc *sc, int what, bus_size_t offs);
128 static void hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc);
129 static void hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc);
130 static void hscx_write_reg(int chan, u_int off, u_int val, struct isic_softc *sc);
131 static u_char hscx_read_reg(int chan, u_int off, struct isic_softc *sc);
132 static u_int hscx_read_reg_int(int chan, u_int off, struct isic_softc *sc);
133 static void avma1pp_bchannel_stat(isdn_layer1token, int h_chan, bchan_statistics_t *bsp);
134 static void avma1pp_map_int(struct ifpci_softc *sc, struct pci_attach_args *pa);
135 static void avma1pp_bchannel_setup(isdn_layer1token, int h_chan, int bprot, int activate);
136 static void avma1pp_init_linktab(struct isic_softc *);
137 static int ifpci_match(device_t parent, cfdata_t match, void *aux);
138 static void ifpci_attach(device_t parent, device_t self, void *aux);
139 static int ifpci_detach(device_t self, int flags);
140 static int ifpci_activate(device_t self, enum devact act);
141
142 CFATTACH_DECL(ifpci, sizeof(struct ifpci_softc),
143 ifpci_match, ifpci_attach, ifpci_detach, ifpci_activate);
144
145 /*---------------------------------------------------------------------------*
146 * AVM PCI Fritz!Card special registers
147 *---------------------------------------------------------------------------*/
148
149 /*
150 * register offsets from i/o base
151 */
152 #define STAT0_OFFSET 0x02
153 #define STAT1_OFFSET 0x03
154 #define ADDR_REG_OFFSET 0x04
155 /*#define MODREG_OFFSET 0x06
156 #define VERREG_OFFSET 0x07*/
157
158 /* these 2 are used to select an ISAC register set */
159 #define ISAC_LO_REG_OFFSET 0x04
160 #define ISAC_HI_REG_OFFSET 0x06
161
162 /* offset higher than this goes to the HI register set */
163 #define MAX_LO_REG_OFFSET 0x2f
164
165 /* mask for the offset */
166 #define ISAC_REGSET_MASK 0x0f
167
168 /* the offset from the base to the ISAC registers */
169 #define ISAC_REG_OFFSET 0x10
170
171 /* the offset from the base to the ISAC FIFO */
172 #define ISAC_FIFO 0x02
173
174 /* not really the HSCX, but sort of */
175 #define HSCX_FIFO 0x00
176 #define HSCX_STAT 0x04
177
178 /*
179 * AVM PCI Status Latch 0 read only bits
180 */
181 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active low */
182 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active low */
183 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active low */
184 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
185 /* actually active LOW */
186 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
187
188 /*
189 * AVM Status Latch 0 write only bits
190 */
191 #define ASL_RESET_ALL 0x01 /* reset siemens IC's, active 1 */
192 #define ASL_TIMERDISABLE 0x02 /* active high */
193 #define ASL_TIMERRESET 0x04 /* active high */
194 #define ASL_ENABLE_INT 0x08 /* active high */
195 #define ASL_TESTBIT 0x10 /* active high */
196
197 /*
198 * AVM Status Latch 1 write only bits
199 */
200 #define ASL1_INTSEL 0x0f /* active high */
201 #define ASL1_ENABLE_IOM 0x80 /* active high */
202
203 /*
204 * "HSCX" mode bits
205 */
206 #define HSCX_MODE_ITF_FLG 0x01
207 #define HSCX_MODE_TRANS 0x02
208 #define HSCX_MODE_CCR_7 0x04
209 #define HSCX_MODE_CCR_16 0x08
210 #define HSCX_MODE_TESTLOOP 0x80
211
212 /*
213 * "HSCX" status bits
214 */
215 #define HSCX_STAT_RME 0x01
216 #define HSCX_STAT_RDO 0x10
217 #define HSCX_STAT_CRCVFRRAB 0x0E
218 #define HSCX_STAT_CRCVFR 0x06
219 #define HSCX_STAT_RML_MASK 0x3f00
220
221 /*
222 * "HSCX" interrupt bits
223 */
224 #define HSCX_INT_XPR 0x80
225 #define HSCX_INT_XDU 0x40
226 #define HSCX_INT_RPR 0x20
227 #define HSCX_INT_MASK 0xE0
228
229 /*
230 * "HSCX" command bits
231 */
232 #define HSCX_CMD_XRS 0x80
233 #define HSCX_CMD_XME 0x01
234 #define HSCX_CMD_RRS 0x20
235 #define HSCX_CMD_XML_MASK 0x3f00
236
237 /*
238 * Commands and parameters are sent to the "HSCX" as a long, but the
239 * fields are handled as bytes.
240 *
241 * The long contains:
242 * (prot << 16)|(txl << 8)|cmd
243 *
244 * where:
245 * prot = protocol to use
246 * txl = transmit length
247 * cmd = the command to be executed
248 *
249 * The fields are defined as u_char in struct isic_softc.
250 *
251 * Macro to coalesce the byte fields into a u_int
252 */
253 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
254 | (sc->avma1pp_prot << 16))
255
256 /*
257 * to prevent deactivating the "HSCX" when both channels are active we
258 * define an HSCX_ACTIVE flag which is or'd into the channel's state
259 * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
260 * It is set high to allow room for new flags.
261 */
262 #define HSCX_AVMA1PP_ACTIVE 0x1000
263
264 static int
265 ifpci_match(device_t parent, cfdata_t match, void *aux)
266 {
267 struct pci_attach_args *pa = aux;
268
269 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AVM &&
270 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AVM_FRITZ_CARD)
271 return 1;
272 return 0;
273 }
274
275 static void
276 ifpci_attach(device_t parent, device_t self, void *aux)
277 {
278 struct ifpci_softc *psc = device_private(self);
279 struct pci_attach_args *pa = aux;
280 struct isic_softc *sc = &psc->sc_isic;
281 struct isdn_l3_driver *drv;
282 u_int v;
283
284 /* announce */
285 printf(": Fritz!PCI card\n");
286
287 /* initialize sc */
288 callout_init(&sc->sc_T3_callout, 0);
289 callout_init(&sc->sc_T4_callout, 0);
290
291 /* setup io mappings */
292 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
293 sc->sc_num_mappings = 1;
294 MALLOC_MAPS(sc);
295 sc->sc_maps[0].size = 0;
296 if (pci_mapreg_map(pa, FRITZPCI_PORT0_MEM_MAPOFF, PCI_MAPREG_TYPE_MEM, 0,
297 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size) != 0
298 && pci_mapreg_map(pa, FRITZPCI_PORT0_IO_MAPOFF, PCI_MAPREG_TYPE_IO, 0,
299 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size) != 0) {
300 aprint_error_dev(&sc->sc_dev, "can't map card\n");
301 return;
302 }
303
304 /* setup access routines */
305
306 sc->clearirq = NULL;
307 sc->readreg = avma1pp_read_reg;
308 sc->writereg = avma1pp_write_reg;
309
310 sc->readfifo = avma1pp_read_fifo;
311 sc->writefifo = avma1pp_write_fifo;
312
313
314 /* setup card type */
315
316 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
317
318 /* setup IOM bus type */
319
320 sc->sc_bustyp = BUS_TYPE_IOM2;
321
322 /* this is no IPAC based card */
323 sc->sc_ipac = 0;
324 sc->sc_bfifolen = HSCX_FIFO_LEN;
325
326 /* setup interrupt mapping */
327 avma1pp_map_int(psc, pa);
328
329 /* init the card */
330 /* the Linux driver does this to clear any pending ISAC interrupts */
331 /* see if it helps any - XXXX */
332 v = 0;
333 v = ISAC_READ(I_STAR);
334 v = ISAC_READ(I_MODE);
335 v = ISAC_READ(I_ADF2);
336 v = ISAC_READ(I_ISTA);
337 if (v & ISAC_ISTA_EXI)
338 {
339 v = ISAC_READ(I_EXIR);
340 }
341 v = ISAC_READ(I_CIRR);
342 ISAC_WRITE(I_MASK, 0xff);
343 /* the Linux driver does this to clear any pending HSCX interrupts */
344 v = hscx_read_reg_int(0, HSCX_STAT, sc);
345 v = hscx_read_reg_int(1, HSCX_STAT, sc);
346
347 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
348 DELAY(SEC_DELAY/100); /* 10 ms */
349 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
350 DELAY(SEC_DELAY/100); /* 10 ms */
351
352 /* setup i4b infrastructure (have to roll our own here) */
353
354 /* sc->sc_isac_version = ((ISAC_READ(I_RBCH)) >> 5) & 0x03; */
355 printf("%s: ISAC %s (IOM-%c)\n", device_xname(&sc->sc_dev),
356 "2085 Version A1/A2 or 2086/2186 Version 1.1",
357 sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
358
359 /* init the ISAC */
360 isic_isac_init(sc);
361
362 /* init the "HSCX" */
363 avma1pp_bchannel_setup(sc, HSCX_CH_A, BPROT_NONE, 0);
364
365 avma1pp_bchannel_setup(sc, HSCX_CH_B, BPROT_NONE, 0);
366
367 /* can't use the normal B-Channel stuff */
368 avma1pp_init_linktab(sc);
369
370 /* set trace level */
371
372 sc->sc_trace = TRACE_OFF;
373
374 sc->sc_state = ISAC_IDLE;
375
376 sc->sc_ibuf = NULL;
377 sc->sc_ib = NULL;
378 sc->sc_ilen = 0;
379
380 sc->sc_obuf = NULL;
381 sc->sc_op = NULL;
382 sc->sc_ol = 0;
383 sc->sc_freeflag = 0;
384
385 sc->sc_obuf2 = NULL;
386 sc->sc_freeflag2 = 0;
387
388 /* init higher protocol layers */
389 drv = isdn_attach_isdnif(device_xname(&sc->sc_dev),
390 "AVM Fritz!PCI", &sc->sc_l2, &ifpci_l3_driver, NBCH_BRI);
391 sc->sc_l3token = drv;
392 sc->sc_l2.driver = &isic_std_driver;
393 sc->sc_l2.l1_token = sc;
394 sc->sc_l2.drv = drv;
395 isdn_layer2_status_ind(&sc->sc_l2, drv, STI_ATTACH, 1);
396 isdn_isdnif_ready(drv->isdnif);
397 }
398
399 static int
400 ifpci_detach(device_t self, int flags)
401 {
402 struct ifpci_softc *psc = device_private(self);
403
404 bus_space_unmap(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
405 bus_space_free(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
406 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
407
408 return (0);
409 }
410
411 int
412 ifpci_activate(device_t self, enum devact act)
413 {
414 struct ifpci_softc *psc = device_private(self);
415
416 switch (act) {
417 case DVACT_DEACTIVATE:
418 psc->sc_isic.sc_intr_valid = ISIC_INTR_DYING;
419 isdn_layer2_status_ind(&psc->sc_isic.sc_l2, psc->sc_isic.sc_l3token, STI_ATTACH, 0);
420 isdn_detach_isdnif(psc->sc_isic.sc_l3token);
421 psc->sc_isic.sc_l3token = NULL;
422 return 0;
423 default:
424 return EOPNOTSUPP;
425 }
426 }
427
428 /*---------------------------------------------------------------------------*
429 * AVM read fifo routines
430 *---------------------------------------------------------------------------*/
431
432 static void
433 avma1pp_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
434 {
435 switch (what) {
436 case ISIC_WHAT_ISAC:
437 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, ISAC_FIFO);
438 bus_space_read_multi_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, buf, size);
439 break;
440 case ISIC_WHAT_HSCXA:
441 hscx_read_fifo(0, buf, size, sc);
442 break;
443 case ISIC_WHAT_HSCXB:
444 hscx_read_fifo(1, buf, size, sc);
445 break;
446 }
447 }
448
449 static void
450 hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc)
451 {
452 u_int32_t *ip;
453 size_t cnt;
454
455 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
456 ip = (u_int32_t *)buf;
457 cnt = 0;
458 /* what if len isn't a multiple of sizeof(int) and buf is */
459 /* too small ???? */
460 while (cnt < len)
461 {
462 *ip++ = bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET);
463 cnt += 4;
464 }
465 }
466
467 /*---------------------------------------------------------------------------*
468 * AVM write fifo routines
469 *---------------------------------------------------------------------------*/
470
471 static void
472 avma1pp_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
473 {
474 switch (what) {
475 case ISIC_WHAT_ISAC:
476 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, ISAC_FIFO);
477 bus_space_write_multi_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, buf, size);
478 break;
479 case ISIC_WHAT_HSCXA:
480 hscx_write_fifo(0, buf, size, sc);
481 break;
482 case ISIC_WHAT_HSCXB:
483 hscx_write_fifo(1, buf, size, sc);
484 break;
485 }
486 }
487
488 static void
489 hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc)
490 {
491 const u_int32_t *ip;
492 size_t cnt;
493 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
494
495 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
496 sc->avma1pp_txl = 0;
497 if (Bchan->out_mbuf_cur == NULL)
498 {
499 if (Bchan->bprot != BPROT_NONE)
500 sc->avma1pp_cmd |= HSCX_CMD_XME;
501 }
502 if (len != sc->sc_bfifolen)
503 sc->avma1pp_txl = len;
504
505 cnt = 0; /* borrow cnt */
506 AVMA1PPSETCMDLONG(cnt);
507 hscx_write_reg(chan, HSCX_STAT, cnt, sc);
508
509 ip = (const u_int32_t *)buf;
510 cnt = 0;
511 while (cnt < len)
512 {
513 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, *ip);
514 ip++;
515 cnt += 4;
516 }
517 }
518
519 /*---------------------------------------------------------------------------*
520 * AVM write register routines
521 *---------------------------------------------------------------------------*/
522
523 static void
524 avma1pp_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
525 {
526 u_char reg_bank;
527 switch (what) {
528 case ISIC_WHAT_ISAC:
529 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
530 /* set the register bank */
531 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, reg_bank);
532 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
533 break;
534 case ISIC_WHAT_HSCXA:
535 hscx_write_reg(0, offs, data, sc);
536 break;
537 case ISIC_WHAT_HSCXB:
538 hscx_write_reg(1, offs, data, sc);
539 break;
540 }
541 }
542
543 static void
544 hscx_write_reg(int chan, u_int off, u_int val, struct isic_softc *sc)
545 {
546 /* HACK */
547 if (off == H_MASK)
548 return;
549 /* point at the correct channel */
550 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
551 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + off, val);
552 }
553
554 /*---------------------------------------------------------------------------*
555 * AVM read register routines
556 *---------------------------------------------------------------------------*/
557
558 static u_int8_t
559 avma1pp_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
560 {
561 u_char reg_bank;
562 switch (what) {
563 case ISIC_WHAT_ISAC:
564 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
565 /* set the register bank */
566 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, reg_bank);
567 return(bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET +
568 (offs & ISAC_REGSET_MASK)));
569 case ISIC_WHAT_HSCXA:
570 return hscx_read_reg(0, offs, sc);
571 case ISIC_WHAT_HSCXB:
572 return hscx_read_reg(1, offs, sc);
573 }
574 return 0;
575 }
576
577 static u_char
578 hscx_read_reg(int chan, u_int off, struct isic_softc *sc)
579 {
580 return(hscx_read_reg_int(chan, off, sc) & 0xff);
581 }
582
583 /*
584 * need to be able to return an int because the RBCH is in the 2nd
585 * byte.
586 */
587 static u_int
588 hscx_read_reg_int(int chan, u_int off, struct isic_softc *sc)
589 {
590 /* HACK */
591 if (off == H_ISTA)
592 return(0);
593 /* point at the correct channel */
594 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
595 return(bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + off));
596 }
597
598 /*
599 * this is the real interrupt routine
600 */
601 static void
602 avma1pp_hscx_intr(int h_chan, u_int stat, struct isic_softc *sc)
603 {
604 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
605 int activity = -1;
606 u_int param = 0;
607
608 NDBGL1(L1_H_IRQ, "%#x", stat);
609
610 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
611 {
612 chan->stat_XDU++;
613 NDBGL1(L1_H_XFRERR, "xmit data underrun");
614 /* abort the transmission */
615 sc->avma1pp_txl = 0;
616 sc->avma1pp_cmd |= HSCX_CMD_XRS;
617 AVMA1PPSETCMDLONG(param);
618 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
619 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
620 AVMA1PPSETCMDLONG(param);
621 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
622
623 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
624 {
625 i4b_Bfreembuf(chan->out_mbuf_head);
626 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
627 }
628 }
629
630 /*
631 * The following is based on examination of the Linux driver.
632 *
633 * The logic here is different than with a "real" HSCX; all kinds
634 * of information (interrupt/status bits) are in stat.
635 * HSCX_INT_RPR indicates a receive interrupt
636 * HSCX_STAT_RDO indicates an overrun condition, abort -
637 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
638 * HSCX_STAT_RME indicates end-of-frame and apparently any
639 * CRC/framing errors are only reported in this state.
640 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
641 * CRC/framing error
642 */
643
644 if(stat & HSCX_INT_RPR)
645 {
646 register int fifo_data_len;
647 int error = 0;
648 /* always have to read the FIFO, so use a scratch buffer */
649 u_char scrbuf[HSCX_FIFO_LEN];
650
651 if(stat & HSCX_STAT_RDO)
652 {
653 chan->stat_RDO++;
654 NDBGL1(L1_H_XFRERR, "receive data overflow");
655 error++;
656 }
657
658 /*
659 * check whether we're receiving data for an inactive B-channel
660 * and discard it. This appears to happen for telephony when
661 * both B-channels are active and one is deactivated. Since
662 * it is not really possible to deactivate the channel in that
663 * case (the ASIC seems to deactivate _both_ channels), the
664 * "deactivated" channel keeps receiving data which can lead
665 * to exhaustion of mbufs and a kernel panic.
666 *
667 * This is a hack, but it's the only solution I can think of
668 * without having the documentation for the ASIC.
669 * GJ - 28 Nov 1999
670 */
671 if (chan->state == HSCX_IDLE)
672 {
673 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
674 error++;
675 }
676
677 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
678
679 if(fifo_data_len == 0)
680 fifo_data_len = sc->sc_bfifolen;
681
682 /* ALWAYS read data from HSCX fifo */
683
684 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
685 chan->rxcount += fifo_data_len;
686
687 /* all error conditions checked, now decide and take action */
688
689 if(error == 0)
690 {
691 if(chan->in_mbuf == NULL)
692 {
693 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
694 panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!");
695 chan->in_cbptr = chan->in_mbuf->m_data;
696 chan->in_len = 0;
697 }
698
699 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
700 {
701 /* OK to copy the data */
702 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
703 chan->in_cbptr += fifo_data_len;
704 chan->in_len += fifo_data_len;
705
706 /* setup mbuf data length */
707
708 chan->in_mbuf->m_len = chan->in_len;
709 chan->in_mbuf->m_pkthdr.len = chan->in_len;
710
711 if(sc->sc_trace & TRACE_B_RX)
712 {
713 struct i4b_trace_hdr hdr;
714 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
715 hdr.dir = FROM_NT;
716 hdr.count = ++sc->sc_trace_bcount;
717 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
718 }
719
720 if (stat & HSCX_STAT_RME)
721 {
722 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
723 {
724 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
725 activity = ACT_RX;
726
727 /* mark buffer ptr as unused */
728
729 chan->in_mbuf = NULL;
730 chan->in_cbptr = NULL;
731 chan->in_len = 0;
732 }
733 else
734 {
735 chan->stat_CRC++;
736 NDBGL1(L1_H_XFRERR, "CRC/RAB");
737 if (chan->in_mbuf != NULL)
738 {
739 i4b_Bfreembuf(chan->in_mbuf);
740 chan->in_mbuf = NULL;
741 chan->in_cbptr = NULL;
742 chan->in_len = 0;
743 }
744 }
745 }
746 } /* END enough space in mbuf */
747 else
748 {
749 if(chan->bprot == BPROT_NONE)
750 {
751 /* setup mbuf data length */
752
753 chan->in_mbuf->m_len = chan->in_len;
754 chan->in_mbuf->m_pkthdr.len = chan->in_len;
755
756 if(sc->sc_trace & TRACE_B_RX)
757 {
758 struct i4b_trace_hdr hdr;
759 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
760 hdr.dir = FROM_NT;
761 hdr.count = ++sc->sc_trace_bcount;
762 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
763 }
764
765 if(!(isdn_bchan_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
766 activity = ACT_RX;
767
768 /* move rx'd data to rx queue */
769
770 if (!(IF_QFULL(&chan->rx_queue)))
771 {
772 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
773 }
774 else
775 {
776 i4b_Bfreembuf(chan->in_mbuf);
777 }
778
779 /* signal upper layer that data are available */
780 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
781
782 /* alloc new buffer */
783
784 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
785 panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!");
786
787 /* setup new data ptr */
788
789 chan->in_cbptr = chan->in_mbuf->m_data;
790
791 /* OK to copy the data */
792 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
793
794 chan->in_cbptr += fifo_data_len;
795 chan->in_len = fifo_data_len;
796
797 chan->rxcount += fifo_data_len;
798 }
799 else
800 {
801 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
802 chan->in_cbptr = chan->in_mbuf->m_data;
803 chan->in_len = 0;
804 }
805 }
806 } /* if(error == 0) */
807 else
808 {
809 /* land here for RDO */
810 if (chan->in_mbuf != NULL)
811 {
812 i4b_Bfreembuf(chan->in_mbuf);
813 chan->in_mbuf = NULL;
814 chan->in_cbptr = NULL;
815 chan->in_len = 0;
816 }
817 sc->avma1pp_txl = 0;
818 sc->avma1pp_cmd |= HSCX_CMD_RRS;
819 AVMA1PPSETCMDLONG(param);
820 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
821 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
822 AVMA1PPSETCMDLONG(param);
823 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
824 }
825 }
826
827
828 /* transmit fifo empty, new data can be written to fifo */
829
830 if(stat & HSCX_INT_XPR)
831 {
832 /*
833 * for a description what is going on here, please have
834 * a look at isic_bchannel_start() in i4b_bchan.c !
835 */
836
837 NDBGL1(L1_H_IRQ, "%s: chan %d - XPR, Tx Fifo Empty!", device_xname(&sc->sc_dev), h_chan);
838
839 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
840 {
841 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
842
843 if(chan->out_mbuf_head == NULL)
844 {
845 chan->state &= ~HSCX_TX_ACTIVE;
846 (*chan->l4_driver->bch_tx_queue_empty)(chan->l4_driver_softc);
847 }
848 else
849 {
850 chan->state |= HSCX_TX_ACTIVE;
851 chan->out_mbuf_cur = chan->out_mbuf_head;
852 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
853 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
854
855 if(sc->sc_trace & TRACE_B_TX)
856 {
857 struct i4b_trace_hdr hdr;
858 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
859 hdr.dir = FROM_TE;
860 hdr.count = ++sc->sc_trace_bcount;
861 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
862 }
863
864 if(chan->bprot == BPROT_NONE)
865 {
866 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
867 activity = ACT_TX;
868 }
869 else
870 {
871 activity = ACT_TX;
872 }
873 }
874 }
875
876 isic_hscx_fifo(chan, sc);
877 }
878
879 /* call timeout handling routine */
880
881 if(activity == ACT_RX || activity == ACT_TX)
882 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
883 }
884
885 /*
886 * this is the main routine which checks each channel and then calls
887 * the real interrupt routine as appropriate
888 */
889 static void
890 avma1pp_hscx_int_handler(struct isic_softc *sc)
891 {
892 u_int stat;
893
894 /* has to be a u_int because the byte count is in the 2nd byte */
895 stat = hscx_read_reg_int(0, HSCX_STAT, sc);
896 if (stat & HSCX_INT_MASK)
897 avma1pp_hscx_intr(0, stat, sc);
898 stat = hscx_read_reg_int(1, HSCX_STAT, sc);
899 if (stat & HSCX_INT_MASK)
900 avma1pp_hscx_intr(1, stat, sc);
901 }
902
903 static void
904 avma1pp_disable(struct isic_softc *sc)
905 {
906 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
907 }
908
909 static int
910 avma1pp_intr(void *parm)
911 {
912 struct isic_softc *sc = parm;
913 int ret = 0;
914 #define OURS ret = 1
915 u_char stat;
916
917 if (sc->sc_intr_valid != ISIC_INTR_VALID)
918 return 0;
919
920 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
921 NDBGL1(L1_H_IRQ, "stat %x", stat);
922 /* was there an interrupt from this card ? */
923 if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
924 return 0; /* no */
925 /* interrupts are low active */
926 if (!(stat & ASL_IRQ_TIMER))
927 NDBGL1(L1_H_IRQ, "timer interrupt ???");
928 if (!(stat & ASL_IRQ_HSCX))
929 {
930 NDBGL1(L1_H_IRQ, "HSCX");
931 avma1pp_hscx_int_handler(sc);
932 OURS;
933 }
934 if (!(stat & ASL_IRQ_ISAC))
935 {
936 NDBGL1(L1_H_IRQ, "ISAC");
937 for (;;) {
938 /* get isac irq status */
939 u_int8_t isac_irq_stat = ISAC_READ(I_ISTA);
940 if (!isac_irq_stat)
941 break;
942 isic_isac_irq(sc, isac_irq_stat);
943 }
944 OURS;
945 }
946 return ret;
947 }
948
949 static void
950 avma1pp_map_int(struct ifpci_softc *psc, struct pci_attach_args *pa)
951 {
952 struct isic_softc *sc = &psc->sc_isic;
953 pci_chipset_tag_t pc = pa->pa_pc;
954 pci_intr_handle_t ih;
955 const char *intrstr;
956
957 /* Map and establish the interrupt. */
958 if (pci_intr_map(pa, &ih)) {
959 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n");
960 avma1pp_disable(sc);
961 return;
962 }
963 psc->sc_pc = pc;
964 intrstr = pci_intr_string(pc, ih);
965 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, avma1pp_intr, sc);
966 if (psc->sc_ih == NULL) {
967 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt");
968 if (intrstr != NULL)
969 aprint_error(" at %s", intrstr);
970 aprint_error("\n");
971 avma1pp_disable(sc);
972 return;
973 }
974 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr);
975 }
976
977 static void
978 avma1pp_hscx_init(struct isic_softc *sc, int h_chan, int activate)
979 {
980 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
981 u_int param = 0;
982
983 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
984 device_xname(&sc->sc_dev), h_chan, activate ? "activate" : "deactivate");
985
986 if (activate == 0)
987 {
988 /* only deactivate if both channels are idle */
989 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
990 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
991 {
992 return;
993 }
994 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
995 sc->avma1pp_prot = HSCX_MODE_TRANS;
996 AVMA1PPSETCMDLONG(param);
997 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
998 return;
999 }
1000 if(chan->bprot == BPROT_RHDLC)
1001 {
1002 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1003
1004 /* HDLC Frames, transparent mode 0 */
1005 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1006 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1007 AVMA1PPSETCMDLONG(param);
1008 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1009 sc->avma1pp_cmd = HSCX_CMD_XRS;
1010 AVMA1PPSETCMDLONG(param);
1011 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1012 sc->avma1pp_cmd = 0;
1013 }
1014 else
1015 {
1016 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1017
1018 /* Raw Telephony, extended transparent mode 1 */
1019 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1020 sc->avma1pp_prot = HSCX_MODE_TRANS;
1021 AVMA1PPSETCMDLONG(param);
1022 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1023 sc->avma1pp_cmd = HSCX_CMD_XRS;
1024 AVMA1PPSETCMDLONG(param);
1025 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1026 sc->avma1pp_cmd = 0;
1027 }
1028 }
1029
1030 static void
1031 avma1pp_bchannel_setup(isdn_layer1token t, int h_chan, int bprot, int activate)
1032 {
1033 struct isic_softc *sc = (struct isic_softc*)t;
1034 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1035
1036 int s = splnet();
1037
1038 if(activate == 0)
1039 {
1040 /* deactivation */
1041 chan->state = HSCX_IDLE;
1042 avma1pp_hscx_init(sc, h_chan, activate);
1043 }
1044
1045 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
1046 device_xname(&sc->sc_dev), h_chan, activate ? "activate" : "deactivate");
1047
1048 /* general part */
1049
1050 chan->channel = h_chan; /* B channel */
1051 chan->bprot = bprot; /* B channel protocol */
1052 chan->state = HSCX_IDLE; /* B channel state */
1053
1054 /* receiver part */
1055
1056 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1057
1058 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1059
1060 chan->rxcount = 0; /* reset rx counter */
1061
1062 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1063
1064 chan->in_mbuf = NULL; /* reset mbuf ptr */
1065 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1066 chan->in_len = 0; /* reset mbuf data len */
1067
1068 /* transmitter part */
1069
1070 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1071
1072 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1073
1074 chan->txcount = 0; /* reset tx counter */
1075
1076 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1077
1078 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1079 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1080 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1081 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1082
1083 if(activate != 0)
1084 {
1085 /* activation */
1086 avma1pp_hscx_init(sc, h_chan, activate);
1087 chan->state |= HSCX_AVMA1PP_ACTIVE;
1088 }
1089
1090 splx(s);
1091 }
1092
1093 static void
1094 avma1pp_bchannel_start(isdn_layer1token t, int h_chan)
1095 {
1096 struct isic_softc *sc = (struct isic_softc*)t;
1097 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1098 int s;
1099 int activity = -1;
1100
1101 s = splnet(); /* enter critical section */
1102 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1103 {
1104 splx(s);
1105 return; /* yes, leave */
1106 }
1107
1108 /* get next mbuf from queue */
1109
1110 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1111
1112 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1113 {
1114 splx(s); /* leave critical section */
1115 return; /* yes, exit */
1116 }
1117
1118 /* init current mbuf values */
1119
1120 chan->out_mbuf_cur = chan->out_mbuf_head;
1121 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1122 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1123
1124 /* activity indicator for timeout handling */
1125
1126 if(chan->bprot == BPROT_NONE)
1127 {
1128 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1129 activity = ACT_TX;
1130 }
1131 else
1132 {
1133 activity = ACT_TX;
1134 }
1135
1136 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1137
1138 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1139 {
1140 struct i4b_trace_hdr hdr;
1141 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1142 hdr.dir = FROM_TE;
1143 hdr.count = ++sc->sc_trace_bcount;
1144 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1145 }
1146
1147 isic_hscx_fifo(chan, sc);
1148
1149 /* call timeout handling routine */
1150
1151 if(activity == ACT_RX || activity == ACT_TX)
1152 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
1153
1154 splx(s);
1155 }
1156
1157 /*---------------------------------------------------------------------------*
1158 * return the address of isic drivers linktab
1159 *---------------------------------------------------------------------------*/
1160 static isdn_link_t *
1161 avma1pp_ret_linktab(void *token, int channel)
1162 {
1163 struct l2_softc *l2sc = token;
1164 struct isic_softc *sc = l2sc->l1_token;
1165
1166 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1167
1168 return(&chan->isdn_linktab);
1169 }
1170
1171 /*---------------------------------------------------------------------------*
1172 * set the driver linktab in the b channel softc
1173 *---------------------------------------------------------------------------*/
1174 static void
1175 avma1pp_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc)
1176 {
1177 struct l2_softc *l2sc = token;
1178 struct isic_softc *sc = l2sc->l1_token;
1179 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1180
1181 chan->l4_driver = l4_driver;
1182 chan->l4_driver_softc = l4_driver_softc;
1183 }
1184
1185 static const struct isdn_l4_bchannel_functions
1186 avma1pp_l4_bchannel_functions = {
1187 avma1pp_bchannel_setup,
1188 avma1pp_bchannel_start,
1189 avma1pp_bchannel_stat
1190 };
1191
1192 /*---------------------------------------------------------------------------*
1193 * initialize our local linktab
1194 *---------------------------------------------------------------------------*/
1195 static void
1196 avma1pp_init_linktab(struct isic_softc *sc)
1197 {
1198 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1199 isdn_link_t *lt = &chan->isdn_linktab;
1200
1201 /* local setup */
1202 lt->l1token = sc;
1203 lt->channel = HSCX_CH_A;
1204 lt->bchannel_driver = &avma1pp_l4_bchannel_functions;
1205 lt->tx_queue = &chan->tx_queue;
1206
1207 /* used by non-HDLC data transfers, i.e. telephony drivers */
1208 lt->rx_queue = &chan->rx_queue;
1209
1210 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1211 lt->rx_mbuf = &chan->in_mbuf;
1212
1213 chan = &sc->sc_chan[HSCX_CH_B];
1214 lt = &chan->isdn_linktab;
1215
1216 lt->l1token = sc;
1217 lt->channel = HSCX_CH_B;
1218 lt->bchannel_driver = &avma1pp_l4_bchannel_functions;
1219 lt->tx_queue = &chan->tx_queue;
1220
1221 /* used by non-HDLC data transfers, i.e. telephony drivers */
1222 lt->rx_queue = &chan->rx_queue;
1223
1224 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1225 lt->rx_mbuf = &chan->in_mbuf;
1226 }
1227
1228 /*
1229 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1230 */
1231 static void
1232 avma1pp_bchannel_stat(isdn_layer1token t, int h_chan, bchan_statistics_t *bsp)
1233 {
1234 struct isic_softc *sc = (struct isic_softc*)t;
1235 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1236 int s;
1237
1238 s = splnet();
1239
1240 bsp->outbytes = chan->txcount;
1241 bsp->inbytes = chan->rxcount;
1242
1243 chan->txcount = 0;
1244 chan->rxcount = 0;
1245
1246 splx(s);
1247 }
1248
1249 /*---------------------------------------------------------------------------*
1250 * fill HSCX fifo with data from the current mbuf
1251 * Put this here until it can go into i4b_hscx.c
1252 *---------------------------------------------------------------------------*/
1253 static int
1254 isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc)
1255 {
1256 int len;
1257 int nextlen;
1258 int i;
1259 int cmd;
1260 /* using a scratch buffer simplifies writing to the FIFO */
1261 u_char scrbuf[HSCX_FIFO_LEN];
1262
1263 len = 0;
1264 cmd = 0;
1265
1266 /*
1267 * fill the HSCX tx fifo with data from the current mbuf. if
1268 * current mbuf holds less data than HSCX fifo length, try to
1269 * get the next mbuf from (a possible) mbuf chain. if there is
1270 * not enough data in a single mbuf or in a chain, then this
1271 * is the last mbuf and we tell the HSCX that it has to send
1272 * CRC and closing flag
1273 */
1274
1275 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1276 {
1277 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1278
1279 #ifdef NOTDEF
1280 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1281 chan->out_mbuf_head,
1282 chan->out_mbuf_cur,
1283 chan->out_mbuf_cur_ptr,
1284 chan->out_mbuf_cur_len,
1285 len,
1286 nextlen);
1287 #endif
1288
1289 cmd |= HSCX_CMDR_XTF;
1290 /* collect the data in the scratch buffer */
1291 for (i = 0; i < nextlen; i++)
1292 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1293
1294 len += nextlen;
1295 chan->txcount += nextlen;
1296
1297 chan->out_mbuf_cur_ptr += nextlen;
1298 chan->out_mbuf_cur_len -= nextlen;
1299
1300 if(chan->out_mbuf_cur_len == 0)
1301 {
1302 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1303 {
1304 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1305 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1306
1307 if(sc->sc_trace & TRACE_B_TX)
1308 {
1309 struct i4b_trace_hdr hdr;
1310 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1311 hdr.dir = FROM_TE;
1312 hdr.count = ++sc->sc_trace_bcount;
1313 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1314 }
1315 }
1316 else
1317 {
1318 if (chan->bprot != BPROT_NONE)
1319 cmd |= HSCX_CMDR_XME;
1320 i4b_Bfreembuf(chan->out_mbuf_head);
1321 chan->out_mbuf_head = NULL;
1322 }
1323 }
1324 }
1325 /* write what we have from the scratch buf to the HSCX fifo */
1326 if (len != 0)
1327 HSCX_WRFIFO(chan->channel, scrbuf, len);
1328 return(cmd);
1329 }
NetBSD on the FriendlyARM MINI2440