sys/dev/pci/n8/common/n8_driver_main.h

   1 /*-
   2  * Copyright (C) 2001-2003 by NBMK Encryption Technologies.
   3  * All rights reserved.
   4  *
   5  * NBMK Encryption Technologies provides no support of any kind for
   6  * this software.  Questions or concerns about it may be addressed to
   7  * the members of the relevant open-source community at
   8  * <tech-crypto@netbsd.org>.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are
  12  * met:
  13  *
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  *
  17  * 2. Redistributions in binary form must reproduce the above
  18  *    copyright notice, this list of conditions and the following
  19  *    disclaimer in the documentation and/or other materials provided
  20  *    with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /*****************************************************************************
  36  * @(#) n8_driver_main.h 1.27@(#)
  37  *****************************************************************************/
  38
  39 /*****************************************************************************/
  40 /** @file n8_driver_main.h
  41  *  @brief NSP2000 Device Driver main common header
  42  *
  43  * This file contains all data structures, constants, and prototypes used by
  44  * the NSP2000 Device Driver.
  45  *
  46  *****************************************************************************/
  47
  48 /*****************************************************************************
  49  * Revision history:
  50  * 02/12/04 bac   Fixed time-related defines to be more clear.
  51  * 04/21/03 brr   Move several non-configuration constants here from
  52  *                n8_driver_parms.h.
  53  * 03/19/03 brr   Added statistics to better track IRS's.
  54  * 02/20/03 brr   Eliminated all references to shared memory.
  55  * 11/25/02 brr   Move multiply defined constants to this on file. Also
  56  *                reformat to conform to coding standards.
  57  * 10/10/02 brr   Eliminate eventWaitType.
  58  * 06/25/02 brr   Moved SKS constants here from n8_driver_parms.h.
  59  * 05/30/02 brr   Keep statistics for bus errors.
  60  * 05/20/02 brr   Revert to a single AMBA wait queue.
  61  * 05/02/02 brr   Moved SKS semaphore here from queue struture.
  62  * 03/19/02 msz   Shadow memory is now called shared memory.
  63  * 02/25/02 brr   Removed references to qmgrData.
  64  * 02/15/02 brr   Removed obsolete FPGA defines, added context memory support.
  65  * 01/15/02 msz   Support of an array of AMBA wait blocks.
  66  * 11/26/01 mmd   Added N8_PCIDEVICES_t type and PCIinfo field to NspInstance_t.
  67  *                Pruned some no-longer used fields. Renamed from simon_drv.h.
  68  * 11/15/01 mmd   Eliminated memory struct field.
  69  * 11/14/01 mmd   Moved all magic numbers to n8_driver_parms.h.
  70  * 11/10/01 brr   Modified to support static allocations of persistant data
  71  *                by the driver.
  72  * 11/06/01 mmd   Added FPGA_Type and FPGA_CrystalType fields to
  73  *                SimonInstance_t.
  74  * 10/11/01 mmd   Added programmed field to SimonInstance_t.
  75  * 09/25/01 mmd   Added SKSSize, ContextMemSize, HardwareVersion, and
  76  *                RevisionID to SimonInstance_t, and changed field name from
  77  *                FPGA to IsFPGA.
  78  * 09/24/01 mmd   Added AMBAblock, AMBAbitmask, and AMBAirqstatus to
  79  *                SimonInstance_t.
  80  * 09/20/01 mmd   Removed pid field from SimonInstance_t.
  81  * 09/13/01 mmd   Added FPGAsessionID and FPGAlocked to the SimonInstance_t
  82  *                structure, for FPGA lock safeguarding.
  83  * 09/12/01 mmd   Moved declaration of NSPDeviceTable_g, NSPcount_g, and
  84  *                N8_FPGA_g to driverglobals.h.
  85  * 09/10/01 mmd   Moved declaration of global resources to this header.
  86  * 09/07/01 mmd   Added DEF_PSEUDO_DEVICE to implement the pseudo device.
  87  * 08/21/01 mmd   Added new fields to SimonInstance_t (coretype, FPGALock).
  88  * 08/16/01 mmd   Removed inclusion of n8_types.h..
  89  * 07/27/01 brr   Added PLX & LCR macros.
  90  * 06/17/01 mmd   Further cleanup and debugging.
  91  * 05/29/01 mmd   Incorporated suggestions from code review.
  92  * 05/17/01 mmd   Original version.
  93  ****************************************************************************/
  94
  95 #ifndef N8_DRIVER_MAIN_H
  96 #define N8_DRIVER_MAIN_H
  97
  98
  99 #include "helper.h"
 100 #include "n8_device_info.h"
 101 #include "n8_driver_parms.h"
 102 #include "contextMem.h"
 103
 104 /* Time-related macros */
 105 #define N8_USECS_PER_SEC    1000000
 106 #define N8_USECS_PER_MSEC   1000
 107 #define N8_USECS_PER_TICK   (N8_USECS_PER_SEC/HZ)
 108 #define N8_MINIMUM_YIELD_USECS (10 * N8_USECS_PER_MSEC)
 109
 110 /*****************************************************************************
 111  * HARDWARE IDENTIFICATION -                                                 *
 112  * PCI devices are identified with unique vendor/device ID's. Also, here are *
 113  * some memory resource parameters for FPGAs, since they don't indicate the  *
 114  * correct needed amount of address space for operation.                     *
 115  *****************************************************************************/
 116
 117 #define DEF_ASIC_VENDOR_ID             0x170b
 118 #define DEF_ASIC_DEVICE_ID             0x0100
 119 #define DEF_ASIC_PCI_MEMORY_SIZE_2     (16384 * 4)    /* 64K          */
 120
 121 #define N8_DEF_SKS_MEMSIZE         512
 122 #define N8_SKS_PROM_SIZE          4096
 123
 124 #define N8_EA_CMD_BLK_SIZE          128
 125 #define N8_PKE_CMD_BLK_SIZE          32
 126 #define N8_RNG_CMD_BLK_SIZE           8
 127
 128
 129 #define N8_MAX_CMD_QUE_EXP           15
 130 #define N8_MIN_CMD_QUE_EXP            4
 131
 132 #define N8_DEF_RNG_QUE_SIZE       (1<<N8_DEF_RNG_QUE_EXP)
 133
 134 /* The following two values are inSilicon PCI test registers that need  */
 135 /* to be set to the PCI standards rather than their defaults.           */
 136 #define INSILICON_PCI_TRDY_TIMEOUT      0x40
 137 #define INSILICON_PCI_RETRY_TIMEOUT     0x41
 138
 139 /**************************************************************************
 140  * DEVICE INFORMATION STRUCTURES -                                        *
 141  *                                                                        *
 142  * The NSPDeviceTable_g is an array of structures, one per hardware       *
 143  * instance, that retain assorted information about each instance. The    *
 144  * minor number of any request indexes into this array. NSPcount_g        *
 145  * maintains the number of detected NSP2000 hardware instances.           *
 146  **************************************************************************/
 147
 148 typedef struct
 149 {
 150    unsigned long   base_address [6];
 151    unsigned long   base_range   [6];
 152    unsigned short  vendor_id;
 153    unsigned short  device_id;
 154    unsigned char   revision_id;
 155    unsigned char   irq;
 156 } N8_PCIDEVICES_t;
 157
 158 /* Device instance information structure */
 159 typedef struct
 160 {
 161    void                   *dev;              /* nsp2000_softsc_t *        */
 162    wait_queue_head_t       RNHblock;         /* Wait queue for RNH IRQ's  */
 163    wait_queue_head_t       CCHblock;         /* Wait queue for CCH IRQ's  */
 164    wait_queue_head_t       PKHblock;         /* Wait queue for PKH IRQ's  */
 165    wait_queue_head_t       AMBAblock;        /* Wait queue for AMBA IRQ's */
 166
 167    unsigned long           RNHbitmask;       /* RNH IRQ bitmask           */
 168    unsigned long           CCHbitmask;       /* CCH IRQ bitmask           */
 169    unsigned long           PKHbitmask;       /* PKH IRQ bitmask           */
 170    unsigned long           AMBAbitmask;      /* AMBA IRQ bitmask          */
 171
 172    unsigned long           RNHirqstatus;     /* RNH control/status @ IRQ  */
 173    unsigned long           CCHirqstatus;     /* CCH control/status @ IRQ  */
 174    unsigned long           PKHirqstatus;     /* PKH control/status @ IRQ  */
 175    unsigned long           AMBAirqstatus;    /* AMBA control/status @ IRQ */
 176
 177    int                     RNHbuserrors;     /* Counter for bus errors    */
 178    int                     PKHbuserrors;     /* Counter for bus errors    */
 179    int                     CCHbuserrors;     /* Counter for bus errors    */
 180    int                     RNHcmderrors;     /* Counter for RNH errors    */
 181    int                     PKHcmderrors;     /* Counter for PKH errors    */
 182    int                     CCHcmderrors;     /* Counter for CCH errors    */
 183
 184    N8_PCIDEVICES_t         PCIinfo;          /* PCI config info per inst  */
 185
 186    unsigned long           contextMemSize;   /* Size of context memory (bytes) */
 187    unsigned long           contextMemEntries;/* Size of context memory (entries) */
 188    unsigned long           contextMemNext;   /* Index to begin search for */
 189                                              /* next allocation.          */
 190    ContextMemoryMap_t     *contextMemMap_p;  /* pointer to context memory */
 191                                              /* allocation map.           */
 192    ATOMICLOCK_t            contextMemSem;    /* Mutual exclusion semaphore*/
 193
 194 /********************************************************************************/
 195    unsigned short          HardwareVersion;  /* PCI Device ID                 */
 196    unsigned char           RevisionID;       /* PCI Revision ID               */
 197    unsigned char           chip;             /* Number or this chip           */
 198    void                   *RNqueue_p;        /* Pointer to RN queue           */
 199    unsigned long           RNqueue_size;     /* Size of RN queue in bytes     */
 200    unsigned long           RNqueue_base;     /* Phys. base addr. of RN queue  */
 201    void                   *PKqueue_p;        /* Pointer to PK queue           */
 202    unsigned long           PKqueue_size;     /* Size of PK queue in bytes     */
 203    unsigned long           PKqueue_base;     /* Phys. base addr. of PK queue  */
 204    void                   *EAqueue_p;        /* Pointer to EA queue           */
 205    unsigned long           EAqueue_size;     /* Size of EA queue in bytes     */
 206    unsigned long           EAqueue_base;     /* Phys. base addr. of EA queue  */
 207    char                    SKS_map[N8_DEF_SKS_MEMSIZE]; /* SKS allocation map */
 208    unsigned long           SKS_size;         /* Size of SKS in bytes          */
 209    ATOMICLOCK_t            SKSSem;           /* resource lock for SKS map     */
 210    void                   *RNGparms_p;       /* Pointer to RNG parm struct    */
 211    unsigned long           RNGparms_size;    /* Size of RNG parm struct (byte)*/
 212    unsigned long           RNGparms_base;    /* Phys. base addr. of RNG parms */
 213    unsigned long          *NSPregs_p;        /* NSP register mapping          */
 214    unsigned long           NSPregs_base;     /* Phys. base addr. of NSP regs  */
 215    uint16_t                EAreadIndex;      /* EA read index                 */
 216    uint16_t                PKreadIndex;      /* PK read index                 */
 217    N8_Hardware_t           hardwareType;     /* Device type for this chip     */
 218
 219 } NspInstance_t;
 220
 221
 222
 223 #endif    /* N8_DRIVER_MAIN_H */
 224
 225
 226