sys/dev/pci/pciide_cmd_reg.h

   1 /*      $NetBSD: pciide_cmd_reg.h,v 1.16 2007/12/25 18:33:41 perry Exp $        */
   2
   3 /*
   4  * Copyright (c) 1998 Manuel Bouyer.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  */
  27
  28 /*
  29  * Registers definitions for CMD Technologies's PCI 064x IDE controllers.
  30  * Available from http://www.cmd.com/
  31  */
  32
  33 /* Interesting revision of the 0646 */
  34 #define CMD0646U2_REV 0x05
  35 #define CMD0646U_REV 0x03
  36
  37 /* Configuration (RO) */
  38 #define CMD_CONF 0x50
  39 #define CMD_CONF_REV_MASK       0x03 /* 0640/3/6 only */
  40 #define CMD_CONF_DRV0_INTR      0x04
  41 #define CMD_CONF_DEVID          0x18 /* 0640/3/6 only */
  42 #define CMD_CONF_VESAPRT        0x20 /* 0640/3/6 only */
  43 #define CMD_CONF_DSA1           0x40
  44 #define CMD_CONF_DSA0           0x80 /* 0640/3/6 only */
  45
  46 /* Control register (RW) */
  47 #define CMD_CTRL 0x51
  48 #define CMD_CTRL_HR_FIFO                0x01 /* 0640/3/6 only */
  49 #define CMD_CTRL_HW_FIFO                0x02 /* 0640/3/6 only */
  50 #define CMD_CTRL_DEVSEL                 0x04
  51 #define CMD_CTRL_2PORT                  0x08
  52 #define CMD_CTRL_PAR                    0x10 /* 0640/3/6 only */
  53 #define CMD_CTRL_HW_HLD                 0x20 /* 0640/3/6 only */
  54 #define CMD_CTRL_DRV0_RAHEAD            0x40
  55 #define CMD_CTRL_DRV1_RAHEAD            0x80
  56
  57 /*
  58  * data read/write timing registers . 0640 uses the same for drive 0 and 1
  59  * on the secondary channel
  60  */
  61 #define CMD_DATA_TIM(chan, drive) \
  62         (((chan) == 0) ? \
  63                 ((drive) == 0) ? 0x54: 0x56 \
  64                 : \
  65                 ((drive) == 0) ? 0x58 : 0x5b)
  66
  67 /* secondary channel status and addr timings */
  68 #define CMD_ARTTIM23    0x57
  69 #define CMD_ARTTIM23_IRQ        0x10
  70 #define CMD_ARTTIM23_RHAEAD(d)  ((0x4) << (d))
  71
  72 /* DMA master read mode select */
  73 #define CMD_DMA_MODE 0x71
  74 #define CMD_DMA_MASK            0x03
  75 #define CMD_DMA                 0x00
  76 #define CMD_DMA_MULTIPLE        0x01
  77 #define CMD_DMA_LINE            0x03
  78 /* the followings bits are only for 0646U/646U2/648/649 */
  79 #define CMD_DMA_IRQ(chan)       (0x4 << (chan))
  80 #define CMD_DMA_IRQ_DIS(chan)   (0x10 << (chan))
  81 #define CMD_DMA_RST             0x40
  82
  83 /* the followings are only for 0646U/646U2/648/649 */
  84 /* busmaster control/status register */
  85 #define CMD_BICSR       0x79
  86 #define CMD_BICSR_80(chan)      (0x01 << (chan))
  87 /* Ultra/DMA timings reg */
  88 #define CMD_UDMATIM(channel)    (0x73 + (8 * (channel)))
  89 #define CMD_UDMATIM_UDMA(drive) (0x01 << (drive))
  90 #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
  91 #define CMD_UDMATIM_TIM_MASK    0x3
  92 #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
  93 static const int8_t cmd0646_9_tim_udma[] __unused =
  94     {0x03, 0x02, 0x01, 0x02, 0x01, 0x00};
  95
  96 /*
  97  * timings values for the 0643/6/8/9
  98  * for all dma_mode we have to have
  99  * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
 100  */
 101 static const int8_t cmd0643_9_data_tim_pio[] __unused =
 102     {0xA9, 0x57, 0x44, 0x32, 0x3F};
 103 static const int8_t cmd0643_9_data_tim_dma[] __unused =
 104     {0x87, 0x32, 0x3F};