sys/dev/pci/pciidevar.h

   1 /*      $NetBSD: pciidevar.h,v 1.39 2009/10/05 20:03:47 dyoung Exp $    */
   2
   3 /*
   4  * Copyright (c) 1998 Christopher G. Demetriou.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Christopher G. Demetriou
  17  *      for the NetBSD Project.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _DEV_PCI_PCIIDEVAR_H_
  34 #define _DEV_PCI_PCIIDEVAR_H_
  35
  36 /*
  37  * PCI IDE driver exported software structures.
  38  *
  39  * Author: Christopher G. Demetriou, March 2, 1998.
  40  */
  41
  42 #include <dev/ata/atavar.h>
  43 #include <dev/ic/wdcreg.h>
  44 #include <dev/ic/wdcvar.h>
  45 #include <sys/device_if.h>
  46 #include "opt_pciide.h"
  47
  48 /* options passed via the 'flags' config keyword */
  49 #define PCIIDE_OPTIONS_DMA      0x01
  50 #define PCIIDE_OPTIONS_NODMA    0x02
  51
  52 #ifndef ATADEBUG
  53 #define ATADEBUG
  54 #endif
  55
  56 #define DEBUG_DMA   0x01
  57 #define DEBUG_XFERS  0x02
  58 #define DEBUG_FUNCS  0x08
  59 #define DEBUG_PROBE  0x10
  60 #ifdef ATADEBUG
  61 extern int atadebug_pciide_mask;
  62 #define ATADEBUG_PRINT(args, level) \
  63         if (atadebug_pciide_mask & (level)) printf args
  64 #else
  65 #define ATADEBUG_PRINT(args, level)
  66 #endif
  67
  68 /*
  69  * While standard PCI IDE controllers only have 2 channels, it is
  70  * common for PCI SATA controllers to have more.  Here we define
  71  * the maximum number of channels that any one PCI IDE device can
  72  * have.
  73  */
  74 #define PCIIDE_MAX_CHANNELS     4
  75
  76 struct pciide_softc {
  77         struct wdc_softc        sc_wdcdev;      /* common wdc definitions */
  78         pci_chipset_tag_t       sc_pc;          /* PCI registers info */
  79         pcitag_t                sc_tag;
  80         void                    *sc_pci_ih;     /* PCI interrupt handle */
  81 #if NATA_DMA
  82         int                     sc_dma_ok;      /* bus-master DMA info */
  83         /*
  84          * sc_dma_ioh may only be used to allocate the dma_iohs
  85          * array in the channels (see below), or by chip-dependent
  86          * code that knows what it's doing, as the registers may
  87          * be laid out differently. All code in pciide_common.c
  88          * must use the channel->dma_iohs array.
  89          */
  90         bus_space_tag_t         sc_dma_iot;
  91         bus_space_handle_t      sc_dma_ioh;
  92         bus_dma_tag_t           sc_dmat;
  93
  94         /*
  95          * Some controllers might have DMA restrictions other than
  96          * the norm.
  97          */
  98         bus_size_t              sc_dma_maxsegsz;
  99         bus_size_t              sc_dma_boundary;
 100
 101         /* For VIA/AMD/nVidia */
 102         bus_addr_t sc_apo_regbase;
 103
 104         /* For Cypress */
 105         const struct cy82c693_handle *sc_cy_handle;
 106         int sc_cy_compatchan;
 107
 108         /* for SiS */
 109         u_int8_t sis_type;
 110
 111         /*
 112          * For Silicon Image SATALink, Serverworks SATA, Artisea SATA
 113          * and Promise SATA
 114          */
 115         bus_space_tag_t sc_ba5_st;
 116         bus_space_handle_t sc_ba5_sh;
 117         int sc_ba5_en;
 118 #endif  /* NATA_DMA */
 119
 120         /* Vendor info (for interpreting Chip description) */
 121         pcireg_t sc_pci_id;
 122         /* Chip description */
 123         const struct pciide_product_desc *sc_pp;
 124         /* common definitions */
 125         struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS];
 126         /* internal bookkeeping */
 127         struct pciide_channel {                 /* per-channel data */
 128                 struct ata_channel ata_channel; /* generic part */
 129                 const char      *name;
 130                 int             compat; /* is it compat? */
 131                 void            *ih;    /* compat or pci handle */
 132                 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
 133 #if NATA_DMA
 134                 /* DMA tables and DMA map for xfer, for each drive */
 135                 struct pciide_dma_maps {
 136                         bus_dmamap_t    dmamap_table;
 137                         struct idedma_table *dma_table;
 138                         bus_dmamap_t    dmamap_xfer;
 139                         int dma_flags;
 140                 } dma_maps[2];
 141                 bus_space_handle_t      dma_iohs[IDEDMA_NREGS];
 142                 /*
 143                  * Some controllers require certain bits to
 144                  * always be set for proper operation of the
 145                  * controller.  Set those bits here, if they're
 146                  * required.
 147                  */
 148                 uint8_t         idedma_cmd;
 149 #endif  /* NATA_DMA */
 150         } pciide_channels[PCIIDE_MAX_CHANNELS];
 151
 152         pcireg_t                sc_pm_reg[4];
 153 };
 154
 155 /* Given an ata_channel, get the pciide_softc. */
 156 #define CHAN_TO_PCIIDE(chp)     ((struct pciide_softc *) (chp)->ch_atac)
 157
 158 /* Given an ata_channel, get the pciide_channel. */
 159 #define CHAN_TO_PCHAN(chp)      ((struct pciide_channel *) (chp))
 160
 161 struct pciide_product_desc {
 162         u_int32_t ide_product;
 163         int ide_flags;
 164         const char *ide_name;
 165         /* map and setup chip, probe drives */
 166         void (*chip_map)(struct pciide_softc*, struct pci_attach_args*);
 167 #if 0
 168         void (*chip_unmap)(struct pciide_softc *);
 169 #endif
 170 };
 171
 172 /* Flags for ide_flags */
 173 #define IDE_16BIT_IOSPACE       0x0002 /* I/O space BARS ignore upper word */
 174
 175
 176 /* inlines for reading/writing 8-bit PCI registers */
 177 static inline u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, int);
 178 static inline void pciide_pci_write(pci_chipset_tag_t, pcitag_t,
 179                                            int, u_int8_t);
 180
 181 static inline u_int8_t
 182 pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
 183 {
 184
 185         return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
 186             ((reg & 0x03) * 8) & 0xff);
 187 }
 188
 189 static inline void
 190 pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)
 191 {
 192         pcireg_t pcival;
 193
 194         pcival = pci_conf_read(pc, pa, (reg & ~0x03));
 195         pcival &= ~(0xff << ((reg & 0x03) * 8));
 196         pcival |= (val << ((reg & 0x03) * 8));
 197         pci_conf_write(pc, pa, (reg & ~0x03), pcival);
 198 }
 199
 200 void default_chip_map(struct pciide_softc*, struct pci_attach_args*);
 201 void sata_setup_channel(struct ata_channel*);
 202
 203 void pciide_channel_dma_setup(struct pciide_channel *);
 204 int  pciide_dma_table_setup(struct pciide_softc*, int, int);
 205 int  pciide_dma_dmamap_setup(struct pciide_softc *, int, int,
 206                                 void *, size_t, int);
 207 int  pciide_dma_init(void*, int, int, void *, size_t, int);
 208 void pciide_dma_start(void*, int, int);
 209 int  pciide_dma_finish(void*, int, int, int);
 210 void pciide_irqack(struct ata_channel *);
 211
 212 /*
 213  * Functions defined by machine-dependent code.
 214  */
 215
 216 /* Attach compat interrupt handler, returning handle or NULL if failed. */
 217 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
 218 void    *pciide_machdep_compat_intr_establish(device_t,
 219             struct pci_attach_args *, int, int (*)(void *), void *);
 220 #endif
 221
 222 const struct pciide_product_desc* pciide_lookup_product
 223         (u_int32_t, const struct pciide_product_desc *);
 224 void    pciide_common_attach(struct pciide_softc *, struct pci_attach_args *,
 225                 const struct pciide_product_desc *);
 226
 227 int     pciide_chipen(struct pciide_softc *, struct pci_attach_args *);
 228 void    pciide_mapregs_compat(struct pci_attach_args *,
 229             struct pciide_channel *, int, bus_size_t *, bus_size_t*);
 230 void    pciide_mapregs_native(struct pci_attach_args *,
 231             struct pciide_channel *, bus_size_t *, bus_size_t *,
 232             int (*pci_intr)(void *));
 233 void    pciide_mapreg_dma(struct pciide_softc *,
 234             struct pci_attach_args *);
 235 int     pciide_chansetup(struct pciide_softc *, int, pcireg_t);
 236 void    pciide_mapchan(struct pci_attach_args *,
 237             struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *,
 238             int (*pci_intr)(void *));
 239 void    pciide_map_compat_intr(struct pci_attach_args *,
 240             struct pciide_channel *, int);
 241 int     pciide_compat_intr(void *);
 242 int     pciide_pci_intr(void *);
 243
 244 #endif /* _DEV_PCI_PCIIDEVAR_H_ */