sys/dev/pci/piixpmreg.h

   1 /* $NetBSD: piixpmreg.h,v 1.3 2006/06/22 16:49:01 jmcneill Exp $ */
   2 /*      $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $      */
   3
   4 /*
   5  * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
   6  *
   7  * Permission to use, copy, modify, and distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef _DEV_PCI_PIIXREG_H_
  21 #define _DEV_PCI_PIIXREG_H_
  22
  23 /*
  24  * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions.
  25  */
  26
  27 /*
  28  * Power management registers.
  29  */
  30
  31 /* PCI configuration registers */
  32 #define PIIX_PM_BASE    0x40            /* Power management base address */
  33 #define PIIX_DEVACTA    0x54            /* Device activity A (function 3) */
  34 #define PIIX_DEVACTB    0x58            /* Device activity B (function 3) */
  35 #define PIIX_PMREGMISC  0x80            /* Misc. Power management */
  36 #define PIIX_SMB_BASE   0x90            /* SMBus base address */
  37 #define PIIX_SMB_HOSTC  0xd0            /* SMBus host configuration */
  38 #define PIIX_SMB_HOSTC_HSTEN    (1 << 16)       /* enable host controller */
  39 #define PIIX_SMB_HOSTC_SMI      (0 << 17)       /* SMI */
  40 #define PIIX_SMB_HOSTC_IRQ      (4 << 17)       /* IRQ */
  41 #define PIIX_SMB_HOSTC_INTMASK  (7 << 17)
  42
  43 /* SMBus I/O registers */
  44 #define PIIX_SMB_HS     0x00            /* host status */
  45 #define PIIX_SMB_HS_BUSY        (1 << 0)        /* running a command */
  46 #define PIIX_SMB_HS_INTR        (1 << 1)        /* command completed */
  47 #define PIIX_SMB_HS_DEVERR      (1 << 2)        /* command error */
  48 #define PIIX_SMB_HS_BUSERR      (1 << 3)        /* transaction collision */
  49 #define PIIX_SMB_HS_FAILED      (1 << 4)        /* failed bus transaction */
  50 #define PIIX_SMB_HS_BITS        "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
  51 #define PIIX_SMB_HC     0x02            /* host control */
  52 #define PIIX_SMB_HC_INTREN      (1 << 0)        /* enable interrupts */
  53 #define PIIX_SMB_HC_KILL        (1 << 1)        /* kill current transaction */
  54 #define PIIX_SMB_HC_CMD_QUICK   (0 << 2)        /* QUICK command */
  55 #define PIIX_SMB_HC_CMD_BYTE    (1 << 2)        /* BYTE command */
  56 #define PIIX_SMB_HC_CMD_BDATA   (2 << 2)        /* BYTE DATA command */
  57 #define PIIX_SMB_HC_CMD_WDATA   (3 << 2)        /* WORD DATA command */
  58 #define PIIX_SMB_HC_CMD_BLOCK   (5 << 2)        /* BLOCK command */
  59 #define PIIX_SMB_HC_START       (1 << 6)        /* start transaction */
  60 #define PIIX_SMB_HCMD   0x03            /* host command */
  61 #define PIIX_SMB_TXSLVA 0x04            /* transmit slave address */
  62 #define PIIX_SMB_TXSLVA_READ    (1 << 0)        /* read direction */
  63 #define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
  64 #define PIIX_SMB_HD0    0x05            /* host data 0 */
  65 #define PIIX_SMB_HD1    0x06            /* host data 1 */
  66 #define PIIX_SMB_HBDB   0x07            /* host block data byte */
  67 #define PIIX_SMB_SC     0x08            /* slave control */
  68 #define PIIX_SMB_SC_ALERTEN     (1 << 3)        /* enable SMBALERT# */
  69
  70 /* Power management I/O registers */
  71 #define PIIX_PM_PMTMR   0x08            /* power management timer */
  72
  73 /* Misc */
  74 #define PIIX_PM_SIZE    0x38            /* Power management I/O space size */
  75 #define PIIX_SMB_SIZE   0x10            /* SMBus I/O space size */
  76
  77 #endif  /* !_DEV_PCI_PIIXREG_H_ */