sys/dev/pci/r128fbreg.h

   1 /*      $NetBSD: chipsfb.c,v 1.12 2007/08/19 15:57:24 he Exp $  */
   2
   3 /*
   4  * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
   5  *                      Precision Insight, Inc., Cedar Park, Texas, and
   6  *                      VA Linux Systems Inc., Fremont, California.
   7  *
   8  * All Rights Reserved.
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining
  11  * a copy of this software and associated documentation files (the
  12  * "Software"), to deal in the Software without restriction, including
  13  * without limitation on the rights to use, copy, modify, merge,
  14  * publish, distribute, sublicense, and/or sell copies of the Software,
  15  * and to permit persons to whom the Software is furnished to do so,
  16  * subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the
  19  * next paragraph) shall be included in all copies or substantial
  20  * portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
  26  * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  27  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  28  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  29  * OTHER DEALINGS IN THE SOFTWARE.
  30  */
  31
  32 /*
  33  * Authors:
  34  *   Rickard E. Faith <faith@valinux.com>
  35  *   Kevin E. Martin <martin@valinux.com>
  36  *   Gareth Hughes <gareth@valinux.com>
  37  *
  38  * References:
  39  *
  40  *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
  41  *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
  42  *   1999.
  43  *
  44  *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
  45  *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
  46  *
  47  */
  48
  49 /*
  50  * register definitions for ATI Rage 128 graphics controllers
  51  * mostly from XFree86's ati driver
  52  */
  53
  54
  55 #ifndef R128FB_REG_H
  56 #define R128FB_REG_H
  57
  58 #define R128_PALETTE_DATA                 0x00b4
  59 #define R128_PALETTE_INDEX                0x00b0
  60
  61 #define R128_PC_NGUI_CTLSTAT              0x0184
  62 #       define R128_PC_FLUSH_GUI          (3 << 0)
  63 #       define R128_PC_RI_GUI             (1 << 2)
  64 #       define R128_PC_FLUSH_ALL          0x00ff
  65 #       define R128_PC_BUSY               (1 << 31)
  66
  67 #define R128_CRTC_OFFSET                  0x0224
  68
  69 #define R128_DST_OFFSET                   0x1404
  70 #define R128_DST_PITCH                    0x1408
  71
  72 #define R128_DP_GUI_MASTER_CNTL           0x146c
  73 #       define R128_GMC_SRC_PITCH_OFFSET_CNTL (1    <<  0)
  74 #       define R128_GMC_DST_PITCH_OFFSET_CNTL (1    <<  1)
  75 #       define R128_GMC_SRC_CLIPPING          (1    <<  2)
  76 #       define R128_GMC_DST_CLIPPING          (1    <<  3)
  77 #       define R128_GMC_BRUSH_DATATYPE_MASK   (0x0f <<  4)
  78 #       define R128_GMC_BRUSH_8X8_MONO_FG_BG  (0    <<  4)
  79 #       define R128_GMC_BRUSH_8X8_MONO_FG_LA  (1    <<  4)
  80 #       define R128_GMC_BRUSH_1X8_MONO_FG_BG  (4    <<  4)
  81 #       define R128_GMC_BRUSH_1X8_MONO_FG_LA  (5    <<  4)
  82 #       define R128_GMC_BRUSH_32x1_MONO_FG_BG (6    <<  4)
  83 #       define R128_GMC_BRUSH_32x1_MONO_FG_LA (7    <<  4)
  84 #       define R128_GMC_BRUSH_32x32_MONO_FG_BG (8    <<  4)
  85 #       define R128_GMC_BRUSH_32x32_MONO_FG_LA (9    <<  4)
  86 #       define R128_GMC_BRUSH_8x8_COLOR       (10   <<  4)
  87 #       define R128_GMC_BRUSH_1X8_COLOR       (12   <<  4)
  88 #       define R128_GMC_BRUSH_SOLID_COLOR     (13   <<  4)
  89 #       define R128_GMC_BRUSH_NONE            (15   <<  4)
  90 #       define R128_GMC_DST_8BPP_CI           (2    <<  8)
  91 #       define R128_GMC_DST_15BPP             (3    <<  8)
  92 #       define R128_GMC_DST_16BPP             (4    <<  8)
  93 #       define R128_GMC_DST_24BPP             (5    <<  8)
  94 #       define R128_GMC_DST_32BPP             (6    <<  8)
  95 #       define R128_GMC_DST_8BPP_RGB          (7    <<  8)
  96 #       define R128_GMC_DST_Y8                (8    <<  8)
  97 #       define R128_GMC_DST_RGB8              (9    <<  8)
  98 #       define R128_GMC_DST_VYUY              (11   <<  8)
  99 #       define R128_GMC_DST_YVYU              (12   <<  8)
 100 #       define R128_GMC_DST_AYUV444           (14   <<  8)
 101 #       define R128_GMC_DST_ARGB4444          (15   <<  8)
 102 #       define R128_GMC_DST_DATATYPE_MASK     (0x0f <<  8)
 103 #       define R128_GMC_DST_DATATYPE_SHIFT    8
 104 #       define R128_GMC_SRC_DATATYPE_MASK       (3    << 12)
 105 #       define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)
 106 #       define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1    << 12)
 107 #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
 108 #       define R128_GMC_BYTE_PIX_ORDER        (1    << 14)
 109 #       define R128_GMC_BYTE_MSB_TO_LSB       (0    << 14)
 110 #       define R128_GMC_BYTE_LSB_TO_MSB       (1    << 14)
 111 #       define R128_GMC_CONVERSION_TEMP       (1    << 15)
 112 #       define R128_GMC_CONVERSION_TEMP_6500  (0    << 15)
 113 #       define R128_GMC_CONVERSION_TEMP_9300  (1    << 15)
 114 #       define R128_GMC_ROP3_MASK             (0xff << 16)
 115 #       define R128_DP_SRC_SOURCE_MASK        (7    << 24)
 116 #       define R128_DP_SRC_SOURCE_MEMORY      (2    << 24)
 117 #       define R128_DP_SRC_SOURCE_HOST_DATA   (3    << 24)
 118 #       define R128_GMC_3D_FCN_EN             (1    << 27)
 119 #       define R128_GMC_CLR_CMP_CNTL_DIS      (1    << 28)
 120 #       define R128_GMC_AUX_CLIP_DIS          (1    << 29)
 121 #       define R128_GMC_WR_MSK_DIS            (1    << 30)
 122 #       define R128_GMC_LD_BRUSH_Y_X          (1    << 31)
 123 #       define R128_ROP3_ZERO             0x00000000
 124 #       define R128_ROP3_DSa              0x00880000
 125 #       define R128_ROP3_SDna             0x00440000
 126 #       define R128_ROP3_S                0x00cc0000
 127 #       define R128_ROP3_DSna             0x00220000
 128 #       define R128_ROP3_D                0x00aa0000
 129 #       define R128_ROP3_DSx              0x00660000
 130 #       define R128_ROP3_DSo              0x00ee0000
 131 #       define R128_ROP3_DSon             0x00110000
 132 #       define R128_ROP3_DSxn             0x00990000
 133 #       define R128_ROP3_Dn               0x00550000
 134 #       define R128_ROP3_SDno             0x00dd0000
 135 #       define R128_ROP3_Sn               0x00330000
 136 #       define R128_ROP3_DSno             0x00bb0000
 137 #       define R128_ROP3_DSan             0x00770000
 138 #       define R128_ROP3_ONE              0x00ff0000
 139 #       define R128_ROP3_DPa              0x00a00000
 140 #       define R128_ROP3_PDna             0x00500000
 141 #       define R128_ROP3_P                0x00f00000
 142 #       define R128_ROP3_DPna             0x000a0000
 143 #       define R128_ROP3_D                0x00aa0000
 144 #       define R128_ROP3_DPx              0x005a0000
 145 #       define R128_ROP3_DPo              0x00fa0000
 146 #       define R128_ROP3_DPon             0x00050000
 147 #       define R128_ROP3_PDxn             0x00a50000
 148 #       define R128_ROP3_PDno             0x00f50000
 149 #       define R128_ROP3_Pn               0x000f0000
 150 #       define R128_ROP3_DPno             0x00af0000
 151 #       define R128_ROP3_DPan             0x005f0000
 152
 153 #define R128_DP_BRUSH_BKGD_CLR            0x1478
 154 #define R128_DP_BRUSH_FRGD_CLR            0x147c
 155 #define R128_SRC_X_Y                      0x1590
 156 #define R128_DST_X_Y                      0x1594
 157 #define R128_DST_WIDTH_HEIGHT             0x1598
 158
 159 #define R128_SRC_OFFSET                   0x15ac
 160 #define R128_SRC_PITCH                    0x15b0
 161
 162 #define R128_AUX_SC_CNTL                  0x1660
 163 #       define R128_AUX1_SC_EN            (1 << 0)
 164 #       define R128_AUX1_SC_MODE_OR       (0 << 1)
 165 #       define R128_AUX1_SC_MODE_NAND     (1 << 1)
 166 #       define R128_AUX2_SC_EN            (1 << 2)
 167 #       define R128_AUX2_SC_MODE_OR       (0 << 3)
 168 #       define R128_AUX2_SC_MODE_NAND     (1 << 3)
 169 #       define R128_AUX3_SC_EN            (1 << 4)
 170 #       define R128_AUX3_SC_MODE_OR       (0 << 5)
 171 #       define R128_AUX3_SC_MODE_NAND     (1 << 5)
 172
 173 #define R128_DP_CNTL                      0x16c0
 174 #       define R128_DST_X_LEFT_TO_RIGHT   (1 <<  0)
 175 #       define R128_DST_Y_TOP_TO_BOTTOM   (1 <<  1)
 176
 177 #define R128_DP_DATATYPE                  0x16c4
 178 #       define R128_HOST_BIG_ENDIAN_EN    (1 << 29)
 179
 180 #define R128_DP_WRITE_MASK                0x16cc
 181
 182 #define R128_DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0
 183 #       define R128_DST_Y_MAJOR             (1 <<  2)
 184 #       define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
 185 #       define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
 186
 187 #define R128_DEFAULT_OFFSET               0x16e0
 188 #define R128_DEFAULT_PITCH                0x16e4
 189 #define R128_DEFAULT_SC_BOTTOM_RIGHT      0x16e8
 190 #       define R128_DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)
 191 #       define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
 192
 193 #define R128_SC_TOP_LEFT                  0x16ec
 194 #define R128_SC_BOTTOM_RIGHT              0x16f0
 195
 196 #define R128_GUI_STAT                     0x1740
 197 #       define R128_GUI_FIFOCNT_MASK      0x0fff
 198 #       define R128_GUI_ACTIVE            (1 << 31)
 199
 200 #endif /* R128FB_REG_H */