sys/dev/pci/radeonfbvar.h

   1 /* $NetBSD: radeonfbvar.h,v 1.6 2007/08/03 05:40:47 macallan Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2006 Itronix Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Garrett D'Amore for Itronix Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of Itronix Inc. may not be used to endorse
  18  *    or promote products derived from this software without specific
  19  *    prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
  36  * does not endorse, this software.  ATI will not be responsible or liable
  37  * for any actual or alleged damage or loss caused by or in connection with
  38  * the use of or reliance on this software.
  39  */
  40
  41 #ifndef _DEV_PCI_RADEONFBVAR_H
  42 #define _DEV_PCI_RADEONFBVAR_H
  43
  44 #include "opt_splash.h"
  45
  46 #include <sys/param.h>
  47 #include <sys/types.h>
  48 #include <sys/device.h>
  49 #include <sys/callout.h>
  50 #include <dev/pci/pcivar.h>
  51 #include <dev/wscons/wsdisplayvar.h>
  52 #include <dev/wscons/wsconsio.h>
  53 #include <dev/wsfont/wsfont.h>
  54 #include <dev/rasops/rasops.h>
  55 #include <dev/wscons/wsdisplay_vconsvar.h>
  56 #include <dev/videomode/videomode.h>
  57 #include <dev/videomode/edidvar.h>
  58 #ifdef SPLASHSCREEN
  59 #include <dev/splash/splash.h>
  60 #endif
  61 #include <dev/i2c/i2cvar.h>
  62
  63 /* XXX: change this when we complete the support for multi HEAD */
  64 #define RADEON_NDISPLAYS        (1)
  65 #define RADEON_MAXX             (2048)
  66 #define RADEON_MAXY             (1536)
  67 #define RADEON_MAXBPP           (32)
  68 #define RADEON_STRIDEALIGN      (64)
  69 #define RADEON_CURSORMAXX       (64)
  70 #define RADEON_CURSORMAXY       (64)
  71 #define RADEON_PANINCREMENT     (1)
  72
  73 struct radeonfb_softc;
  74
  75 struct radeonfb_port {
  76         int                     rp_number;
  77         int                     rp_mon_type;
  78         int                     rp_conn_type;
  79         int                     rp_dac_type;
  80         int                     rp_ddc_type;
  81         int                     rp_tmds_type;
  82         int                     rp_edid_valid;
  83         struct edid_info        rp_edid;
  84 };
  85
  86 /* connector values used by legacy bios */
  87 #define RADEON_CONN_NONE        0
  88 #define RADEON_CONN_PROPRIETARY 1       /* think LVDS ribbon cable */
  89 #define RADEON_CONN_CRT         2
  90 #define RADEON_CONN_DVI_I       3
  91 #define RADEON_CONN_DVI_D       4
  92 #define RADEON_CONN_CTV         5
  93 #define RADEON_CONN_STV         6
  94 #define RADEON_CONN_UNSUPPORTED 7
  95
  96 /* connector values used by atom bios */
  97 #define ATOM_CONN_NONE          0
  98 #define ATOM_CONN_VGA           1
  99 #define ATOM_CONN_DVI_I         2
 100 #define ATOM_CONN_DVI_D         3
 101 #define ATOM_CONN_DVI_A         4
 102 #define ATOM_CONN_STV           5
 103 #define ATOM_CONN_CTV           6
 104 #define ATOM_CONN_LVDS          7
 105 #define ATOM_CONN_DIGITAL       8
 106 #define ATOM_CONN_UNSUPPORTED   9
 107
 108 #define RADEON_DDC_NONE         0
 109 #define RADEON_DDC_MONID        1
 110 #define RADEON_DDC_DVI          2
 111 #define RADEON_DDC_VGA          3
 112 #define RADEON_DDC_CRT2         4
 113
 114 #define RADEON_DAC_UNKNOWN      -1
 115 #define RADEON_DAC_PRIMARY      0
 116 #define RADEON_DAC_TVDAC        1
 117
 118 #define RADEON_TMDS_UNKNOWN     -1
 119 #define RADEON_TMDS_INT         0
 120 #define RADEON_TMDS_EXT         1
 121
 122 #define RADEON_MT_UNKNOWN       -1
 123 #define RADEON_MT_NONE          0
 124 #define RADEON_MT_CRT           1
 125 #define RADEON_MT_LCD           2       /* LVDS */
 126 #define RADEON_MT_DFP           3       /* TMDS */
 127 #define RADEON_MT_CTV           4
 128 #define RADEON_MT_STV           5
 129
 130 struct radeonfb_i2c {
 131         struct radeonfb_softc   *ric_softc;
 132         int                     ric_register;
 133         struct i2c_controller   ric_controller;
 134 };
 135
 136 struct radeonfb_crtc {
 137         int                     rc_number;
 138         struct videomode        rc_videomode;
 139         uint16_t                rc_xoffset;
 140         uint16_t                rc_yoffset;
 141
 142         struct radeonfb_port    *rc_port;
 143 };
 144
 145 struct radeonfb_cursor {
 146         int                     rc_visible;
 147         struct wsdisplay_curpos rc_pos;
 148         struct wsdisplay_curpos rc_hot;
 149         struct wsdisplay_curpos rc_size;
 150         uint32_t                rc_cmap[2];
 151         uint8_t                 rc_image[512];  /* 64x64x1 bit */
 152         uint8_t                 rc_mask[512];   /* 64x64x1 bit */
 153 };
 154
 155 struct radeonfb_display {
 156         struct radeonfb_softc   *rd_softc;
 157         int                     rd_number;      /* 0 .. RADEON_NDISPLAYS */
 158
 159         bus_size_t              rd_offset;      /* offset within FB memory */
 160         vaddr_t                 rd_fbptr;       /* framebuffer pointer */
 161         vaddr_t                 rd_curptr;      /* cursor data pointer */
 162         size_t                  rd_curoff;      /* cursor offset */
 163
 164         uint16_t                rd_bpp;
 165         uint16_t                rd_virtx;
 166         uint16_t                rd_virty;
 167         uint16_t                rd_stride;
 168         uint16_t                rd_format;      /* chip pixel format */
 169
 170         uint16_t                rd_xoffset;
 171         uint16_t                rd_yoffset;
 172
 173         int                     rd_bg;          /* background */
 174         bool                    rd_console;
 175
 176         struct callout          rd_bl_lvds_co;  /* delayed lvds operation */
 177         uint32_t                rd_bl_lvds_val; /* value of delayed lvds */
 178
 179         int                     rd_wsmode;
 180
 181         int                     rd_ncrtcs;
 182         struct radeonfb_crtc    rd_crtcs[2];
 183
 184         struct radeonfb_cursor  rd_cursor;
 185         /* XXX: this should probaby be an array for CRTCs */
 186         //struct videomode      rd_videomode;
 187
 188         struct wsscreen_list    rd_wsscreenlist;
 189         struct wsscreen_descr   rd_wsscreens_storage[1];
 190         struct wsscreen_descr   *rd_wsscreens;
 191         struct vcons_screen     rd_vscreen;
 192         struct vcons_data       rd_vd;
 193
 194
 195 #if 0
 196         uint8_t                 rd_cmap_red[256];
 197         uint8_t                 rd_cmap_green[256];
 198         uint8_t                 rd_cmap_blue[256];
 199 #endif
 200
 201 #ifdef SPLASHSCREEN
 202         struct splash_info      rd_splash;
 203 #endif
 204
 205 #ifdef SPLASHSCREEN_PROGRESS
 206         struct splash_progress  rd_progress;
 207 #endif
 208 };
 209
 210 struct radeon_tmds_pll {
 211         uint32_t                rtp_freq;
 212         uint32_t                rtp_pll;
 213 };
 214
 215 struct radeonfb_softc {
 216         struct device           sc_dev;
 217         uint16_t                sc_family;
 218         uint16_t                sc_flags;
 219         pcireg_t                sc_id;
 220
 221         char                    sc_devinfo[256];
 222
 223         bus_space_tag_t         sc_regt;
 224         bus_space_handle_t      sc_regh;
 225         bus_size_t              sc_regsz;
 226         bus_addr_t              sc_regaddr;
 227
 228         bus_space_tag_t         sc_memt;
 229         bus_space_handle_t      sc_memh;
 230         bus_size_t              sc_memsz;
 231         bus_addr_t              sc_memaddr;
 232
 233         bus_space_tag_t         sc_iot;
 234         bus_space_handle_t      sc_ioh;
 235         bus_size_t              sc_iosz;
 236         bus_addr_t              sc_ioaddr;
 237
 238         /* size of a single display */
 239         int                     sc_maxx;
 240         int                     sc_maxy;
 241         int                     sc_maxbpp;
 242         int                     sc_fboffset;
 243         int                     sc_fbsize;
 244
 245         bus_space_tag_t         sc_romt;
 246         bus_space_handle_t      sc_romh;
 247         bus_size_t              sc_romsz;
 248         bus_addr_t              sc_romaddr;
 249         bus_space_handle_t      sc_biosh;
 250
 251         bus_dma_tag_t           sc_dmat;
 252
 253         uint16_t                sc_refclk;
 254         uint16_t                sc_refdiv;
 255         uint32_t                sc_minpll;
 256         uint32_t                sc_maxpll;
 257
 258         pci_chipset_tag_t       sc_pc;
 259         pcitag_t                sc_pt;
 260
 261         /* card's idea of addresses, internally */
 262         uint32_t                sc_aperbase;
 263
 264         int                     sc_ndisplays;
 265         struct radeonfb_display sc_displays[RADEON_NDISPLAYS];
 266
 267         int                     sc_nports;
 268         struct radeonfb_port    sc_ports[2];
 269
 270         struct radeon_tmds_pll  sc_tmds_pll[4];
 271
 272         struct radeonfb_i2c     sc_i2c[4];
 273
 274         uint8_t                 *sc_bios;
 275         bus_size_t              sc_biossz;
 276
 277         char                    sc_modebuf[64];
 278         const char              *sc_defaultmode;
 279 };
 280
 281 /* chip families */
 282 #define RADEON_R100     1
 283 #define RADEON_RV100    2
 284 #define RADEON_RS100    3
 285 #define RADEON_RV200    4
 286 #define RADEON_RS200    5
 287 #define RADEON_R200     6
 288 #define RADEON_RV250    7
 289 #define RADEON_RS300    8
 290 #define RADEON_RV280    9
 291 #define RADEON_R300     10
 292 #define RADEON_R350     11
 293 #define RADEON_RV350    12
 294 #define RADEON_RV380    13
 295 #define RADEON_R420     14
 296 #define RADEON_FAMILIES 15
 297
 298 /* feature flags */
 299 #define RFB_MOB         (1 << 0)        /* Mobility */
 300 #define RFB_NCRTC2      (1 << 1)        /* No CRTC2 */
 301 #define RFB_IGP         (1 << 2)
 302 #define RFB_R300CG      (1 << 3)
 303 #define RFB_SDAC        (1 << 4)        /* Single DAC */
 304 #define RFB_R300        (1 << 5)        /* R300 variants -- newer parts */
 305 #define RFB_RV100       (1 << 6)        /* RV100 variants -- previous gen */
 306 #define RFB_ATOM        (1 << 7)        /* ATOM bios */
 307 #define RFB_INV_BLIGHT  (1 << 8)        /* backlight level inverted */
 308
 309 #define IS_MOBILITY(sc) ((sc)->sc_flags & RFB_MOB)
 310 #define HAS_CRTC2(sc)   (((sc)->sc_flags & RFB_NCRTC2) == 0)
 311
 312 #define IS_R300(sc)     ((sc)->sc_flags & RFB_R300)
 313 #define HAS_R300CG(sc)  ((sc)->sc_flags & RFB_R300CG)
 314 #define HAS_SDAC(sc)    ((sc)->sc_flags & RFB_SDAC)
 315 #define IS_RV100(sc)    ((sc)->sc_flags & RFB_RV100)
 316 #define IS_IGP(sc)      ((sc)->sc_flags & RFB_IGP)
 317 #define IS_ATOM(sc)     ((sc)->sc_flags & RFB_ATOM)
 318
 319 #define RADEON_TIMEOUT  2000000
 320
 321 #define GET32(sc, r)    radeonfb_get32(sc, r)
 322 #define PUT32(sc, r, v) radeonfb_put32(sc, r, v)
 323 #define SET32(sc, r, v) PUT32(sc, r, GET32(sc, r) | (v))
 324 #define CLR32(sc, r, v) PUT32(sc, r, GET32(sc, r) & ~(v))
 325 #define PATCH32(sc, r, v, m)    PUT32(sc, r, (GET32(sc, r) & (m)) | (v))
 326
 327
 328 #define GETPLL(sc, r)           radeonfb_getpll(sc, r)
 329 #define PUTPLL(sc, r, v)        radeonfb_putpll(sc, r, v)
 330 #define SETPLL(sc, r, v)        PUTPLL(sc, r, GETPLL(sc, r) | (v))
 331 #define CLRPLL(sc, r, v)        PUTPLL(sc, r, GETPLL(sc, r) & ~(v))
 332 #define PATCHPLL(sc, r, v, m)   PUTPLL(sc, r, (GETPLL(sc, r) & (m)) | (v))
 333
 334 #define GETROM32(sc, r) bus_space_read_4(sc->sc_romt, sc->sc_romh, r)
 335 #define GETROM16(sc, r) bus_space_read_2(sc->sc_romt, sc->sc_romh, r)
 336 #define GETROM8(sc, r)  bus_space_read_1(sc->sc_romt, sc->sc_romh, r)
 337
 338 /*
 339  * Some values in BIOS are misaligned...
 340  */
 341 #define GETBIOS8(sc, r)         ((sc)->sc_bios[(r)])
 342
 343 #define GETBIOS16(sc, r)        \
 344         ((GETBIOS8(sc, (r) + 1) << 8) | GETBIOS8(sc, (r)))
 345
 346 #define GETBIOS32(sc, r)        \
 347         ((GETBIOS16(sc, (r) + 2) << 16) | GETBIOS16(sc, (r)))
 348
 349 #define XNAME(sc)       device_xname(&sc->sc_dev)
 350
 351 #define DIVIDE(x,y)     (((x) + (y / 2)) / (y))
 352
 353 uint32_t radeonfb_get32(struct radeonfb_softc *, uint32_t);
 354 void radeonfb_put32(struct radeonfb_softc *, uint32_t, uint32_t);
 355 void radeonfb_mask32(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t);
 356
 357 uint32_t radeonfb_getindex(struct radeonfb_softc *, uint32_t);
 358 void radeonfb_putindex(struct radeonfb_softc *, uint32_t, uint32_t);
 359 void radeonfb_maskindex(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t);
 360
 361 uint32_t radeonfb_getpll(struct radeonfb_softc *, uint32_t);
 362 void radeonfb_putpll(struct radeonfb_softc *, uint32_t, uint32_t);
 363 void radeonfb_maskpll(struct radeonfb_softc *, uint32_t, uint32_t, uint32_t);
 364
 365 #ifdef  RADEON_BIOS_INIT
 366 int     radeonfb_bios_init(struct radeonfb_softc *);
 367 #endif
 368
 369 void    radeonfb_i2c_init(struct radeonfb_softc *);
 370 int     radeonfb_i2c_read_edid(struct radeonfb_softc *, int, uint8_t *);
 371
 372 #endif  /* _DEV_PCI_RADEONFBVAR_H */