sys/dev/pci/ubsecvar.h

   1 /*      $NetBSD: ubsecvar.h,v 1.2 2005/12/11 12:22:51 christos Exp $    */
   2 /*      $OpenBSD: ubsecvar.h,v 1.36 2003/06/04 16:02:41 jason Exp $     */
   3
   4 /*
   5  * Copyright (c) 2000 Theo de Raadt
   6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Effort sponsored in part by the Defense Advanced Research Projects
  30  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  31  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  32  *
  33  */
  34
  35 /* Maximum queue length */
  36 #ifndef UBS_MAX_NQUEUE
  37 #define UBS_MAX_NQUEUE          60
  38 #endif
  39
  40 #define UBS_MAX_SCATTER         64      /* Maximum scatter/gather depth */
  41
  42 #ifndef UBS_MAX_AGGR
  43 #define UBS_MAX_AGGR            5       /* Maximum aggregation count */
  44 #endif
  45
  46 #define UBSEC_CARD(sid)         (((sid) & 0xf0000000) >> 28)
  47 #define UBSEC_SESSION(sid)      ( (sid) & 0x0fffffff)
  48 #define UBSEC_SID(crd, sesn)    (((crd) << 28) | ((sesn) & 0x0fffffff))
  49
  50 #define UBS_DEF_RTY             0xff    /* PCI Retry Timeout */
  51 #define UBS_DEF_TOUT            0xff    /* PCI TRDY Timeout */
  52 #define UBS_DEF_CACHELINE       0x01    /* Cache Line setting */
  53
  54 struct ubsec_dma_alloc {
  55         u_int32_t               dma_paddr;
  56         void *                  dma_vaddr;
  57         bus_dmamap_t            dma_map;
  58         bus_dma_segment_t       dma_seg;
  59         bus_size_t              dma_size;
  60         int                     dma_nseg;
  61 };
  62
  63 struct ubsec_q2 {
  64         SIMPLEQ_ENTRY(ubsec_q2)         q_next;
  65         struct ubsec_dma_alloc          q_mcr;
  66         struct ubsec_dma_alloc          q_ctx;
  67         u_int                           q_type;
  68 };
  69
  70 struct ubsec_q2_rng {
  71         struct ubsec_q2                 rng_q;
  72         struct ubsec_dma_alloc          rng_buf;
  73         int                             rng_used;
  74 };
  75
  76 /* C = (M ^ E) mod N */
  77 #define UBS_MODEXP_PAR_M        0
  78 #define UBS_MODEXP_PAR_E        1
  79 #define UBS_MODEXP_PAR_N        2
  80 struct ubsec_q2_modexp {
  81         struct ubsec_q2                 me_q;
  82         struct cryptkop *               me_krp;
  83         struct ubsec_dma_alloc          me_M;
  84         struct ubsec_dma_alloc          me_E;
  85         struct ubsec_dma_alloc          me_C;
  86         struct ubsec_dma_alloc          me_epb;
  87         int                             me_modbits;
  88         int                             me_shiftbits;
  89         int                             me_normbits;
  90 };
  91
  92 #define UBS_RSAPRIV_PAR_P       0
  93 #define UBS_RSAPRIV_PAR_Q       1
  94 #define UBS_RSAPRIV_PAR_DP      2
  95 #define UBS_RSAPRIV_PAR_DQ      3
  96 #define UBS_RSAPRIV_PAR_PINV    4
  97 #define UBS_RSAPRIV_PAR_MSGIN   5
  98 #define UBS_RSAPRIV_PAR_MSGOUT  6
  99 struct ubsec_q2_rsapriv {
 100         struct ubsec_q2                 rpr_q;
 101         struct cryptkop *               rpr_krp;
 102         struct ubsec_dma_alloc          rpr_msgin;
 103         struct ubsec_dma_alloc          rpr_msgout;
 104 };
 105
 106 #define UBSEC_RNG_BUFSIZ        16              /* measured in 32bit words */
 107
 108 struct ubsec_dmachunk {
 109         struct ubsec_mcr        d_mcr;
 110         struct ubsec_mcr_add    d_mcradd[UBS_MAX_AGGR-1];
 111         struct ubsec_pktbuf     d_sbuf[UBS_MAX_SCATTER-1];
 112         struct ubsec_pktbuf     d_dbuf[UBS_MAX_SCATTER-1];
 113         u_int32_t               d_macbuf[5];
 114         union {
 115                 struct ubsec_pktctx_long        ctxl;
 116                 struct ubsec_pktctx             ctx;
 117         } d_ctx;
 118 };
 119
 120 struct ubsec_dma {
 121         SIMPLEQ_ENTRY(ubsec_dma)        d_next;
 122         struct ubsec_dmachunk           *d_dma;
 123         struct ubsec_dma_alloc          d_alloc;
 124 };
 125
 126 #define UBS_FLAGS_KEY           0x01            /* has key accelerator */
 127 #define UBS_FLAGS_LONGCTX       0x02            /* uses long ipsec ctx */
 128 #define UBS_FLAGS_BIGKEY        0x04            /* 2048bit keys */
 129 #define UBS_FLAGS_HWNORM        0x08            /* hardware normalization */
 130 #define UBS_FLAGS_RNG           0x10            /* hardware rng */
 131
 132 struct ubsec_q {
 133         SIMPLEQ_ENTRY(ubsec_q)          q_next;
 134         int                             q_nstacked_mcrs;
 135         struct ubsec_q                  *q_stacked_mcr[UBS_MAX_AGGR-1];
 136         struct cryptop                  *q_crp;
 137         struct ubsec_dma                *q_dma;
 138
 139         struct mbuf                     *q_src_m, *q_dst_m;
 140         struct uio                      *q_src_io, *q_dst_io;
 141
 142         bus_dmamap_t                    q_src_map;
 143         bus_dmamap_t                    q_dst_map;
 144
 145         int                             q_sesn;
 146         int                             q_flags;
 147 };
 148
 149 struct ubsec_softc {
 150         struct  device          sc_dv;          /* generic device */
 151         void                    *sc_ih;         /* interrupt handler cookie */
 152         bus_space_handle_t      sc_sh;          /* memory handle */
 153         bus_space_tag_t         sc_st;          /* memory tag */
 154         bus_dma_tag_t           sc_dmat;        /* dma tag */
 155         int                     sc_flags;       /* device specific flags */
 156         int                     sc_suspended;
 157         int                     sc_needwakeup;  /* notify crypto layer */
 158         u_int32_t               sc_statmask;    /* interrupt status mask */
 159         int32_t                 sc_cid;         /* crypto tag */
 160         SIMPLEQ_HEAD(,ubsec_q)  sc_queue;       /* packet queue, mcr1 */
 161         int                     sc_nqueue;      /* count enqueued, mcr1 */
 162         SIMPLEQ_HEAD(,ubsec_q)  sc_qchip;       /* on chip, mcr1 */
 163         int                     sc_nqchip;      /* count on chip, mcr1 */
 164         SIMPLEQ_HEAD(,ubsec_q)  sc_freequeue;   /* list of free queue elements */
 165         SIMPLEQ_HEAD(,ubsec_q2) sc_queue2;      /* packet queue, mcr2 */
 166         int                     sc_nqueue2;     /* count enqueued, mcr2 */
 167         SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2;      /* on chip, mcr2 */
 168         int                     sc_nsessions;   /* # of sessions */
 169         struct ubsec_session    *sc_sessions;   /* sessions */
 170         struct callout          sc_rngto;       /* rng timeout */
 171         int                     sc_rnghz;       /* rng poll time */
 172         struct ubsec_q2_rng     sc_rng;
 173         struct ubsec_dma        sc_dmaa[UBS_MAX_NQUEUE];
 174         struct ubsec_q          *sc_queuea[UBS_MAX_NQUEUE];
 175         SIMPLEQ_HEAD(,ubsec_q2) sc_q2free;      /* free list */
 176 };
 177
 178 #define UBSEC_QFLAGS_COPYOUTIV          0x1
 179
 180 struct ubsec_session {
 181         u_int32_t       ses_used;
 182         u_int32_t       ses_deskey[6];          /* 3DES key */
 183         u_int32_t       ses_hminner[5];         /* hmac inner state */
 184         u_int32_t       ses_hmouter[5];         /* hmac outer state */
 185         u_int32_t       ses_iv[2];              /* [3]DES iv */
 186 };
 187
 188 struct ubsec_stats {
 189         u_int64_t hst_ibytes;
 190         u_int64_t hst_obytes;
 191         u_int32_t hst_ipackets;
 192         u_int32_t hst_opackets;
 193         u_int32_t hst_invalid;          /* invalid argument */
 194         u_int32_t hst_badsession;       /* invalid session id */
 195         u_int32_t hst_badflags;         /* flags indicate !(mbuf | uio) */
 196         u_int32_t hst_nodesc;           /* op submitted w/o descriptors */
 197         u_int32_t hst_badalg;           /* unsupported algorithm */
 198
 199         u_int32_t hst_nomem;
 200         u_int32_t hst_queuefull;
 201         u_int32_t hst_dmaerr;
 202         u_int32_t hst_mcrerr;
 203         u_int32_t hst_nodmafree;
 204
 205         u_int32_t hst_lenmismatch;      /* enc/auth lengths different */
 206         u_int32_t hst_skipmismatch;     /* enc part begins before auth part */
 207         u_int32_t hst_iovmisaligned;    /* iov op not aligned */
 208         u_int32_t hst_noirq;            /* IRQ for no reason */
 209         u_int32_t hst_unaligned;        /* unaligned src caused copy */
 210         u_int32_t hst_nomap;            /* bus_dmamap_create failed */
 211         u_int32_t hst_noload;           /* bus_dmamap_load_* failed */
 212         u_int32_t hst_nombuf;           /* MGET* failed */
 213         u_int32_t hst_nomcl;            /* MCLGET* failed */
 214         u_int32_t hst_totbatch;         /* ops submitted w/o interrupt */
 215         u_int32_t hst_maxbatch;         /* max ops submitted together */
 216         u_int32_t hst_maxqueue;         /* max ops queued for submission */
 217         u_int32_t hst_maxqchip;         /* max mcr1 ops out for processing */
 218         u_int32_t hst_mcr1full;         /* MCR1 too busy to take ops */
 219         u_int32_t hst_rng;              /* RNG requests */
 220         u_int32_t hst_modexp;           /* MOD EXP requests */
 221         u_int32_t hst_modexpcrt;        /* MOD EXP CRT requests */
 222 };