sys/dev/sbus/bppreg.h

   1 /*      $NetBSD: bppreg.h,v 1.1 1998/09/21 21:20:48 pk Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Paul Kranenburg.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /* Hardware Configuration Register */
  33 #define BPP_HCR_DSS_MASK        0x003f  /* Data before strobe */
  34 #define BPP_HCR_DSS_SHFT        0       /*   (in Sbus clocks)*/
  35 #define BPP_HCR_DSW_MASK        0x7f00  /* Data Strobe Width */
  36 #define BPP_HCR_DSW_SHFT        8       /*   (in Sbus clocks)*/
  37 #define BPP_HCR_TEST            0x8000  /* */
  38 #define BPP_HCR_BITS            "\177\020" \
  39                                 "f\0\6DSS\0f\10\7DSW\0b\17TEST\0"
  40
  41
  42 /* Operation Configuration Register */
  43 #define BPP_OCR_IDLE            0x0008  /* State machines are idle */
  44 #define BPP_OCR_SRST            0x0080  /* Reset bit */
  45 #define BPP_OCR_ACK_OP          0x0100  /* ACK handshake operation */
  46 #define BPP_OCR_BUSY_OP         0x0200  /* BUSY handshake operation */
  47 #define BPP_OCR_EN_DIAG         0x0400  /* */
  48 #define BPP_OCR_ACK_DSEL        0x0800  /* ack line is bidirectional */
  49 #define BPP_OCR_BUSY_DSEL       0x1000  /* busy line is bidirectional */
  50 #define BPP_OCR_DS_DSEL         0x2000  /* data strobe line is bidirectional */
  51 #define BPP_OCR_DATA_SRC        0x4000  /* Data source for `memory clear' */
  52 #define BPP_OCR_MEM_SRC         0x8000  /* Enable `memory clear' */
  53 #define BPP_OCR_BITS            "\177\020" \
  54                                 "b\3IDLE\0b\7SRST\0b\10ACK_OP\0b\11BUSY_OP\0" \
  55                                 "b\12EN_DIAG\0b\13ACK_DSEL\0b\14BUSY_DSEL\0" \
  56                                 "b\15DS_DSEL\0b\16DATA_SRC\0b\17MEM_SRC\0"
  57 /* User settable bits */
  58 #define BPP_OCR_USER    \
  59         (BPP_OCR_ACK_OP|BPP_OCR_BUSY_OP|BPP_OCR_ACK_DSEL|\
  60          BPP_OCR_BUSY_DSEL|BPP_OCR_DS_DSEL)
  61
  62 /* Transfer Control Register */
  63 #define BPP_TCR_DS              0x01    /* Data Strobe */
  64 #define BPP_TCR_ACK             0x02    /* Acknowledge */
  65 #define BPP_TCR_BUSY            0x04    /* Busy */
  66 #define BPP_TCR_DIR             0x08    /* Direction control */
  67 #define BPP_TCR_BITS            "\177\020" \
  68                                 "b\0DS\0b\1ACK\0b\2BUSY\0b\3DIR\0"
  69 #define BPP_TCR_USER            (BPP_TCR_DS|BPP_TCR_ACK|BPP_TCR_BUSY)
  70
  71 /* Output Register */
  72 #define BPP_OR_SLCTIN           0x01    /* Select */
  73 #define BPP_OR_AFXN             0x02    /* Auto Feed */
  74 #define BPP_OR_INIT             0x04    /* Initialize */
  75 #define BPP_OR_BITS             "\177\020" \
  76                                 "b\0SLCTIN\0b\1AFXN\0b\2INIT\0"
  77 #define BPP_OR_USER             (BPP_OR_SLCTIN|BPP_OR_AFXN)
  78
  79 /* Input Register (read-only) */
  80 #define BPP_IR_ERR              0x01    /* Err input pin */
  81 #define BPP_IR_SLCT             0x02    /* Select input pin */
  82 #define BPP_IR_PE               0x04    /* Paper Out input pin */
  83 #define BPP_IR_BITS             "\177\020" \
  84                                 "b\0ERR\0b\1SLCT\0b\2PE\0"
  85
  86 /* Interrupt Control Register */
  87 #define BPP_ERR_IRQ_EN          0x0001  /* Error interrupt enable */
  88 #define BPP_ERR_IRP             0x0002  /* ERR interrupt polarity */
  89 #define BPP_SLCT_IRQ_EN         0x0004  /* Select interrupt enable */
  90 #define BPP_SLCT_IRP            0x0008  /* Select interrupt polarity */
  91 #define BPP_PE_IRQ_EN           0x0010  /* Paper Empty interrupt enable */
  92 #define BPP_PE_IRP              0x0020  /* PE interrupt polarity */
  93 #define BPP_BUSY_IRQ_EN         0x0040  /* BUSY interrupt enable */
  94 #define BPP_BUSY_IRP            0x0080  /* BUSY interrupt polarity */
  95 #define BPP_ACK_IRQ_EN          0x0100  /* ACK interrupt enable */
  96 #define BPP_DS_IRQ_EN           0x0200  /* Data Strobe interrupt enable */
  97 #define BPP_ERR_IRQ             0x0400  /* ERR interrupt pending */
  98 #define BPP_SLCT_IRQ            0x0800  /* SLCT interrupt pending */
  99 #define BPP_PE_IRQ              0x1000  /* PE interrupt pending */
 100 #define BPP_BUSY_IRQ            0x2000  /* BUSY interrupt pending */
 101 #define BPP_ACK_IRQ             0x4000  /* ACK interrupt pending */
 102 #define BPP_DS_IRQ              0x8000  /* DS interrupt pending */
 103
 104 /* Define mask for each of all irq request, all polarity and all enable bits */
 105 #define BPP_ALLIRQ      (BPP_ERR_IRQ|BPP_SLCT_IRQ|BPP_PE_IRQ|   \
 106                          BPP_BUSY_IRQ|BPP_ACK_IRQ|BPP_DS_IRQ)
 107 #define BPP_ALLEN       (BPP_ERR_IRQ_EN|BPP_SLCT_IRQ_EN|        \
 108                          BPP_PE_IRQ_EN|BPP_BUSY_IRQ_EN|         \
 109                          BPP_ACK_IRQ_EN|BPP_DS_IRQ_EN)
 110 #define BPP_ALLIRP      (BPP_ERR_IRP|BPP_PE_IRP|BPP_BUSY_IRP)
 111 #define BPP_IRQ_USER    BPP_ALLIRP
 112
 113 #define BPP_IRQ_BITS    "\177\020"                                      \
 114                         "b\0ERR_IRQ_EN\0b\1ERR_IRP\0b\2SLCT_IRQ_EN\0"   \
 115                         "b\3SLCT_IRP\0b\4PE_IRQ_EN\0b\5PE_IRP\0"        \
 116                         "b\6BUSY_IRQ_EN\0b\7BUSY_IRP\0b\10ACK_IRQ_EN\0" \
 117                         "b\11DS_IRQ_EN\0b\12ERR_IRQ\0b\13SLCT_IRQ\0"    \
 118                         "b\14PE_IRQ\0b\15BUSY_IRQ\0b\16ACK_IRQ\0"       \
 119                         "b\17DS_IRQ\0"