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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / sbus / esp_sbus.c
blobe0ebd058bb834ad3df35364de224621070655987
1 /* $NetBSD: esp_sbus.c,v 1.50 2009/09/08 18:31:36 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: esp_sbus.c,v 1.50 2009/09/08 18:31:36 tsutsui Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/device.h>
39 #include <sys/buf.h>
40 #include <sys/malloc.h>
41
42 #include <dev/scsipi/scsi_all.h>
43 #include <dev/scsipi/scsipi_all.h>
44 #include <dev/scsipi/scsiconf.h>
45 #include <dev/scsipi/scsi_message.h>
46
47 #include <sys/bus.h>
48 #include <sys/intr.h>
49 #include <machine/autoconf.h>
50
51 #include <dev/ic/lsi64854reg.h>
52 #include <dev/ic/lsi64854var.h>
53
54 #include <dev/ic/ncr53c9xreg.h>
55 #include <dev/ic/ncr53c9xvar.h>
56
57 #include <dev/sbus/sbusvar.h>
58
59 #include "opt_ddb.h"
60
61 /* #define ESP_SBUS_DEBUG */
62
63 struct esp_softc {
64 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
65
66 bus_space_tag_t sc_bustag;
67 bus_dma_tag_t sc_dmatag;
68
69 bus_space_handle_t sc_reg; /* the registers */
70 struct lsi64854_softc *sc_dma; /* pointer to my dma */
71
72 int sc_pri; /* SBUS priority */
73 };
74
75 int espmatch_sbus(device_t, cfdata_t, void *);
76 void espattach_sbus(device_t, device_t, void *);
77 void espattach_dma(device_t, device_t, void *);
78
79 static void espattach(struct esp_softc *, struct ncr53c9x_glue *);
80
81 CFATTACH_DECL_NEW(esp_sbus, sizeof(struct esp_softc),
82 espmatch_sbus, espattach_sbus, NULL, NULL);
83
84 CFATTACH_DECL_NEW(esp_dma, sizeof(struct esp_softc),
85 espmatch_sbus, espattach_dma, NULL, NULL);
86
87 /*
88 * Functions and the switch for the MI code.
89 */
90 static uint8_t esp_read_reg(struct ncr53c9x_softc *, int);
91 static void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
92 static uint8_t esp_rdreg1(struct ncr53c9x_softc *, int);
93 static void esp_wrreg1(struct ncr53c9x_softc *, int, uint8_t);
94 static int esp_dma_isintr(struct ncr53c9x_softc *);
95 static void esp_dma_reset(struct ncr53c9x_softc *);
96 static int esp_dma_intr(struct ncr53c9x_softc *);
97 static int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **,
98 size_t *, int, size_t *);
99 static void esp_dma_go(struct ncr53c9x_softc *);
100 static void esp_dma_stop(struct ncr53c9x_softc *);
101 static int esp_dma_isactive(struct ncr53c9x_softc *);
102
103 #ifdef DDB
104 static void esp_init_ddb_cmds(void);
105 #endif
106
107 static struct ncr53c9x_glue esp_sbus_glue = {
108 esp_read_reg,
109 esp_write_reg,
110 esp_dma_isintr,
111 esp_dma_reset,
112 esp_dma_intr,
113 esp_dma_setup,
114 esp_dma_go,
115 esp_dma_stop,
116 esp_dma_isactive,
117 NULL, /* gl_clear_latched_intr */
118 };
119
120 static struct ncr53c9x_glue esp_sbus_glue1 = {
121 esp_rdreg1,
122 esp_wrreg1,
123 esp_dma_isintr,
124 esp_dma_reset,
125 esp_dma_intr,
126 esp_dma_setup,
127 esp_dma_go,
128 esp_dma_stop,
129 esp_dma_isactive,
130 NULL, /* gl_clear_latched_intr */
131 };
132
133 int
134 espmatch_sbus(device_t parent, cfdata_t cf, void *aux)
135 {
136 int rv;
137 struct sbus_attach_args *sa = aux;
138
139 if (strcmp("SUNW,fas", sa->sa_name) == 0)
140 return 1;
141
142 rv = (strcmp(cf->cf_name, sa->sa_name) == 0 ||
143 strcmp("ptscII", sa->sa_name) == 0);
144 return rv;
145 }
146
147 void
148 espattach_sbus(device_t parent, device_t self, void *aux)
149 {
150 struct esp_softc *esc = device_private(self);
151 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
152 struct sbus_softc *sbsc = device_private(parent);
153 struct sbus_attach_args *sa = aux;
154 struct lsi64854_softc *lsc;
155 device_t dma_dev;
156 int burst, sbusburst;
157
158 sc->sc_dev = self;
159
160 #ifdef DDB
161 esp_init_ddb_cmds();
162 #endif
163
164 esc->sc_bustag = sa->sa_bustag;
165 esc->sc_dmatag = sa->sa_dmatag;
166
167 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7);
168 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1);
169 if (sc->sc_freq < 0)
170 sc->sc_freq = sbsc->sc_clockfreq;
171
172 #ifdef ESP_SBUS_DEBUG
173 aprint_normal("\n");
174 aprint_normal_dev(self, "%s: sc_id %d, freq %d\n",
175 __func__, sc->sc_id, sc->sc_freq);
176 aprint_normal("%s", device_xname(self));
177 #endif
178
179 if (strcmp("SUNW,fas", sa->sa_name) == 0) {
180
181 /*
182 * fas has 2 register spaces: dma(lsi64854) and
183 * SCSI core (ncr53c9x)
184 */
185 if (sa->sa_nreg != 2) {
186 aprint_error(": %d register spaces\n", sa->sa_nreg);
187 return;
188 }
189
190 /*
191 * allocate space for dma, in SUNW,fas there are no separate
192 * dma device
193 */
194 lsc = malloc(sizeof(struct lsi64854_softc), M_DEVBUF, M_NOWAIT);
195
196 if (lsc == NULL) {
197 aprint_error(": out of memory (lsi64854_softc)\n");
198 return;
199 }
200 lsc->sc_dev = malloc(sizeof(struct device), M_DEVBUF,
201 M_NOWAIT | M_ZERO);
202 if (lsc->sc_dev == NULL) {
203 aprint_error(": out of memory (device_t)\n");
204 free(lsc, M_DEVBUF);
205 return;
206 }
207 esc->sc_dma = lsc;
208
209 lsc->sc_bustag = sa->sa_bustag;
210 lsc->sc_dmatag = sa->sa_dmatag;
211
212 strlcpy(lsc->sc_dev->dv_xname, device_xname(sc->sc_dev),
213 sizeof(lsc->sc_dev->dv_xname));
214
215 /* Map dma registers */
216 if (sa->sa_npromvaddrs) {
217 sbus_promaddr_to_handle(sa->sa_bustag,
218 sa->sa_promvaddrs[0], &lsc->sc_regs);
219 } else {
220 if (sbus_bus_map(sa->sa_bustag,
221 sa->sa_reg[0].oa_space,
222 sa->sa_reg[0].oa_base,
223 sa->sa_reg[0].oa_size,
224 0, &lsc->sc_regs) != 0) {
225 aprint_error(": cannot map dma registers\n");
226 return;
227 }
228 }
229
230 /*
231 * XXX is this common(from bpp.c), the same in dma_sbus...etc.
232 *
233 * Get transfer burst size from PROM and plug it into the
234 * controller registers. This is needed on the Sun4m; do
235 * others need it too?
236 */
237 sbusburst = sbsc->sc_burst;
238 if (sbusburst == 0)
239 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
240
241 burst = prom_getpropint(sa->sa_node, "burst-sizes", -1);
242
243 #if ESP_SBUS_DEBUG
244 aprint_normal("%s: burst 0x%x, sbus 0x%x\n",
245 __func__, burst, sbusburst);
246 aprint_normal("%s", device_xname(self));
247 #endif
248
249 if (burst == -1)
250 /* take SBus burst sizes */
251 burst = sbusburst;
252
253 /* Clamp at parent's burst sizes */
254 burst &= sbusburst;
255 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 :
256 (burst & SBUS_BURST_16) ? 16 : 0;
257
258 lsc->sc_channel = L64854_CHANNEL_SCSI;
259 lsc->sc_client = sc;
260
261 lsi64854_attach(lsc);
262
263 /*
264 * map SCSI core registers
265 */
266 if (sa->sa_npromvaddrs > 1) {
267 sbus_promaddr_to_handle(sa->sa_bustag,
268 sa->sa_promvaddrs[1], &esc->sc_reg);
269 } else {
270 if (sbus_bus_map(sa->sa_bustag,
271 sa->sa_reg[1].oa_space,
272 sa->sa_reg[1].oa_base,
273 sa->sa_reg[1].oa_size,
274 0, &esc->sc_reg) != 0) {
275 aprint_error(": cannot map "
276 "scsi core registers\n");
277 return;
278 }
279 }
280
281 if (sa->sa_nintr == 0) {
282 aprint_error(": no interrupt property\n");
283 return;
284 }
285
286 esc->sc_pri = sa->sa_pri;
287
288 espattach(esc, &esp_sbus_glue);
289
290 return;
291 }
292
293 /*
294 * Find the DMA by poking around the dma device structures
295 *
296 * What happens here is that if the dma driver has not been
297 * configured, then this returns a NULL pointer. Then when the
298 * dma actually gets configured, it does the opposing test, and
299 * if the sc->sc_esp field in it's softc is NULL, then tries to
300 * find the matching esp driver.
301 */
302 dma_dev = device_find_by_driver_unit("dma", device_unit(self));
303 if (dma_dev == NULL) {
304 aprint_error(": no corresponding DMA device\n");
305 return;
306 }
307 esc->sc_dma = device_private(dma_dev);
308 esc->sc_dma->sc_client = sc;
309
310 /*
311 * The `ESC' DMA chip must be reset before we can access
312 * the esp registers.
313 */
314 if (esc->sc_dma->sc_rev == DMAREV_ESC)
315 DMA_RESET(esc->sc_dma);
316
317 /*
318 * Map my registers in, if they aren't already in virtual
319 * address space.
320 */
321 if (sa->sa_npromvaddrs) {
322 sbus_promaddr_to_handle(sa->sa_bustag,
323 sa->sa_promvaddrs[0], &esc->sc_reg);
324 } else {
325 if (sbus_bus_map(sa->sa_bustag,
326 sa->sa_slot, sa->sa_offset, sa->sa_size,
327 0, &esc->sc_reg) != 0) {
328 aprint_error(": cannot map registers\n");
329 return;
330 }
331 }
332
333 if (sa->sa_nintr == 0) {
334 /*
335 * No interrupt properties: we quit; this might
336 * happen on e.g. a Sparc X terminal.
337 */
338 aprint_error(": no interrupt property\n");
339 return;
340 }
341
342 esc->sc_pri = sa->sa_pri;
343
344 if (strcmp("ptscII", sa->sa_name) == 0) {
345 espattach(esc, &esp_sbus_glue1);
346 } else {
347 espattach(esc, &esp_sbus_glue);
348 }
349 }
350
351 void
352 espattach_dma(device_t parent, device_t self, void *aux)
353 {
354 struct esp_softc *esc = device_private(self);
355 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
356 struct sbus_attach_args *sa = aux;
357
358 if (strcmp("ptscII", sa->sa_name) == 0) {
359 return;
360 }
361
362 sc->sc_dev = self;
363
364 esc->sc_bustag = sa->sa_bustag;
365 esc->sc_dmatag = sa->sa_dmatag;
366
367 sc->sc_id = prom_getpropint(sa->sa_node, "initiator-id", 7);
368 sc->sc_freq = prom_getpropint(sa->sa_node, "clock-frequency", -1);
369
370 esc->sc_dma = device_private(parent);
371 esc->sc_dma->sc_client = sc;
372
373 /*
374 * Map my registers in, if they aren't already in virtual
375 * address space.
376 */
377 if (sa->sa_npromvaddrs) {
378 sbus_promaddr_to_handle(sa->sa_bustag,
379 sa->sa_promvaddrs[0], &esc->sc_reg);
380 } else {
381 if (sbus_bus_map(sa->sa_bustag,
382 sa->sa_slot, sa->sa_offset, sa->sa_size,
383 0, &esc->sc_reg) != 0) {
384 aprint_error(": cannot map registers\n");
385 return;
386 }
387 }
388
389 if (sa->sa_nintr == 0) {
390 /*
391 * No interrupt properties: we quit; this might
392 * happen on e.g. a Sparc X terminal.
393 */
394 aprint_error(": no interrupt property\n");
395 return;
396 }
397
398 esc->sc_pri = sa->sa_pri;
399
400 espattach(esc, &esp_sbus_glue);
401 }
402
403
404 /*
405 * Attach this instance, and then all the sub-devices
406 */
407 void
408 espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep)
409 {
410 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
411 void *icookie;
412 unsigned int uid = 0;
413
414 /*
415 * Set up glue for MI code early; we use some of it here.
416 */
417 sc->sc_glue = gluep;
418
419 /* gimme MHz */
420 sc->sc_freq /= 1000000;
421
422 /*
423 * XXX More of this should be in ncr53c9x_attach(), but
424 * XXX should we really poke around the chip that much in
425 * XXX the MI code? Think about this more...
426 */
427
428 /*
429 * It is necessary to try to load the 2nd config register here,
430 * to find out what rev the esp chip is, else the ncr53c9x_reset
431 * will not set up the defaults correctly.
432 */
433 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
434 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
435 sc->sc_cfg3 = NCRCFG3_CDB;
436 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
437
438 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
439 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
440 sc->sc_rev = NCR_VARIANT_ESP100;
441 } else {
442 sc->sc_cfg2 = NCRCFG2_SCSI2;
443 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
444 sc->sc_cfg3 = 0;
445 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
446 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
447 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
448 if (NCR_READ_REG(sc, NCR_CFG3) !=
449 (NCRCFG3_CDB | NCRCFG3_FCLK)) {
450 sc->sc_rev = NCR_VARIANT_ESP100A;
451 } else {
452 /* NCRCFG2_FE enables > 64K transfers */
453 sc->sc_cfg2 |= NCRCFG2_FE;
454 sc->sc_cfg3 = 0;
455 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
456 sc->sc_rev = NCR_VARIANT_ESP200;
457
458 /*
459 * XXX spec says it's valid after power up or
460 * chip reset
461 */
462 uid = NCR_READ_REG(sc, NCR_UID);
463 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */
464 sc->sc_rev = NCR_VARIANT_FAS366;
465 }
466 }
467
468 #ifdef ESP_SBUS_DEBUG
469 aprint_debug("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
470 aprint_normal("%s", device_xname(sc->sc_dev));
471 #endif
472
473 /*
474 * XXX minsync and maxxfer _should_ be set up in MI code,
475 * XXX but it appears to have some dependency on what sort
476 * XXX of DMA we're hooked up to, etc.
477 */
478
479 /*
480 * This is the value used to start sync negotiations
481 * Note that the NCR register "SYNCTP" is programmed
482 * in "clocks per byte", and has a minimum value of 4.
483 * The SCSI period used in negotiation is one-fourth
484 * of the time (in nanoseconds) needed to transfer one byte.
485 * Since the chip's clock is given in MHz, we have the following
486 * formula: 4 * period = (1000 / freq) * 4
487 */
488 sc->sc_minsync = 1000 / sc->sc_freq;
489
490 /*
491 * Alas, we must now modify the value a bit, because it's
492 * only valid when can switch on FASTCLK and FASTSCSI bits
493 * in config register 3...
494 */
495 switch (sc->sc_rev) {
496 case NCR_VARIANT_ESP100:
497 sc->sc_maxxfer = 64 * 1024;
498 sc->sc_minsync = 0; /* No synch on old chip? */
499 break;
500
501 case NCR_VARIANT_ESP100A:
502 sc->sc_maxxfer = 64 * 1024;
503 /* Min clocks/byte is 5 */
504 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
505 break;
506
507 case NCR_VARIANT_ESP200:
508 case NCR_VARIANT_FAS366:
509 sc->sc_maxxfer = 16 * 1024 * 1024;
510 /* XXX - do actually set FAST* bits */
511 break;
512 }
513
514 /* Establish interrupt channel */
515 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO,
516 ncr53c9x_intr, sc);
517
518 /* register interrupt stats */
519 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
520 device_xname(sc->sc_dev), "intr");
521
522 /* Turn on target selection using the `dma' method */
523 if (sc->sc_rev != NCR_VARIANT_FAS366)
524 sc->sc_features |= NCR_F_DMASELECT;
525
526 /* Do the common parts of attachment. */
527 sc->sc_adapter.adapt_minphys = minphys;
528 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
529 ncr53c9x_attach(sc);
530 }
531
532 /*
533 * Glue functions.
534 */
535
536 #ifdef ESP_SBUS_DEBUG
537 int esp_sbus_debug = 0;
538
539 static struct {
540 char *r_name;
541 int r_flag;
542 } esp__read_regnames [] = {
543 { "TCL", 0}, /* 0/00 */
544 { "TCM", 0}, /* 1/04 */
545 { "FIFO", 0}, /* 2/08 */
546 { "CMD", 0}, /* 3/0c */
547 { "STAT", 0}, /* 4/10 */
548 { "INTR", 0}, /* 5/14 */
549 { "STEP", 0}, /* 6/18 */
550 { "FFLAGS", 1}, /* 7/1c */
551 { "CFG1", 1}, /* 8/20 */
552 { "STAT2", 0}, /* 9/24 */
553 { "CFG4", 1}, /* a/28 */
554 { "CFG2", 1}, /* b/2c */
555 { "CFG3", 1}, /* c/30 */
556 { "-none", 1}, /* d/34 */
557 { "TCH", 1}, /* e/38 */
558 { "TCX", 1}, /* f/3c */
559 };
560
561 static struct {
562 char *r_name;
563 int r_flag;
564 } esp__write_regnames[] = {
565 { "TCL", 1}, /* 0/00 */
566 { "TCM", 1}, /* 1/04 */
567 { "FIFO", 0}, /* 2/08 */
568 { "CMD", 0}, /* 3/0c */
569 { "SELID", 1}, /* 4/10 */
570 { "TIMEOUT", 1}, /* 5/14 */
571 { "SYNCTP", 1}, /* 6/18 */
572 { "SYNCOFF", 1}, /* 7/1c */
573 { "CFG1", 1}, /* 8/20 */
574 { "CCF", 1}, /* 9/24 */
575 { "TEST", 1}, /* a/28 */
576 { "CFG2", 1}, /* b/2c */
577 { "CFG3", 1}, /* c/30 */
578 { "-none", 1}, /* d/34 */
579 { "TCH", 1}, /* e/38 */
580 { "TCX", 1}, /* f/3c */
581 };
582 #endif
583
584 uint8_t
585 esp_read_reg(struct ncr53c9x_softc *sc, int reg)
586 {
587 struct esp_softc *esc = (struct esp_softc *)sc;
588 uint8_t v;
589
590 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);
591 #ifdef ESP_SBUS_DEBUG
592 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)
593 printf("RD:%x <%s> %x\n", reg * 4,
594 ((unsigned int)reg < 0x10) ?
595 esp__read_regnames[reg].r_name : "<***>", v);
596 #endif
597 return v;
598 }
599
600 void
601 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
602 {
603 struct esp_softc *esc = (struct esp_softc *)sc;
604
605 #ifdef ESP_SBUS_DEBUG
606 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)
607 printf("WR:%x <%s> %x\n", reg * 4,
608 ((unsigned int)reg < 0x10) ?
609 esp__write_regnames[reg].r_name : "<***>", v);
610 #endif
611 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);
612 }
613
614 uint8_t
615 esp_rdreg1(struct ncr53c9x_softc *sc, int reg)
616 {
617 struct esp_softc *esc = (struct esp_softc *)sc;
618
619 return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg);
620 }
621
622 void
623 esp_wrreg1(struct ncr53c9x_softc *sc, int reg, uint8_t v)
624 {
625 struct esp_softc *esc = (struct esp_softc *)sc;
626
627 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v);
628 }
629
630 int
631 esp_dma_isintr(struct ncr53c9x_softc *sc)
632 {
633 struct esp_softc *esc = (struct esp_softc *)sc;
634
635 return DMA_ISINTR(esc->sc_dma);
636 }
637
638 void
639 esp_dma_reset(struct ncr53c9x_softc *sc)
640 {
641 struct esp_softc *esc = (struct esp_softc *)sc;
642
643 DMA_RESET(esc->sc_dma);
644 }
645
646 int
647 esp_dma_intr(struct ncr53c9x_softc *sc)
648 {
649 struct esp_softc *esc = (struct esp_softc *)sc;
650
651 return DMA_INTR(esc->sc_dma);
652 }
653
654 int
655 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
656 int datain, size_t *dmasize)
657 {
658 struct esp_softc *esc = (struct esp_softc *)sc;
659
660 return DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize);
661 }
662
663 void
664 esp_dma_go(struct ncr53c9x_softc *sc)
665 {
666 struct esp_softc *esc = (struct esp_softc *)sc;
667
668 DMA_GO(esc->sc_dma);
669 }
670
671 void
672 esp_dma_stop(struct ncr53c9x_softc *sc)
673 {
674 struct esp_softc *esc = (struct esp_softc *)sc;
675 uint32_t csr;
676
677 csr = L64854_GCSR(esc->sc_dma);
678 csr &= ~D_EN_DMA;
679 L64854_SCSR(esc->sc_dma, csr);
680 }
681
682 int
683 esp_dma_isactive(struct ncr53c9x_softc *sc)
684 {
685 struct esp_softc *esc = (struct esp_softc *)sc;
686
687 return DMA_ISACTIVE(esc->sc_dma);
688 }
689
690 #ifdef DDB
691 #include <machine/db_machdep.h>
692 #include <ddb/db_output.h>
693 #include <ddb/db_command.h>
694
695 void db_esp(db_expr_t, bool, db_expr_t, const char*);
696
697 const struct db_command db_esp_command_table[] = {
698 { DDB_ADD_CMD("esp", db_esp, 0,
699 "display status of all esp SCSI controllers and their devices",
700 NULL, NULL) },
701 { DDB_ADD_CMD(NULL, NULL, 0, NULL, NULL, NULL) }
702 };
703
704 static void
705 esp_init_ddb_cmds(void)
706 {
707 static int db_cmds_initialized = 0;
708
709 if (db_cmds_initialized)
710 return;
711 db_cmds_initialized = 1;
712 (void)db_register_tbl(DDB_MACH_CMD, db_esp_command_table);
713 }
714
715 void
716 db_esp(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
717 {
718 device_t dv;
719 struct ncr53c9x_softc *sc;
720 struct ncr53c9x_ecb *ecb;
721 struct ncr53c9x_linfo *li;
722 int u, t, i;
723
724 for (u = 0; u < 10; u++) {
725 dv = device_find_by_driver_unit("esp", u);
726 if (dv == NULL)
727 continue;
728 sc = device_private(dv);
729
730 db_printf("%s: nexus %p phase %x prev %x"
731 " dp %p dleft %lx ify %x\n", device_xname(dv),
732 sc->sc_nexus, sc->sc_phase, sc->sc_prevphase,
733 sc->sc_dp, sc->sc_dleft, sc->sc_msgify);
734 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n",
735 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0],
736 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3],
737 sc->sc_imess[0]);
738 db_printf("ready: ");
739 for (ecb = TAILQ_FIRST(&sc->ready_list); ecb != NULL;
740 ecb = TAILQ_NEXT(ecb, chain)) {
741 db_printf("ecb %p ", ecb);
742 if (ecb == TAILQ_NEXT(ecb, chain)) {
743 db_printf("\nWARNING: tailq loop on ecb %p",
744 ecb);
745 break;
746 }
747 }
748 db_printf("\n");
749
750 for (t = 0; t < sc->sc_ntarg; t++) {
751 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) {
752 db_printf("t%d lun %d untagged %p"
753 " busy %d used %x\n",
754 t, (int)li->lun, li->untagged, li->busy,
755 li->used);
756 for (i = 0; i < 256; i++)
757 ecb = li->queued[i];
758 if (ecb != NULL) {
759 db_printf("ecb %p tag %x\n",
760 ecb, i);
761 }
762 }
763 }
764 }
765 }
766 #endif
NetBSD on the FriendlyARM MINI2440