sys/dev/sbus/spif.c

   1 /*      $NetBSD: spif.c,v 1.24 2009/09/17 16:39:48 tsutsui Exp $        */
   2 /*      $OpenBSD: spif.c,v 1.12 2003/10/03 16:44:51 miod Exp $  */
   3
   4 /*
   5  * Copyright (c) 1999-2002 Jason L. Wright (jason@thought.net)
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  19  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  20  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  21  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  22  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  23  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  25  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  26  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  27  * POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Effort sponsored in part by the Defense Advanced Research Projects
  30  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  31  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  32  *
  33  */
  34
  35 /*
  36  * Driver for the SUNW,spif: 8 serial, 1 parallel sbus board
  37  * based heavily on Iain Hibbert's driver for the MAGMA cards
  38  */
  39
  40 /* Ported to NetBSD 2.0 by Hauke Fath */
  41
  42
  43 #include <sys/cdefs.h>
  44 __KERNEL_RCSID(0, "$NetBSD: spif.c,v 1.24 2009/09/17 16:39:48 tsutsui Exp $");
  45
  46 #include "spif.h"
  47 #if NSPIF > 0
  48
  49 #include <sys/param.h>
  50 #include <sys/systm.h>
  51 #include <sys/proc.h>
  52 #include <sys/device.h>
  53 #include <sys/file.h>
  54 #include <sys/ioctl.h>
  55 #include <sys/malloc.h>
  56 #include <sys/tty.h>
  57 #include <sys/time.h>
  58 #include <sys/kernel.h>
  59 #include <sys/syslog.h>
  60 #include <sys/conf.h>
  61 #include <sys/errno.h>
  62 #include <sys/kauth.h>
  63 #include <sys/intr.h>
  64
  65 #include <sys/bus.h>
  66 #include <machine/autoconf.h>
  67 #include <machine/promlib.h>
  68
  69 #include <dev/sbus/sbusvar.h>
  70
  71 #include <dev/sbus/spifvar.h>
  72 #include <dev/sbus/spifreg.h>
  73
  74 #include "ioconf.h"
  75
  76 /* Autoconfig stuff */
  77
  78 CFATTACH_DECL(spif, sizeof(struct spif_softc),
  79     spif_match, spif_attach, NULL, NULL);
  80
  81 CFATTACH_DECL(stty, sizeof(struct stty_softc),
  82     stty_match, stty_attach, NULL, NULL);
  83
  84 CFATTACH_DECL(sbpp, sizeof(struct sbpp_softc),
  85     sbpp_match, sbpp_attach, NULL, NULL);
  86
  87 dev_type_open(stty_open);
  88 dev_type_close(stty_close);
  89 dev_type_read(stty_read);
  90 dev_type_write(stty_write);
  91 dev_type_ioctl(stty_ioctl);
  92 dev_type_stop(stty_stop);
  93 dev_type_tty(stty_tty);
  94 dev_type_poll(stty_poll);
  95
  96 const struct cdevsw stty_cdevsw = {
  97         stty_open, stty_close, stty_read, stty_write, stty_ioctl,
  98         stty_stop, stty_tty, stty_poll, nommap, ttykqfilter, D_TTY
  99 };
 100
 101 dev_type_open(sbpp_open);
 102 dev_type_close(sbpp_close);
 103 dev_type_read(sbpp_read);
 104 dev_type_write(sbpp_write);
 105 dev_type_ioctl(sbpp_ioctl);
 106 dev_type_poll(sbpp_poll);
 107
 108 const struct cdevsw sbpp_cdevsw = {
 109         sbpp_open, sbpp_close, sbpp_read, sbpp_write, sbpp_ioctl,
 110         nostop, notty, sbpp_poll, nommap, nokqfilter, D_OTHER
 111 };
 112
 113
 114 /* normal STC access */
 115 #define STC_WRITE(sc,r,v)       \
 116     bus_space_write_1((sc)->sc_bustag, (sc)->sc_stch, (r), (v))
 117 #define STC_READ(sc,r)          \
 118     bus_space_read_1((sc)->sc_bustag, (sc)->sc_stch, (r))
 119
 120 /* IACK STC access */
 121 #define ISTC_WRITE(sc,r,v)      \
 122     bus_space_write_1((sc)->sc_bustag, (sc)->sc_istch, (r), (v))
 123 #define ISTC_READ(sc,r)         \
 124     bus_space_read_1((sc)->sc_bustag, (sc)->sc_istch, (r))
 125
 126 /* PPC access */
 127 #define PPC_WRITE(sc,r,v)       \
 128     bus_space_write_1((sc)->sc_bustag, (sc)->sc_ppch, (r), (v))
 129 #define PPC_READ(sc,r)          \
 130     bus_space_read_1((sc)->sc_bustag, (sc)->sc_ppch, (r))
 131
 132 #define DTR_WRITE(sc,port,v)                                            \
 133     do {                                                                \
 134         sc->sc_ttys->sc_port[(port)].sp_dtr = v;                        \
 135         bus_space_write_1((sc)->sc_bustag,                              \
 136             sc->sc_dtrh, port, (v == 0) ? 1 : 0);                       \
 137     } while (0)
 138
 139 #define DTR_READ(sc,port)       ((sc)->sc_ttys->sc_port[(port)].sp_dtr)
 140
 141
 142 int
 143 spif_match(device_t parent, cfdata_t vcf, void *aux)
 144 {
 145         struct sbus_attach_args *sa = aux;
 146
 147         if (strcmp(vcf->cf_name, sa->sa_name) &&
 148             strcmp("SUNW,spif", sa->sa_name))
 149                 return (0);
 150         return (1);
 151 }
 152
 153 void
 154 spif_attach(device_t parent, device_t self, void *aux)
 155 {
 156         struct spif_softc *sc = device_private(self);
 157         struct sbus_attach_args *sa = aux;
 158
 159         if (sa->sa_nintr != 2) {
 160                 printf(": expected %d interrupts, got %d\n", 2, sa->sa_nintr);
 161                 return;
 162         }
 163
 164         if (sa->sa_nreg != 1) {
 165                 printf(": expected %d registers, got %d\n", 1, sa->sa_nreg);
 166                 return;
 167         }
 168
 169         sc->sc_bustag = sa->sa_bustag;
 170         if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
 171             sa->sa_offset, sa->sa_size,
 172             0, &sc->sc_regh) != 0) {
 173                 printf(": can't map registers\n");
 174                 return;
 175         }
 176
 177         if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
 178             DTR_REG_OFFSET, DTR_REG_LEN, &sc->sc_dtrh) != 0) {
 179                 printf(": can't map dtr regs\n");
 180                 goto fail_unmapregs;
 181         }
 182
 183         if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
 184             STC_REG_OFFSET, STC_REG_LEN, &sc->sc_stch) != 0) {
 185                 printf(": can't map dtr regs\n");
 186                 goto fail_unmapregs;
 187         }
 188
 189         if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
 190             ISTC_REG_OFFSET, ISTC_REG_LEN, &sc->sc_istch) != 0) {
 191                 printf(": can't map dtr regs\n");
 192                 goto fail_unmapregs;
 193         }
 194
 195         if (bus_space_subregion(sc->sc_bustag, sc->sc_regh,
 196             PPC_REG_OFFSET, PPC_REG_LEN, &sc->sc_ppch) != 0) {
 197                 printf(": can't map dtr regs\n");
 198                 goto fail_unmapregs;
 199         }
 200
 201         sc->sc_ppcih = bus_intr_establish(sa->sa_bustag,
 202             sa->sa_intr[PARALLEL_INTR].oi_pri, IPL_SERIAL, spif_ppcintr, sc);
 203         if (sc->sc_ppcih == NULL) {
 204                 printf(": failed to establish ppc interrupt\n");
 205                 goto fail_unmapregs;
 206         }
 207
 208         sc->sc_stcih = bus_intr_establish(sa->sa_bustag,
 209             sa->sa_intr[SERIAL_INTR].oi_pri, IPL_SERIAL, spif_stcintr, sc);
 210         if (sc->sc_stcih == NULL) {
 211                 printf(": failed to establish stc interrupt\n");
 212                 goto fail_unmapregs;
 213         }
 214
 215         sc->sc_softih = softint_establish(SOFTINT_SERIAL, spif_softintr, sc);
 216         if (sc->sc_softih == NULL) {
 217                 printf(": can't get soft intr\n");
 218                 goto fail_unmapregs;
 219         }
 220
 221         sc->sc_node = sa->sa_node;
 222
 223         sc->sc_rev = prom_getpropint(sc->sc_node, "revlev", 0);
 224
 225         sc->sc_osc = prom_getpropint(sc->sc_node, "verosc", 0);
 226         switch (sc->sc_osc) {
 227         case SPIF_OSC10:
 228                 sc->sc_osc = 10000000;
 229                 break;
 230         case SPIF_OSC9:
 231         default:
 232                 sc->sc_osc = 9830400;
 233                 break;
 234         }
 235
 236         sc->sc_nser = 8;
 237         sc->sc_npar = 1;
 238
 239         sc->sc_rev2 = STC_READ(sc, STC_GFRCR);
 240         STC_WRITE(sc, STC_GSVR, 0);
 241
 242         stty_write_ccr(sc, CD180_CCR_CMD_RESET | CD180_CCR_RESETALL);
 243         while (STC_READ(sc, STC_GSVR) != 0xff);
 244         while (STC_READ(sc, STC_GFRCR) != sc->sc_rev2);
 245
 246         STC_WRITE(sc, STC_PPRH, CD180_PPRH);
 247         STC_WRITE(sc, STC_PPRL, CD180_PPRL);
 248         STC_WRITE(sc, STC_MSMR, SPIF_MSMR);
 249         STC_WRITE(sc, STC_TSMR, SPIF_TSMR);
 250         STC_WRITE(sc, STC_RSMR, SPIF_RSMR);
 251         STC_WRITE(sc, STC_GSVR, 0);
 252         STC_WRITE(sc, STC_GSCR1, 0);
 253         STC_WRITE(sc, STC_GSCR2, 0);
 254         STC_WRITE(sc, STC_GSCR3, 0);
 255
 256         printf(": rev %x chiprev %x osc %sMHz\n",
 257             sc->sc_rev, sc->sc_rev2, clockfreq(sc->sc_osc));
 258
 259         (void)config_found(self, stty_match, NULL);
 260         (void)config_found(self, sbpp_match, NULL);
 261
 262         return;
 263
 264 fail_unmapregs:
 265         bus_space_unmap(sa->sa_bustag, sc->sc_regh, sa->sa_size);
 266 }
 267
 268 int
 269 stty_match(device_t parent, cfdata_t vcf, void *aux)
 270 {
 271         struct spif_softc *sc = device_private(parent);
 272
 273         return (aux == stty_match && sc->sc_ttys == NULL);
 274 }
 275
 276 void
 277 stty_attach(device_t parent, device_t dev, void *aux)
 278 {
 279         struct spif_softc *sc = device_private(parent);
 280         struct stty_softc *ssc = device_private(dev);
 281         int port;
 282
 283         sc->sc_ttys = ssc;
 284
 285         for (port = 0; port < sc->sc_nser; port++) {
 286                 struct stty_port *sp = &ssc->sc_port[port];
 287                 struct tty *tp;
 288
 289                 DTR_WRITE(sc, port, 0);
 290
 291                 tp = ttymalloc();
 292
 293                 tp->t_oproc = stty_start;
 294                 tp->t_param = stty_param;
 295
 296                 sp->sp_tty = tp;
 297                 sp->sp_sc = sc;
 298                 sp->sp_channel = port;
 299
 300                 sp->sp_rbuf = malloc(STTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT);
 301                 if(sp->sp_rbuf == NULL)
 302                         break;
 303
 304                 sp->sp_rend = sp->sp_rbuf + STTY_RBUF_SIZE;
 305         }
 306
 307         ssc->sc_nports = port;
 308
 309         printf(": %d tty%s\n", port, port == 1 ? "" : "s");
 310 }
 311
 312 int
 313 stty_open(dev_t dev, int flags, int mode, struct lwp *l)
 314 {
 315         struct spif_softc *csc;
 316         struct stty_softc *sc;
 317         struct stty_port *sp;
 318         struct tty *tp;
 319         int card = SPIF_CARD(dev);
 320         int port = SPIF_PORT(dev);
 321
 322         sc = device_lookup_private(&stty_cd, card);
 323         csc = device_lookup_private(&spif_cd, card);
 324         if (sc == NULL || csc == NULL)
 325                 return (ENXIO);
 326
 327         if (port >= sc->sc_nports)
 328                 return (ENXIO);
 329
 330         sp = &sc->sc_port[port];
 331         tp = sp->sp_tty;
 332         tp->t_dev = dev;
 333
 334         if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
 335                 return (EBUSY);
 336
 337         mutex_spin_enter(&tty_lock);
 338         if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
 339                 ttychars(tp);
 340                 tp->t_iflag = TTYDEF_IFLAG;
 341                 tp->t_oflag = TTYDEF_OFLAG;
 342                 tp->t_cflag = TTYDEF_CFLAG;
 343                 if (ISSET(sp->sp_openflags, TIOCFLAG_CLOCAL))
 344                         SET(tp->t_cflag, CLOCAL);
 345                 if (ISSET(sp->sp_openflags, TIOCFLAG_CRTSCTS))
 346                         SET(tp->t_cflag, CRTSCTS);
 347                 if (ISSET(sp->sp_openflags, TIOCFLAG_MDMBUF))
 348                         SET(tp->t_cflag, MDMBUF);
 349                 tp->t_lflag = TTYDEF_LFLAG;
 350                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 351
 352                 sp->sp_rput = sp->sp_rget = sp->sp_rbuf;
 353
 354                 STC_WRITE(csc, STC_CAR, sp->sp_channel);
 355                 stty_write_ccr(csc, CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN);
 356                 STC_WRITE(csc, STC_CAR, sp->sp_channel);
 357
 358                 stty_param(tp, &tp->t_termios);
 359
 360                 ttsetwater(tp);
 361
 362                 STC_WRITE(csc, STC_SRER, CD180_SRER_CD | CD180_SRER_RXD);
 363
 364                 if (ISSET(sp->sp_openflags, TIOCFLAG_SOFTCAR) || sp->sp_carrier)
 365                         SET(tp->t_state, TS_CARR_ON);
 366                 else
 367                         CLR(tp->t_state, TS_CARR_ON);
 368         }
 369
 370         if (!ISSET(flags, O_NONBLOCK)) {
 371                 while (!ISSET(tp->t_cflag, CLOCAL) &&
 372                     !ISSET(tp->t_state, TS_CARR_ON)) {
 373                         int error;
 374                         error = ttysleep(tp, &tp->t_rawcv, true, 0);
 375                         if (error != 0) {
 376                                 mutex_spin_exit(&tty_lock);
 377                                 return (error);
 378                         }
 379                 }
 380         }
 381         mutex_spin_exit(&tty_lock);
 382
 383         return ((*tp->t_linesw->l_open)(dev, tp));
 384 }
 385
 386 int
 387 stty_close(dev_t dev, int flags, int mode, struct lwp *l)
 388 {
 389         struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev));
 390         struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
 391         struct spif_softc *csc = sp->sp_sc;
 392         struct tty *tp = sp->sp_tty;
 393         int port = SPIF_PORT(dev);
 394         int s;
 395
 396         (*tp->t_linesw->l_close)(tp, flags);
 397         s = spltty();
 398
 399         if (ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN)) {
 400                 stty_modem_control(sp, 0, DMSET);
 401                 STC_WRITE(csc, STC_CAR, port);
 402                 STC_WRITE(csc, STC_CCR,
 403                     CD180_CCR_CMD_RESET|CD180_CCR_RESETCHAN);
 404         }
 405
 406         splx(s);
 407         ttyclose(tp);
 408         return (0);
 409 }
 410
 411 int
 412 stty_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
 413 {
 414         struct stty_softc *stc = device_lookup_private(&stty_cd,
 415                                                        SPIF_CARD(dev));
 416         struct stty_port *sp = &stc->sc_port[SPIF_PORT(dev)];
 417         struct spif_softc *sc = sp->sp_sc;
 418         struct tty *tp = sp->sp_tty;
 419         int error;
 420
 421         error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l);
 422         if (error >= 0)
 423                 return (error);
 424
 425         error = ttioctl(tp, cmd, data, flags, l);
 426         if (error >= 0)
 427                 return (error);
 428
 429         error = 0;
 430
 431         switch (cmd) {
 432         case TIOCSBRK:
 433                 SET(sp->sp_flags, STTYF_SET_BREAK);
 434                 STC_WRITE(sc, STC_CAR, sp->sp_channel);
 435                 STC_WRITE(sc, STC_SRER,
 436                     STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
 437                 break;
 438         case TIOCCBRK:
 439                 SET(sp->sp_flags, STTYF_CLR_BREAK);
 440                 STC_WRITE(sc, STC_CAR, sp->sp_channel);
 441                 STC_WRITE(sc, STC_SRER,
 442                     STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
 443                 break;
 444         case TIOCSDTR:
 445                 stty_modem_control(sp, TIOCM_DTR, DMBIS);
 446                 break;
 447         case TIOCCDTR:
 448                 stty_modem_control(sp, TIOCM_DTR, DMBIC);
 449                 break;
 450         case TIOCMBIS:
 451                 stty_modem_control(sp, *((int *)data), DMBIS);
 452                 break;
 453         case TIOCMBIC:
 454                 stty_modem_control(sp, *((int *)data), DMBIC);
 455                 break;
 456         case TIOCMGET:
 457                 *((int *)data) = stty_modem_control(sp, 0, DMGET);
 458                 break;
 459         case TIOCMSET:
 460                 stty_modem_control(sp, *((int *)data), DMSET);
 461                 break;
 462         case TIOCGFLAGS:
 463                 *((int *)data) = sp->sp_openflags;
 464                 break;
 465         case TIOCSFLAGS:
 466                 if (kauth_authorize_device_tty(l->l_cred,
 467                     KAUTH_DEVICE_TTY_PRIVSET, tp))
 468                         error = EPERM;
 469                 else
 470                         sp->sp_openflags = *((int *)data) &
 471                             (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
 472                              TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
 473                 break;
 474         default:
 475                 error = ENOTTY;
 476         }
 477
 478         return (error);
 479 }
 480
 481 int
 482 stty_modem_control(struct stty_port *sp, int bits, int how)
 483 {
 484         struct spif_softc *csc = sp->sp_sc;
 485         struct tty *tp = sp->sp_tty;
 486         int s, msvr;
 487
 488         s = spltty();
 489         STC_WRITE(csc, STC_CAR, sp->sp_channel);
 490
 491         switch (how) {
 492         case DMGET:
 493                 bits = TIOCM_LE;
 494                 if (DTR_READ(csc, sp->sp_channel))
 495                         bits |= TIOCM_DTR;
 496                 msvr = STC_READ(csc, STC_MSVR);
 497                 if (ISSET(msvr, CD180_MSVR_DSR))
 498                         bits |= TIOCM_DSR;
 499                 if (ISSET(msvr, CD180_MSVR_CD))
 500                         bits |= TIOCM_CD;
 501                 if (ISSET(msvr, CD180_MSVR_CTS))
 502                         bits |= TIOCM_CTS;
 503                 if (ISSET(msvr, CD180_MSVR_RTS))
 504                         bits |= TIOCM_RTS;
 505                 break;
 506         case DMSET:
 507                 DTR_WRITE(csc, sp->sp_channel, ISSET(bits, TIOCM_DTR) ? 1 : 0);
 508                 if (ISSET(bits, TIOCM_RTS))
 509                         STC_WRITE(csc, STC_MSVR,
 510                             STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS));
 511                 else
 512                         STC_WRITE(csc, STC_MSVR,
 513                             STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS);
 514                 break;
 515         case DMBIS:
 516                 if (ISSET(bits, TIOCM_DTR))
 517                         DTR_WRITE(csc, sp->sp_channel, 1);
 518                 if (ISSET(bits, TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS))
 519                         STC_WRITE(csc, STC_MSVR,
 520                             STC_READ(csc, STC_MSVR) & (~CD180_MSVR_RTS));
 521                 break;
 522         case DMBIC:
 523                 if (ISSET(bits, TIOCM_DTR))
 524                         DTR_WRITE(csc, sp->sp_channel, 0);
 525                 if (ISSET(bits, TIOCM_RTS))
 526                         STC_WRITE(csc, STC_MSVR,
 527                             STC_READ(csc, STC_MSVR) | CD180_MSVR_RTS);
 528                 break;
 529         }
 530
 531         splx(s);
 532         return (bits);
 533 }
 534
 535 int
 536 stty_param(struct tty *tp, struct termios *t)
 537 {
 538         struct stty_softc *st = device_lookup_private(&stty_cd,
 539                                                       SPIF_CARD(tp->t_dev));
 540         struct stty_port *sp = &st->sc_port[SPIF_PORT(tp->t_dev)];
 541         struct spif_softc *sc = sp->sp_sc;
 542         uint8_t rbprl, rbprh, tbprl, tbprh;
 543         int s, opt;
 544
 545         if (t->c_ospeed &&
 546             stty_compute_baud(t->c_ospeed, sc->sc_osc, &tbprl, &tbprh))
 547                 return (EINVAL);
 548
 549         if (t->c_ispeed &&
 550             stty_compute_baud(t->c_ispeed, sc->sc_osc, &rbprl, &rbprh))
 551                 return (EINVAL);
 552
 553         s = spltty();
 554
 555         /* hang up line if ospeed is zero, otherwise raise DTR */
 556         stty_modem_control(sp, TIOCM_DTR,
 557             (t->c_ospeed == 0 ? DMBIC : DMBIS));
 558
 559         STC_WRITE(sc, STC_CAR, sp->sp_channel);
 560
 561         opt = 0;
 562         if (ISSET(t->c_cflag, PARENB)) {
 563                 opt |= CD180_COR1_PARMODE_NORMAL;
 564                 opt |= (ISSET(t->c_cflag, PARODD) ?
 565                                 CD180_COR1_ODDPAR :
 566                                 CD180_COR1_EVENPAR);
 567         }
 568         else
 569                 opt |= CD180_COR1_PARMODE_NO;
 570
 571         if (!ISSET(t->c_iflag, INPCK))
 572                 opt |= CD180_COR1_IGNPAR;
 573
 574         if (ISSET(t->c_cflag, CSTOPB))
 575                 opt |= CD180_COR1_STOP2;
 576
 577         switch (t->c_cflag & CSIZE) {
 578         case CS5:
 579                 opt |= CD180_COR1_CS5;
 580                 break;
 581         case CS6:
 582                 opt |= CD180_COR1_CS6;
 583                 break;
 584         case CS7:
 585                 opt |= CD180_COR1_CS7;
 586                 break;
 587         default:
 588                 opt |= CD180_COR1_CS8;
 589                 break;
 590         }
 591         STC_WRITE(sc, STC_COR1, opt);
 592         stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG1);
 593
 594         opt = CD180_COR2_ETC;
 595         if (ISSET(t->c_cflag, CRTSCTS))
 596                 opt |= CD180_COR2_CTSAE;
 597         STC_WRITE(sc, STC_COR2, opt);
 598         stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG2);
 599
 600         STC_WRITE(sc, STC_COR3, STTY_RX_FIFO_THRESHOLD);
 601         stty_write_ccr(sc, CD180_CCR_CMD_COR|CD180_CCR_CORCHG3);
 602
 603         STC_WRITE(sc, STC_SCHR1, 0x11);
 604         STC_WRITE(sc, STC_SCHR2, 0x13);
 605         STC_WRITE(sc, STC_SCHR3, 0x11);
 606         STC_WRITE(sc, STC_SCHR4, 0x13);
 607         STC_WRITE(sc, STC_RTPR, 0x12);
 608
 609         STC_WRITE(sc, STC_MCOR1, CD180_MCOR1_CDZD | STTY_RX_DTR_THRESHOLD);
 610         STC_WRITE(sc, STC_MCOR2, CD180_MCOR2_CDOD);
 611         STC_WRITE(sc, STC_MCR, 0);
 612
 613         if (t->c_ospeed) {
 614                 STC_WRITE(sc, STC_TBPRH, tbprh);
 615                 STC_WRITE(sc, STC_TBPRL, tbprl);
 616         }
 617
 618         if (t->c_ispeed) {
 619                 STC_WRITE(sc, STC_RBPRH, rbprh);
 620                 STC_WRITE(sc, STC_RBPRL, rbprl);
 621         }
 622
 623         stty_write_ccr(sc, CD180_CCR_CMD_CHAN |
 624             CD180_CCR_CHAN_TXEN | CD180_CCR_CHAN_RXEN);
 625
 626         sp->sp_carrier = STC_READ(sc, STC_MSVR) & CD180_MSVR_CD;
 627
 628         splx(s);
 629         return (0);
 630 }
 631
 632 int
 633 stty_read(dev_t dev, struct uio *uio, int flags)
 634 {
 635         struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev));
 636         struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
 637         struct tty *tp = sp->sp_tty;
 638
 639         return ((*tp->t_linesw->l_read)(tp, uio, flags));
 640 }
 641
 642 int
 643 stty_write(dev_t dev, struct uio *uio, int flags)
 644 {
 645         struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev));
 646         struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
 647         struct tty *tp = sp->sp_tty;
 648
 649         return ((*tp->t_linesw->l_write)(tp, uio, flags));
 650 }
 651
 652 int
 653 stty_poll(dev_t dev, int events, struct lwp *l)
 654 {
 655         struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev));
 656         struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
 657         struct tty *tp = sp->sp_tty;
 658
 659         return ((*tp->t_linesw->l_poll)(tp, events, l));
 660 }
 661
 662 struct tty *
 663 stty_tty(dev_t dev)
 664 {
 665         struct stty_softc *sc = device_lookup_private(&stty_cd, SPIF_CARD(dev));
 666         struct stty_port *sp = &sc->sc_port[SPIF_PORT(dev)];
 667
 668         return (sp->sp_tty);
 669 }
 670
 671 void
 672 stty_stop(struct tty *tp, int flags)
 673 {
 674         struct stty_softc *sc = device_lookup_private(&stty_cd,
 675                                                       SPIF_CARD(tp->t_dev));
 676         struct stty_port *sp = &sc->sc_port[SPIF_PORT(tp->t_dev)];
 677         int s;
 678
 679         s = spltty();
 680         if (ISSET(tp->t_state, TS_BUSY)) {
 681                 if (!ISSET(tp->t_state, TS_TTSTOP))
 682                         SET(tp->t_state, TS_FLUSH);
 683                 SET(sp->sp_flags, STTYF_STOP);
 684         }
 685         splx(s);
 686 }
 687
 688 void
 689 stty_start(struct tty *tp)
 690 {
 691         struct stty_softc *stc = device_lookup_private(&stty_cd,
 692                                                        SPIF_CARD(tp->t_dev));
 693         struct stty_port *sp = &stc->sc_port[SPIF_PORT(tp->t_dev)];
 694         struct spif_softc *sc = sp->sp_sc;
 695         int s;
 696
 697         s = spltty();
 698
 699         if (!ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY)) {
 700                 if (ttypull(tp)) {
 701                         sp->sp_txc = ndqb(&tp->t_outq, 0);
 702                         sp->sp_txp = tp->t_outq.c_cf;
 703                         SET(tp->t_state, TS_BUSY);
 704                         STC_WRITE(sc, STC_CAR, sp->sp_channel);
 705                         STC_WRITE(sc, STC_SRER,
 706                             STC_READ(sc, STC_SRER) | CD180_SRER_TXD);
 707                 }
 708         }
 709
 710         splx(s);
 711 }
 712
 713 int
 714 spif_stcintr_rxexception(struct spif_softc *sc, int *needsoftp)
 715 {
 716         struct stty_port *sp;
 717         uint8_t channel, *ptr;
 718
 719         channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
 720         sp = &sc->sc_ttys->sc_port[channel];
 721         ptr = sp->sp_rput;
 722         *ptr++ = STC_READ(sc, STC_RCSR);
 723         *ptr++ = STC_READ(sc, STC_RDR);
 724         if (ptr == sp->sp_rend)
 725                 ptr = sp->sp_rbuf;
 726         if (ptr == sp->sp_rget) {
 727                 if (ptr == sp->sp_rbuf)
 728                         ptr = sp->sp_rend;
 729                 ptr -= 2;
 730                 SET(sp->sp_flags, STTYF_RING_OVERFLOW);
 731         }
 732         STC_WRITE(sc, STC_EOSRR, 0);
 733         *needsoftp = 1;
 734         sp->sp_rput = ptr;
 735         return (1);
 736 }
 737
 738 int
 739 spif_stcintr_rx(struct spif_softc *sc, int *needsoftp)
 740 {
 741         struct stty_port *sp;
 742         uint8_t channel, *ptr, cnt, rcsr;
 743         int i;
 744
 745         channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
 746         sp = &sc->sc_ttys->sc_port[channel];
 747         ptr = sp->sp_rput;
 748         cnt = STC_READ(sc, STC_RDCR);
 749         for (i = 0; i < cnt; i++) {
 750                 *ptr++ = 0;
 751                 rcsr = STC_READ(sc, STC_RCSR);
 752                 *ptr++ = STC_READ(sc, STC_RDR);
 753                 if (ptr == sp->sp_rend)
 754                         ptr = sp->sp_rbuf;
 755                 if (ptr == sp->sp_rget) {
 756                         if (ptr == sp->sp_rbuf)
 757                                 ptr = sp->sp_rend;
 758                         ptr -= 2;
 759                         SET(sp->sp_flags, STTYF_RING_OVERFLOW);
 760                         break;
 761                 }
 762         }
 763         STC_WRITE(sc, STC_EOSRR, 0);
 764         if (cnt) {
 765                 *needsoftp = 1;
 766                 sp->sp_rput = ptr;
 767         }
 768         return (1);
 769 }
 770
 771 int
 772 spif_stcintr_tx(struct spif_softc *sc, int *needsoftp)
 773 {
 774         struct stty_port *sp;
 775         uint8_t channel, ch;
 776         int cnt = 0;
 777
 778         channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
 779         sp = &sc->sc_ttys->sc_port[channel];
 780         if (!ISSET(sp->sp_flags, STTYF_STOP)) {
 781                 if (ISSET(sp->sp_flags, STTYF_SET_BREAK)) {
 782                         STC_WRITE(sc, STC_TDR, 0);
 783                         STC_WRITE(sc, STC_TDR, 0x81);
 784                         CLR(sp->sp_flags, STTYF_SET_BREAK);
 785                         cnt += 2;
 786                 }
 787                 if (ISSET(sp->sp_flags, STTYF_CLR_BREAK)) {
 788                         STC_WRITE(sc, STC_TDR, 0);
 789                         STC_WRITE(sc, STC_TDR, 0x83);
 790                         CLR(sp->sp_flags, STTYF_CLR_BREAK);
 791                         cnt += 2;
 792                 }
 793
 794                 while (sp->sp_txc > 0 && cnt < (CD180_TX_FIFO_SIZE-1)) {
 795                         ch = *sp->sp_txp;
 796                         sp->sp_txc--;
 797                         sp->sp_txp++;
 798
 799                         if (ch == 0) {
 800                                 STC_WRITE(sc, STC_TDR, ch);
 801                                 cnt++;
 802                         }
 803                         STC_WRITE(sc, STC_TDR, ch);
 804                         cnt++;
 805                 }
 806         }
 807
 808         if (sp->sp_txc == 0 ||
 809             ISSET(sp->sp_flags, STTYF_STOP)) {
 810                 STC_WRITE(sc, STC_SRER, STC_READ(sc, STC_SRER) &
 811                     (~CD180_SRER_TXD));
 812                 CLR(sp->sp_flags, STTYF_STOP);
 813                 SET(sp->sp_flags, STTYF_DONE);
 814                 *needsoftp = 1;
 815         }
 816
 817         STC_WRITE(sc, STC_EOSRR, 0);
 818
 819         return (1);
 820 }
 821
 822 int
 823 spif_stcintr_mx(struct spif_softc *sc, int *needsoftp)
 824 {
 825         struct stty_port *sp;
 826         uint8_t channel, mcr;
 827
 828         channel = CD180_GSCR_CHANNEL(STC_READ(sc, STC_GSCR1));
 829         sp = &sc->sc_ttys->sc_port[channel];
 830         mcr = STC_READ(sc, STC_MCR);
 831         if (mcr & CD180_MCR_CD) {
 832                 SET(sp->sp_flags, STTYF_CDCHG);
 833                 *needsoftp = 1;
 834         }
 835         STC_WRITE(sc, STC_MCR, 0);
 836         STC_WRITE(sc, STC_EOSRR, 0);
 837         return (1);
 838 }
 839
 840 int
 841 spif_stcintr(void *vsc)
 842 {
 843         struct spif_softc *sc = (struct spif_softc *)vsc;
 844         int needsoft = 0, r = 0, i;
 845         uint8_t ar;
 846
 847         for (i = 0; i < 8; i++) {
 848                 ar = ISTC_READ(sc, STC_RRAR) & CD180_GSVR_IMASK;
 849                 if (ar == CD180_GSVR_RXGOOD)
 850                         r |= spif_stcintr_rx(sc, &needsoft);
 851                 else if (ar == CD180_GSVR_RXEXCEPTION)
 852                         r |= spif_stcintr_rxexception(sc, &needsoft);
 853         }
 854
 855         for (i = 0; i < 8; i++) {
 856                 ar = ISTC_READ(sc, STC_TRAR) & CD180_GSVR_IMASK;
 857                 if (ar == CD180_GSVR_TXDATA)
 858                         r |= spif_stcintr_tx(sc, &needsoft);
 859         }
 860
 861         for (i = 0; i < 8; i++) {
 862                 ar = ISTC_READ(sc, STC_MRAR) & CD180_GSVR_IMASK;
 863                 if (ar == CD180_GSVR_STATCHG)
 864                         r |= spif_stcintr_mx(sc, &needsoft);
 865         }
 866
 867         if (needsoft)
 868                 softint_schedule(sc->sc_softih);
 869         return (r);
 870 }
 871
 872 void
 873 spif_softintr(void *vsc)
 874 {
 875         struct spif_softc *sc = (struct spif_softc *)vsc;
 876         struct stty_softc *stc = sc->sc_ttys;
 877         int r = 0, i, data, s, flags;
 878         uint8_t stat, msvr;
 879         struct stty_port *sp;
 880         struct tty *tp;
 881
 882         if (stc != NULL) {
 883                 for (i = 0; i < stc->sc_nports; i++) {
 884                         sp = &stc->sc_port[i];
 885                         tp = sp->sp_tty;
 886
 887                         if (!ISSET(tp->t_state, TS_ISOPEN))
 888                                 continue;
 889
 890                         while (sp->sp_rget != sp->sp_rput) {
 891                                 stat = sp->sp_rget[0];
 892                                 data = sp->sp_rget[1];
 893                                 sp->sp_rget += 2;
 894                                 if (sp->sp_rget == sp->sp_rend)
 895                                         sp->sp_rget = sp->sp_rbuf;
 896
 897                                 if (stat & (CD180_RCSR_BE | CD180_RCSR_FE))
 898                                         data |= TTY_FE;
 899
 900                                 if (stat & CD180_RCSR_PE)
 901                                         data |= TTY_PE;
 902
 903                                 (*tp->t_linesw->l_rint)(data, tp);
 904                                 r = 1;
 905                         }
 906
 907                         s = splhigh();
 908                         flags = sp->sp_flags;
 909                         CLR(sp->sp_flags, STTYF_DONE | STTYF_CDCHG |
 910                             STTYF_RING_OVERFLOW);
 911                         splx(s);
 912
 913                         if (ISSET(flags, STTYF_CDCHG)) {
 914                                 s = spltty();
 915                                 STC_WRITE(sc, STC_CAR, i);
 916                                 msvr = STC_READ(sc, STC_MSVR);
 917                                 splx(s);
 918
 919                                 sp->sp_carrier = msvr & CD180_MSVR_CD;
 920                                 (*tp->t_linesw->l_modem)(tp,
 921                                     sp->sp_carrier);
 922                                 r = 1;
 923                         }
 924
 925                         if (ISSET(flags, STTYF_RING_OVERFLOW)) {
 926                                 log(LOG_WARNING, "%s-%x: ring overflow\n",
 927                                         device_xname(&stc->sc_dev), i);
 928                                 r = 1;
 929                         }
 930
 931                         if (ISSET(flags, STTYF_DONE)) {
 932                                 ndflush(&tp->t_outq,
 933                                     sp->sp_txp - tp->t_outq.c_cf);
 934                                 CLR(tp->t_state, TS_BUSY);
 935                                 (*tp->t_linesw->l_start)(tp);
 936                                 r = 1;
 937                         }
 938                 }
 939         }
 940 }
 941
 942 void
 943 stty_write_ccr(struct spif_softc *sc, uint8_t val)
 944 {
 945         int tries = 100000;
 946
 947         while (STC_READ(sc, STC_CCR) && tries--)
 948                 /*EMPTY*/;
 949         if (tries == 0)
 950                 aprint_error_dev(&sc->sc_dev, "ccr timeout\n");
 951         STC_WRITE(sc, STC_CCR, val);
 952 }
 953
 954 int
 955 stty_compute_baud(speed_t speed, int clock, uint8_t *bprlp, uint8_t *bprhp)
 956 {
 957         uint32_t rate;
 958
 959         rate = (2 * clock) / (16 * speed);
 960         if (rate & 1)
 961                 rate = (rate >> 1) + 1;
 962         else
 963                 rate = rate >> 1;
 964
 965         if (rate > 0xffff || rate == 0)
 966                 return (1);
 967
 968         *bprlp = rate & 0xff;
 969         *bprhp = (rate >> 8) & 0xff;
 970         return (0);
 971 }
 972
 973 int
 974 sbpp_match(device_t parent, cfdata_t vcf, void *aux)
 975 {
 976         struct spif_softc *sc = device_private(parent);
 977
 978         return (aux == sbpp_match && sc->sc_bpps == NULL);
 979 }
 980
 981 void
 982 sbpp_attach(device_t parent, device_t dev, void *aux)
 983 {
 984         struct spif_softc *sc = device_private(parent);
 985         struct sbpp_softc *psc = device_private(dev);
 986         int port;
 987
 988         sc->sc_bpps = psc;
 989
 990         for (port = 0; port < sc->sc_npar; port++) {
 991         }
 992
 993         psc->sc_nports = port;
 994         printf(": %d port%s\n", port, port == 1 ? "" : "s");
 995 }
 996
 997 int
 998 sbpp_open(dev_t dev, int flags, int mode, struct lwp *l)
 999 {
1000         return (ENXIO);
1001 }
1002
1003 int
1004 sbpp_close(dev_t dev, int flags, int mode, struct lwp *l)
1005 {
1006         return (ENXIO);
1007 }
1008
1009 int
1010 spif_ppcintr(void *v)
1011 {
1012         return (0);
1013 }
1014
1015 int
1016 sbpp_read(dev_t dev, struct uio *uio, int flags)
1017 {
1018         return (sbpp_rw(dev, uio));
1019 }
1020
1021 int
1022 sbpp_write(dev_t dev, struct uio *uio, int flags)
1023 {
1024         return (sbpp_rw(dev, uio));
1025 }
1026
1027 int
1028 sbpp_rw(dev_t dev, struct uio *uio)
1029 {
1030         return (ENXIO);
1031 }
1032
1033 int
1034 sbpp_poll(dev_t dev, int events, struct lwp *l)
1035 {
1036         return (seltrue(dev, events, l));
1037 }
1038
1039 int
1040 sbpp_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1041 {
1042         int error;
1043
1044         error = ENOTTY;
1045
1046         return (error);
1047 }
1048
1049 #endif /* NSPIF */