1 /* $NetBSD: bwtworeg.h,v 1.1.26.3 2004/09/21 13:33:26 skrll Exp $ */
4 * Copyright (c) 1992, 1993
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8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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40 * @(#)bwtworeg.h 8.1 (Berkeley) 6/11/93
44 * bwtwo display registers.
46 * The registers start at offset 0x400000 and repeat every 32 bytes
47 * (presumably only the low order address lines are decoded). Video RAM
48 * starts at offset 0x800000. We use separate pointers to each so that
49 * the sparc addressing modes work well.
52 struct fbcontrol bw_fbc
;
57 #define BWREG_REG 0x400000
58 #define BWREG_MEM 0x800000
60 /* same, but for gdb */
62 long ba_id
; /* ID = 0xfe010104 on my IPC */
63 char ba_xxx0
[0x400000-4];
64 struct fbcontrol ba_reg
; /* control registers */
65 char ba_xxx1
[0x400000-32];
66 char ba_ram
[4096]; /* actually larger */