sys/arch/acorn26/include/intr.h

   1 /* $NetBSD: intr.h,v 1.11 2007/03/09 06:45:19 thorpej Exp $ */
   2 /*-
   3  * Copyright (c) 1998, 2000 Ben Harris
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28 /*
  29  * intr.h - Interrupt stuff for the consumption of MI code.
  30  *
  31  * arm26-specific functions are in irq.h
  32  */
  33
  34 #ifndef _ARM26_INTR_H_
  35 #define _ARM26_INTR_H_
  36
  37 /*
  38  * These are the different SPL states
  39  *
  40  * Each state has an interrupt mask associated with it which
  41  * indicate which interrupts are allowed.
  42  */
  43
  44 #define IPL_NONE        0
  45 #define IPL_SOFTCLOCK   1
  46 #define IPL_SOFTNET     2
  47 #define IPL_SOFTBIO     IPL_SOFTNET
  48 #define IPL_SOFTSERIAL  IPL_SOFTNET
  49 #define IPL_VM          3
  50 #define IPL_SCHED       4
  51 #define IPL_HIGH        4
  52 #define NIPL            IPL_HIGH + 1
  53
  54 #if defined(_KERNEL) && !defined(_LOCORE)
  55
  56 #define splsoftnet()    raisespl(IPL_SOFTNET)
  57 #define splsoftbio()    splsoftnet()
  58 #define splsoftserial() splsoftnet()
  59 #define splsoftclock()  raisespl(IPL_SOFTCLOCK)
  60 #define splvm()         raisespl(IPL_VM)
  61 #define splsched()      splhigh()
  62
  63 #define spl0()                  lowerspl(IPL_NONE)
  64 #define splx(s)                 lowerspl(s)
  65
  66 extern int splhigh(void);
  67 extern int raisespl(int);
  68 extern void lowerspl(int);
  69 extern int hardsplx(int);
  70
  71 typedef uint8_t ipl_t;
  72 typedef struct {
  73         ipl_t _ipl;
  74 } ipl_cookie_t;
  75
  76 static inline ipl_cookie_t
  77 makeiplcookie(ipl_t ipl)
  78 {
  79
  80         return (ipl_cookie_t){._ipl = ipl};
  81 }
  82
  83 static inline int
  84 splraiseipl(ipl_cookie_t icookie)
  85 {
  86         ipl_t newipl = icookie._ipl;
  87
  88         return ((newipl) == IPL_HIGH) ? splhigh() : raisespl(newipl);
  89 }
  90
  91 /*
  92  * Interrupt sharing types
  93  * (not currently used on arm26)
  94  */
  95
  96 #define IST_UNUSABLE    -1      /* interrupt cannot be used */
  97 #define IST_NONE        0       /* none (dummy) */
  98 #define IST_PULSE       1       /* pulsed */
  99 #define IST_EDGE        2       /* edge-triggered */
 100 #define IST_LEVEL       3       /* level-triggered */
 101
 102 #endif /* _KERNEL && !ASSEMBLER */
 103 #endif