sys/arch/cobalt/pci/pci_machdep.c

   1 /*      $NetBSD: pci_machdep.c,v 1.26 2008/03/22 18:32:20 tsutsui Exp $ */
   2
   3 /*
   4  * Copyright (c) 2000 Soren S. Jorvang.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.26 2008/03/22 18:32:20 tsutsui Exp $");
  30
  31 #include <sys/types.h>
  32 #include <sys/param.h>
  33 #include <sys/time.h>
  34 #include <sys/systm.h>
  35 #include <sys/errno.h>
  36 #include <sys/device.h>
  37 #include <sys/extent.h>
  38
  39 #define _COBALT_BUS_DMA_PRIVATE
  40 #include <machine/bus.h>
  41 #include <machine/intr.h>
  42
  43 #include <dev/pci/pcivar.h>
  44 #include <dev/pci/pcireg.h>
  45 #include <dev/pci/pcidevs.h>
  46 #include <dev/pci/pciconf.h>
  47 #include <dev/pci/pciide_apollo_reg.h>
  48
  49 #include <cobalt/dev/gtreg.h>
  50
  51 /*
  52  * PCI doesn't have any special needs; just use
  53  * the generic versions of these functions.
  54  */
  55 struct cobalt_bus_dma_tag pci_bus_dma_tag = {
  56         _bus_dmamap_create,
  57         _bus_dmamap_destroy,
  58         _bus_dmamap_load,
  59         _bus_dmamap_load_mbuf,
  60         _bus_dmamap_load_uio,
  61         _bus_dmamap_load_raw,
  62         _bus_dmamap_unload,
  63         _bus_dmamap_sync,
  64         _bus_dmamem_alloc,
  65         _bus_dmamem_free,
  66         _bus_dmamem_map,
  67         _bus_dmamem_unmap,
  68         _bus_dmamem_mmap,
  69 };
  70
  71 void
  72 pci_attach_hook(struct device *parent, struct device *self,
  73     struct pcibus_attach_args *pba)
  74 {
  75         /* XXX */
  76
  77         return;
  78 }
  79
  80 int
  81 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
  82 {
  83
  84         return 32;
  85 }
  86
  87 pcitag_t
  88 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
  89 {
  90
  91         return (bus << 16) | (device << 11) | (function << 8);
  92 }
  93
  94 void
  95 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
  96 {
  97
  98         if (bp != NULL)
  99                 *bp = (tag >> 16) & 0xff;
 100         if (dp != NULL)
 101                 *dp = (tag >> 11) & 0x1f;
 102         if (fp != NULL)
 103                 *fp = (tag >> 8) & 0x07;
 104 }
 105
 106 pcireg_t
 107 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
 108 {
 109         pcireg_t data;
 110         int bus, dev, func;
 111
 112         pci_decompose_tag(pc, tag, &bus, &dev, &func);
 113
 114         /*
 115          * 2700 hardware wedges on accesses to device 6.
 116          */
 117         if (bus == 0 && dev == 6)
 118                 return 0;
 119         /*
 120          * 2800 hardware wedges on accesses to device 31.
 121          */
 122         if (bus == 0 && dev == 31)
 123                 return 0;
 124
 125         bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
 126             PCICFG_ENABLE | tag | reg);
 127         data = bus_space_read_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA);
 128         bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
 129
 130         return data;
 131 }
 132
 133 void
 134 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
 135 {
 136
 137         bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
 138             PCICFG_ENABLE | tag | reg);
 139         bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA, data);
 140         bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
 141 }
 142
 143 int
 144 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 145 {
 146         pci_chipset_tag_t pc = pa->pa_pc;
 147         pcitag_t intrtag = pa->pa_intrtag;
 148         int pin = pa->pa_intrpin;
 149         int line = pa->pa_intrline;
 150         int bus, dev, func;
 151
 152         pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
 153
 154         /*
 155          * The interrupt lines of the internal Tulips are connected
 156          * directly to the CPU.
 157          */
 158         if (cobalt_id == COBALT_ID_QUBE2700) {
 159                 if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
 160                         /* tulip is connected to CPU INT2 on Qube2700 */
 161                         *ihp = NICU_INT + 2;
 162                         return 0;
 163                 }
 164         } else {
 165                 if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
 166                         /* the primary tulip is connected to CPU INT1 */
 167                         *ihp = NICU_INT + 1;
 168                         return 0;
 169                 }
 170                 if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A) {
 171                         /* the secondary tulip is connected to CPU INT2 */
 172                         *ihp = NICU_INT + 2;
 173                         return 0;
 174                 }
 175         }
 176
 177         /* sanity check */
 178         if (line == 0 || line >= NICU_INT)
 179                 return -1;
 180
 181         *ihp = line;
 182         return 0;
 183 }
 184
 185 const char *
 186 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
 187 {
 188         static char irqstr[8];
 189
 190         if (ih >= NICU_INT)
 191                 sprintf(irqstr, "level %d", ih - NICU_INT);
 192         else
 193                 sprintf(irqstr, "irq %d", ih);
 194
 195         return irqstr;
 196 }
 197
 198 const struct evcnt *
 199 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
 200 {
 201
 202         /* XXX for now, no evcnt parent reported */
 203         return NULL;
 204 }
 205
 206 int
 207 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
 208                  int attr, uint64_t data)
 209 {
 210
 211         switch (attr) {
 212         case PCI_INTR_MPSAFE:
 213                 return 0;
 214         default:
 215                 return ENODEV;
 216         }
 217 }
 218
 219 void *
 220 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
 221     int (*func)(void *), void *arg)
 222 {
 223
 224         if (ih >= NICU_INT)
 225                 return cpu_intr_establish(ih - NICU_INT, level, func, arg);
 226         else
 227                 return icu_intr_establish(ih, IST_LEVEL, level, func, arg);
 228 }
 229
 230 void
 231 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
 232 {
 233
 234         /* Try both, only the valid one will disestablish. */
 235         cpu_intr_disestablish(cookie);
 236         icu_intr_disestablish(cookie);
 237 }
 238
 239 void
 240 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
 241     int *iline)
 242 {
 243
 244         /*
 245          * Use irq 9 on all devices on the Qube's PCI slot.
 246          * XXX doesn't handle devices over PCI-PCI bridges
 247          */
 248         if (bus == 0 && dev == 10 && pin != PCI_INTERRUPT_PIN_NONE)
 249                 *iline = 9;
 250 }
 251
 252 int
 253 pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
 254 {
 255
 256         /* ignore bogus IDs */
 257         if (PCI_VENDOR(id) == 0)
 258                 return 0;
 259
 260         /* 2700 hardware wedges on accesses to device 6. */
 261         if (bus == 0 && dev == 6)
 262                 return 0;
 263
 264         /* 2800 hardware wedges on accesses to device 31. */
 265         if (bus == 0 && dev == 31)
 266                 return 0;
 267
 268         /* Don't configure the bridge and PCI probe. */
 269         if (PCI_VENDOR(id) == PCI_VENDOR_MARVELL &&
 270             PCI_PRODUCT(id) == PCI_PRODUCT_MARVELL_GT64011)
 271                 return 0;
 272
 273         /* Don't configure on-board VIA VT82C586 (pcib, uhci) */
 274         if (bus == 0 && dev == 9 && (func == 0 || func == 2))
 275                 return 0;
 276
 277         /* Enable viaide secondary port. Some firmware doesn't enable it. */
 278         if (bus == 0 && dev == 9 && func == 1) {
 279                 pcitag_t tag;
 280                 pcireg_t csr;
 281
 282 #define APO_VIAIDECONF  (APO_VIA_REGBASE + 0x00)
 283
 284                 tag = pci_make_tag(pc, bus, dev, func);
 285                 csr = pci_conf_read(pc, tag, APO_VIAIDECONF);
 286                 pci_conf_write(pc, tag, APO_VIAIDECONF,
 287                     csr | APO_IDECONF_EN(1));
 288         }
 289         return PCI_CONF_DEFAULT & ~(PCI_COMMAND_SERR_ENABLE |
 290             PCI_COMMAND_PARITY_ENABLE);
 291 }