?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / arch / i386 / pci / elan520.c
blobcae29dd68051a4c61c30c315b74d94f03344d04d
1 /* $NetBSD: elan520.c,v 1.45 2010/01/08 00:09:44 dyoung Exp $ */
2
3 /*-
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Device driver for the AMD Elan SC520 System Controller. This attaches
34 * where the "pchb" driver might normally attach, and provides support for
35 * extra features on the SC520, such as the watchdog timer and GPIO.
36 *
37 * Information about the GP bus echo bug work-around is from code posted
38 * to the "soekris-tech" mailing list by Jasper Wallace.
39 */
40
41 #include <sys/cdefs.h>
42
43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.45 2010/01/08 00:09:44 dyoung Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/time.h>
48 #include <sys/device.h>
49 #include <sys/gpio.h>
50 #include <sys/mutex.h>
51 #include <sys/wdog.h>
52 #include <sys/reboot.h>
53
54 #include <uvm/uvm_extern.h>
55
56 #include <machine/bus.h>
57
58 #include <x86/nmi.h>
59
60 #include <dev/pci/pcivar.h>
61
62 #include <dev/pci/pcidevs.h>
63
64 #include "gpio.h"
65 #if NGPIO > 0
66 #include <dev/gpio/gpiovar.h>
67 #endif
68
69 #include <arch/i386/pci/elan520reg.h>
70
71 #include <dev/sysmon/sysmonvar.h>
72
73 #define ELAN_IRQ 1
74 #define PG0_PROT_SIZE PAGE_SIZE
75
76 struct elansc_softc {
77 device_t sc_dev;
78 device_t sc_gpio;
79 device_t sc_par;
80 device_t sc_pex;
81 device_t sc_pci;
82
83 pci_chipset_tag_t sc_pc;
84 pcitag_t sc_tag;
85 bus_dma_tag_t sc_dmat;
86 bus_dma_tag_t sc_dmat64;
87 bus_space_tag_t sc_iot;
88 bus_space_tag_t sc_memt;
89 bus_space_handle_t sc_memh;
90 int sc_pciflags;
91
92 int sc_echobug;
93
94 kmutex_t sc_mtx;
95
96 struct sysmon_wdog sc_smw;
97 void *sc_eih;
98 void *sc_pih;
99 void *sc_sh;
100 uint8_t sc_mpicmode;
101 uint8_t sc_picicr;
102 int sc_pg0par;
103 int sc_textpar[3];
104 #if NGPIO > 0
105 /* GPIO interface */
106 struct gpio_chipset_tag sc_gpio_gc;
107 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS];
108 #endif
109 };
110
111 struct pareg {
112 paddr_t start;
113 paddr_t end;
114 };
115
116 static bool elansc_attached = false;
117 int elansc_wpvnmi = 1;
118 int elansc_pcinmi = 1;
119 int elansc_do_protect_pg0 = 1;
120
121 #if NGPIO > 0
122 static int elansc_gpio_pin_read(void *, int);
123 static void elansc_gpio_pin_write(void *, int, int);
124 static void elansc_gpio_pin_ctl(void *, int, int);
125 #endif
126
127 static void elansc_print_par(device_t, int, uint32_t);
128
129 static void elanpar_intr_establish(device_t, struct elansc_softc *);
130 static void elanpar_intr_disestablish(struct elansc_softc *);
131 static bool elanpar_shutdown(device_t, int);
132
133 static void elanpex_intr_establish(device_t, struct elansc_softc *);
134 static void elanpex_intr_disestablish(struct elansc_softc *);
135 static bool elanpex_shutdown(device_t, int);
136 static int elansc_rescan(device_t, const char *, const int *);
137
138 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t);
139 static bool elansc_shutdown(device_t, int);
140
141 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024;
142
143 static void
144 elansc_childdetached(device_t self, device_t child)
145 {
146 struct elansc_softc *sc = device_private(self);
147
148 if (child == sc->sc_par)
149 sc->sc_par = NULL;
150 if (child == sc->sc_pex)
151 sc->sc_pex = NULL;
152 if (child == sc->sc_pci)
153 sc->sc_pci = NULL;
154 if (child == sc->sc_gpio)
155 sc->sc_gpio = NULL;
156 }
157
158 static int
159 elansc_match(device_t parent, cfdata_t match, void *aux)
160 {
161 struct pcibus_attach_args *pba = aux;
162 pcitag_t tag;
163 pcireg_t id;
164
165 if (elansc_attached)
166 return 0;
167
168 if (pcimatch(parent, match, aux) == 0)
169 return 0;
170
171 if (pba->pba_bus != 0)
172 return 0;
173
174 tag = pci_make_tag(pba->pba_pc, 0, 0, 0);
175 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG);
176
177 if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
178 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC)
179 return 10;
180
181 return 0;
182 }
183
184 /*
185 * Performance tuning for Soekris net4501:
186 * - enable SDRAM write buffer and read prefetching
187 */
188 #if 0
189 uint8_t dbctl;
190
191 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL);
192 dbctl &= ~MMCR_DBCTL_WB_WM_MASK;
193 dbctl |= MMCR_DBCTL_WB_WM_16DW;
194 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB;
195 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl);
196 #endif
197
198 /*
199 * Performance tuning for PCI bus on the AMD Elan SC520:
200 * - enable concurrent arbitration of PCI and CPU busses
201 * (and PCI buffer)
202 * - enable PCI automatic delayed read transactions and
203 * write posting
204 * - enable PCI read buffer snooping (coherency)
205 */
206 static void
207 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh)
208 {
209 uint8_t sysarbctl;
210 uint16_t hbctl;
211 const bool concurrency = true; /* concurrent bus arbitration */
212
213 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL);
214 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) {
215 aprint_debug_dev(self,
216 "concurrent arbitration mode is active\n");
217 } else if (concurrency) {
218 aprint_verbose_dev(self, "activating concurrent "
219 "arbitration mode\n");
220 /* activate concurrent bus arbitration */
221 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB;
222 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl);
223 }
224
225 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL);
226
227 /* target read FIFO snoop */
228 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0)
229 aprint_debug_dev(self, "read-FIFO snooping is active\n");
230 else {
231 aprint_verbose_dev(self, "activating read-FIFO snooping\n");
232 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB;
233 }
234
235 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0)
236 aprint_debug_dev(self, "CPU->PCI write-posting is active\n");
237 else if (concurrency) {
238 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n");
239 hbctl |= MMCR_HBCTL_M_WPOST_ENB;
240 }
241
242 /* auto delay read txn: looks safe, but seems to cause
243 * net4526 w/ minipci ath fits
244 */
245 #if 0
246 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0)
247 aprint_debug_dev(self,
248 "automatic read transaction delay is active\n");
249 else {
250 aprint_verbose_dev(self,
251 "activating automatic read transaction delay\n");
252 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY;
253 }
254 #endif
255 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl);
256 }
257
258 static void
259 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val)
260 {
261 uint8_t echo_mode = 0; /* XXX: gcc */
262
263 KASSERT(mutex_owned(&sc->sc_mtx));
264
265 /* Switch off GP bus echo mode if we need to. */
266 if (sc->sc_echobug) {
267 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
268 MMCR_GPECHO);
269 bus_space_write_1(sc->sc_memt, sc->sc_memh,
270 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB);
271 }
272
273 /* Unlock the register. */
274 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
275 WDTMRCTL_UNLOCK1);
276 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
277 WDTMRCTL_UNLOCK2);
278
279 /* Write the value. */
280 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val);
281
282 /* Switch GP bus echo mode back. */
283 if (sc->sc_echobug)
284 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
285 echo_mode);
286 }
287
288 static void
289 elansc_wdogctl_reset(struct elansc_softc *sc)
290 {
291 uint8_t echo_mode = 0/* XXX: gcc */;
292
293 KASSERT(mutex_owned(&sc->sc_mtx));
294
295 /* Switch off GP bus echo mode if we need to. */
296 if (sc->sc_echobug) {
297 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
298 MMCR_GPECHO);
299 bus_space_write_1(sc->sc_memt, sc->sc_memh,
300 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB);
301 }
302
303 /* Reset the watchdog. */
304 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
305 WDTMRCTL_RESET1);
306 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL,
307 WDTMRCTL_RESET2);
308
309 /* Switch GP bus echo mode back. */
310 if (sc->sc_echobug)
311 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO,
312 echo_mode);
313 }
314
315 static const struct {
316 int period; /* whole seconds */
317 uint16_t exp; /* exponent select */
318 } elansc_wdog_periods[] = {
319 { 1, WDTMRCTL_EXP_SEL25 },
320 { 2, WDTMRCTL_EXP_SEL26 },
321 { 4, WDTMRCTL_EXP_SEL27 },
322 { 8, WDTMRCTL_EXP_SEL28 },
323 { 16, WDTMRCTL_EXP_SEL29 },
324 { 32, WDTMRCTL_EXP_SEL30 },
325 { 0, 0 },
326 };
327
328 static int
329 elansc_wdog_arm(struct elansc_softc *sc)
330 {
331 struct sysmon_wdog *smw = &sc->sc_smw;
332 int i;
333 uint16_t exp_sel = 0; /* XXX: gcc */
334
335 KASSERT(mutex_owned(&sc->sc_mtx));
336
337 if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
338 smw->smw_period = 32;
339 exp_sel = WDTMRCTL_EXP_SEL30;
340 } else {
341 for (i = 0; elansc_wdog_periods[i].period != 0; i++) {
342 if (elansc_wdog_periods[i].period ==
343 smw->smw_period) {
344 exp_sel = elansc_wdog_periods[i].exp;
345 break;
346 }
347 }
348 if (elansc_wdog_periods[i].period == 0)
349 return EINVAL;
350 }
351 elansc_wdogctl_write(sc, WDTMRCTL_ENB |
352 WDTMRCTL_WRST_ENB | exp_sel);
353 elansc_wdogctl_reset(sc);
354 return 0;
355 }
356
357 static int
358 elansc_wdog_setmode(struct sysmon_wdog *smw)
359 {
360 struct elansc_softc *sc = smw->smw_cookie;
361 int rc = 0;
362
363 mutex_enter(&sc->sc_mtx);
364
365 if (!device_is_active(sc->sc_dev))
366 rc = EBUSY;
367 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
368 elansc_wdogctl_write(sc,
369 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
370 } else
371 rc = elansc_wdog_arm(sc);
372
373 mutex_exit(&sc->sc_mtx);
374 return rc;
375 }
376
377 static int
378 elansc_wdog_tickle(struct sysmon_wdog *smw)
379 {
380 struct elansc_softc *sc = smw->smw_cookie;
381
382 mutex_enter(&sc->sc_mtx);
383 elansc_wdogctl_reset(sc);
384 mutex_exit(&sc->sc_mtx);
385 return 0;
386 }
387
388 static const char *elansc_speeds[] = {
389 "(reserved 00)",
390 "100MHz",
391 "133MHz",
392 "(reserved 11)",
393 };
394
395 static int
396 elanpar_intr(void *arg)
397 {
398 struct elansc_softc *sc = arg;
399 uint16_t wpvsta;
400 unsigned win;
401 uint32_t par;
402 const char *wpvstr;
403
404 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA);
405
406 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0)
407 return 0;
408
409 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW);
410
411 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win));
412
413 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
414 MMCR_WPVSTA_WPV_STA);
415
416 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) {
417 case MMCR_WPVSTA_WPV_MSTR_CPU:
418 wpvstr = "cpu";
419 break;
420 case MMCR_WPVSTA_WPV_MSTR_PCI:
421 wpvstr = "pci";
422 break;
423 case MMCR_WPVSTA_WPV_MSTR_GP:
424 wpvstr = "gp";
425 break;
426 default:
427 wpvstr = "unknown";
428 break;
429 }
430 printf_tolog("%s: %s violated write-protect window %u\n",
431 device_xname(sc->sc_par), wpvstr, win);
432 elansc_print_par(sc->sc_par, win, par);
433 return 0;
434 }
435
436 static int
437 elanpar_nmi(const struct trapframe *tf, void *arg)
438 {
439
440 return elanpar_intr(arg);
441 }
442
443 static int
444 elanpex_intr(void *arg)
445 {
446 static struct {
447 const char *string;
448 bool nonfatal;
449 } cmd[16] = {
450 [0] = {.string = "not latched"}
451 , [1] = {.string = "special cycle"}
452 , [2] = {.string = "i/o read"}
453 , [3] = {.string = "i/o write"}
454 , [4] = {.string = "4"}
455 , [5] = {.string = "5"}
456 , [6] = {.string = "memory rd"}
457 , [7] = {.string = "memory wr"}
458 , [8] = {.string = "8"}
459 , [9] = {.string = "9"}
460 , [10] = {.string = "cfg rd", .nonfatal = true}
461 , [11] = {.string = "cfg wr"}
462 , [12] = {.string = "memory rd mul"}
463 , [13] = {.string = "dual-address cycle"}
464 , [14] = {.string = "memory rd line"}
465 , [15] = {.string = "memory wr & inv"}
466 };
467
468 static const struct {
469 uint16_t bit;
470 const char *msg;
471 } mmsg[] = {
472 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"}
473 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"}
474 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"}
475 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"}
476 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"}
477 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"}
478 }, tmsg[] = {
479 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"}
480 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"}
481 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"}
482 };
483 uint8_t pciarbsta;
484 uint16_t mstcmd, mstirq, tgtid, tgtirq;
485 uint32_t mstaddr;
486 uint16_t mstack = 0, tgtack = 0;
487 int fatal = 0, i, handled = 0;
488 struct elansc_softc *sc = arg;
489
490 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA);
491 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA);
492 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD);
493 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA);
494
495 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) {
496 printf_tolog(
497 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n",
498 device_xname(sc->sc_pex),
499 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID));
500 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA,
501 MMCR_PCIARBSTA_GNT_TO_STA);
502 handled = true;
503 }
504
505 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID);
506
507 for (i = 0; i < __arraycount(mmsg); i++) {
508 if ((mstirq & mmsg[i].bit) == 0)
509 continue;
510 printf_tolog("%s: %s %08" PRIx32 " master %s\n",
511 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr,
512 mmsg[i].msg);
513
514 mstack |= mmsg[i].bit;
515 if (!cmd[mstcmd].nonfatal)
516 fatal = true;
517 }
518
519 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID);
520
521 for (i = 0; i < __arraycount(tmsg); i++) {
522 if ((tgtirq & tmsg[i].bit) == 0)
523 continue;
524 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex),
525 tgtid, tmsg[i].msg);
526 tgtack |= tmsg[i].bit;
527 }
528
529 /* acknowledge interrupts */
530 if (tgtack != 0) {
531 handled = true;
532 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA,
533 tgtack);
534 }
535 if (mstack != 0) {
536 handled = true;
537 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA,
538 mstack);
539 }
540 return fatal ? 0 : (handled ? 1 : 0);
541 }
542
543 static int
544 elanpex_nmi(const struct trapframe *tf, void *arg)
545 {
546
547 return elanpex_intr(arg);
548 }
549
550 #define elansc_print_1(__dev, __sc, __reg) \
551 do { \
552 aprint_debug_dev(__dev, \
553 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \
554 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \
555 } while (/*CONSTCOND*/0)
556
557 static void
558 elansc_print_par(device_t dev, int i, uint32_t par)
559 {
560 uint32_t addr, sz, unit;
561 const char *tgtstr;
562
563 if ((boothowto & AB_DEBUG) == 0)
564 return;
565
566 switch (par & MMCR_PAR_TARGET) {
567 default:
568 case MMCR_PAR_TARGET_OFF:
569 tgtstr = "off";
570 break;
571 case MMCR_PAR_TARGET_GPIO:
572 tgtstr = "gpio";
573 break;
574 case MMCR_PAR_TARGET_GPMEM:
575 tgtstr = "gpmem";
576 break;
577 case MMCR_PAR_TARGET_PCI:
578 tgtstr = "pci";
579 break;
580 case MMCR_PAR_TARGET_BOOTCS:
581 tgtstr = "bootcs";
582 break;
583 case MMCR_PAR_TARGET_ROMCS1:
584 tgtstr = "romcs1";
585 break;
586 case MMCR_PAR_TARGET_ROMCS2:
587 tgtstr = "romcs2";
588 break;
589 case MMCR_PAR_TARGET_SDRAM:
590 tgtstr = "sdram";
591 break;
592 }
593 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) {
594 unit = 1;
595 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ);
596 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR);
597 } else if ((par & MMCR_PAR_PG_SZ) != 0) {
598 unit = 64 * 1024;
599 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ);
600 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR);
601 } else {
602 unit = 4 * 1024;
603 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ);
604 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR);
605 }
606
607 printf_tolog(
608 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS
609 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev),
610 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR),
611 addr * unit, (sz + 1) * unit);
612 }
613
614 static void
615 elansc_print_all_par(device_t dev,
616 bus_space_tag_t memt, bus_space_handle_t memh)
617 {
618 int i;
619 uint32_t par;
620
621 for (i = 0; i < 16; i++) {
622 par = bus_space_read_4(memt, memh, MMCR_PAR(i));
623 elansc_print_par(dev, i, par);
624 }
625 }
626
627 static int
628 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh)
629 {
630 int i;
631 uint32_t par;
632
633 for (i = 0; i < 16; i++) {
634
635 par = bus_space_read_4(memt, memh, MMCR_PAR(i));
636
637 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF)
638 break;
639 }
640 if (i == 16)
641 return -1;
642 return i;
643 }
644
645 static void
646 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx)
647 {
648 uint32_t par;
649 par = bus_space_read_4(memt, memh, MMCR_PAR(idx));
650 par &= ~MMCR_PAR_TARGET;
651 par |= MMCR_PAR_TARGET_OFF;
652 bus_space_write_4(memt, memh, MMCR_PAR(idx), par);
653 }
654
655 static int
656 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit)
657 {
658 struct pareg *residue = regions;
659 paddr_t start, end;
660 paddr_t start0, end0;
661
662 start0 = region0->start;
663 end0 = region0->end;
664
665 if (start0 % unit != 0)
666 start = start0 + unit - start0 % unit;
667 else
668 start = start0;
669
670 end = end0 - end0 % unit;
671
672 if (start >= end)
673 return 0;
674
675 residue->start = start;
676 residue->end = end;
677 residue++;
678
679 if (start0 < start) {
680 residue->start = start0;
681 residue->end = start;
682 residue++;
683 }
684 if (end < end0) {
685 residue->start = end;
686 residue->end = end0;
687 residue++;
688 }
689 return residue - regions;
690 }
691
692 static void
693 elansc_protect_text(device_t self, struct elansc_softc *sc)
694 {
695 int i, j, nregion, pidx, tidx = 0, xnregion;
696 uint32_t par;
697 uint32_t protsize, unprotsize;
698 paddr_t start_pa, end_pa;
699 extern char kernel_text, etext;
700 bus_space_tag_t memt;
701 bus_space_handle_t memh;
702 struct pareg region0, regions[3], xregions[3];
703
704 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1;
705
706 memt = sc->sc_memt;
707 memh = sc->sc_memh;
708
709 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text,
710 &region0.start) ||
711 !pmap_extract(pmap_kernel(), (vaddr_t)&etext,
712 &region0.end))
713 return;
714
715 if (&etext - &kernel_text != region0.end - region0.start) {
716 aprint_error_dev(self, "kernel text may not be contiguous\n");
717 return;
718 }
719
720 if ((pidx = elansc_alloc_par(memt, memh)) == -1) {
721 aprint_error_dev(self, "cannot allocate PAR\n");
722 return;
723 }
724
725 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx));
726
727 aprint_debug_dev(self,
728 "protect kernel text at physical addresses %p - %p\n",
729 (void *)region0.start, (void *)region0.end);
730
731 nregion = region_paddr_to_par(&region0, regions, sfkb);
732 if (nregion == 0) {
733 aprint_error_dev(self, "kernel text is unprotected\n");
734 return;
735 }
736
737 unprotsize = 0;
738 for (i = 1; i < nregion; i++)
739 unprotsize += regions[i].end - regions[i].start;
740
741 start_pa = regions[0].start;
742 end_pa = regions[0].end;
743
744 aprint_debug_dev(self,
745 "actually protect kernel text at physical addresses %p - %p\n",
746 (void *)start_pa, (void *)end_pa);
747
748 aprint_verbose_dev(self,
749 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize);
750
751 protsize = end_pa - start_pa;
752
753 elansc_protect(sc, pidx, start_pa, protsize);
754
755 sc->sc_textpar[tidx++] = pidx;
756
757 unprotsize = 0;
758 for (i = 1; i < nregion; i++) {
759 xnregion = region_paddr_to_par(&regions[i], xregions, fkb);
760 if (xnregion == 0) {
761 aprint_verbose_dev(self, "skip region %p - %p\n",
762 (void *)regions[i].start, (void *)regions[i].end);
763 continue;
764 }
765 if ((pidx = elansc_alloc_par(memt, memh)) == -1) {
766 unprotsize += regions[i].end - regions[i].start;
767 continue;
768 }
769 elansc_protect(sc, pidx, xregions[0].start,
770 xregions[0].end - xregions[0].start);
771 sc->sc_textpar[tidx++] = pidx;
772
773 aprint_debug_dev(self,
774 "protect add'l kernel text at physical addresses %p - %p\n",
775 (void *)xregions[0].start, (void *)xregions[0].end);
776
777 for (j = 1; j < xnregion; j++)
778 unprotsize += xregions[j].end - xregions[j].start;
779 }
780 aprint_verbose_dev(self,
781 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize);
782
783 }
784
785 static void
786 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz)
787 {
788 uint32_t addr_field, blksz, par, size_field;
789
790 /* set attribute, target. */
791 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE;
792
793 KASSERT(addr % fkb == 0 && sz % fkb == 0);
794
795 if (addr % sfkb == 0 && sz % sfkb == 0) {
796 par |= MMCR_PAR_PG_SZ;
797
798 size_field = MMCR_PAR_64KB_SZ;
799 addr_field = MMCR_PAR_64KB_ST_ADR;
800 blksz = 64 * 1024;
801 } else {
802 size_field = MMCR_PAR_4KB_SZ;
803 addr_field = MMCR_PAR_4KB_ST_ADR;
804 blksz = 4 * 1024;
805 }
806
807 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field));
808 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field));
809
810 /* set size and address. */
811 par |= __SHIFTIN(sz / blksz - 1, size_field);
812 par |= __SHIFTIN(addr / blksz, addr_field);
813
814 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par);
815 }
816
817 static int
818 elansc_protect_pg0(device_t self, struct elansc_softc *sc)
819 {
820 int pidx;
821 const paddr_t pg0_paddr = 0;
822 bus_space_tag_t memt;
823 bus_space_handle_t memh;
824
825 memt = sc->sc_memt;
826 memh = sc->sc_memh;
827
828 if (elansc_do_protect_pg0 == 0)
829 return -1;
830
831 if ((pidx = elansc_alloc_par(memt, memh)) == -1)
832 return -1;
833
834 aprint_debug_dev(self, "protect page 0\n");
835
836 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE);
837 return pidx;
838 }
839
840 static void
841 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh)
842 {
843 bus_space_write_1(memt, memh, MMCR_PCIARBSTA,
844 MMCR_PCIARBSTA_GNT_TO_STA);
845 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT);
846 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT);
847 }
848
849 static bool
850 elansc_suspend(device_t dev, pmf_qual_t qual)
851 {
852 bool rc;
853 struct elansc_softc *sc = device_private(dev);
854
855 mutex_enter(&sc->sc_mtx);
856 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED);
857 mutex_exit(&sc->sc_mtx);
858 if (!rc)
859 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden");
860 return rc;
861 }
862
863 static bool
864 elansc_resume(device_t dev, pmf_qual_t qual)
865 {
866 struct elansc_softc *sc = device_private(dev);
867
868 mutex_enter(&sc->sc_mtx);
869 /* Set up the watchdog registers with some defaults. */
870 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
871
872 /* ...and clear it. */
873 elansc_wdogctl_reset(sc);
874 mutex_exit(&sc->sc_mtx);
875
876 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh);
877
878 return true;
879 }
880
881 static bool
882 elansc_shutdown(device_t self, int how)
883 {
884 struct elansc_softc *sc = device_private(self);
885
886 /* Set up the watchdog registers with some defaults. */
887 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
888
889 /* ...and clear it. */
890 elansc_wdogctl_reset(sc);
891
892 return true;
893 }
894
895 static int
896 elansc_detach(device_t self, int flags)
897 {
898 int rc;
899 struct elansc_softc *sc = device_private(self);
900
901 if ((rc = config_detach_children(self, flags)) != 0)
902 return rc;
903
904 pmf_device_deregister(self);
905
906 if ((flags & DETACH_SHUTDOWN) == 0 &&
907 (rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) {
908 if (rc == ERESTART)
909 rc = EINTR;
910 return rc;
911 }
912
913 mutex_enter(&sc->sc_mtx);
914
915 (void)elansc_shutdown(self, 0);
916
917 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, sc->sc_picicr);
918 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE,
919 sc->sc_mpicmode);
920
921 mutex_exit(&sc->sc_mtx);
922 mutex_destroy(&sc->sc_mtx);
923
924 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE);
925 elansc_attached = false;
926 return 0;
927 }
928
929 static void *
930 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg)
931 {
932 struct pic *pic;
933 void *ih;
934
935 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) {
936 aprint_error_dev(dev, "PIC for irq %d not found\n",
937 ELAN_IRQ);
938 return NULL;
939 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ,
940 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) {
941 aprint_error_dev(dev,
942 "could not establish interrupt\n");
943 return NULL;
944 }
945 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ);
946 return ih;
947 }
948
949 static bool
950 elanpex_resume(device_t self, pmf_qual_t qual)
951 {
952 struct elansc_softc *sc = device_private(device_parent(self));
953
954 elanpex_intr_establish(self, sc);
955 return sc->sc_eih != NULL;
956 }
957
958 static bool
959 elanpex_suspend(device_t self, pmf_qual_t qual)
960 {
961 struct elansc_softc *sc = device_private(device_parent(self));
962
963 elanpex_intr_disestablish(sc);
964
965 return true;
966 }
967
968 static bool
969 elanpar_resume(device_t self, pmf_qual_t qual)
970 {
971 struct elansc_softc *sc = device_private(device_parent(self));
972
973 elanpar_intr_establish(self, sc);
974 return sc->sc_pih != NULL;
975 }
976
977 static bool
978 elanpar_suspend(device_t self, pmf_qual_t qual)
979 {
980 struct elansc_softc *sc = device_private(device_parent(self));
981
982 elanpar_intr_disestablish(sc);
983
984 return true;
985 }
986
987 static void
988 elanpex_intr_establish(device_t self, struct elansc_softc *sc)
989 {
990 uint8_t sysarbctl;
991 uint16_t pcihostmap, mstirq, tgtirq;
992
993 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh,
994 MMCR_PCIHOSTMAP);
995 /* Priority P2 (Master PIC IR1) */
996 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP;
997 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP);
998 if (elansc_pcinmi)
999 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB;
1000 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP,
1001 pcihostmap);
1002
1003 elanpex_intr_ack(sc->sc_memt, sc->sc_memh);
1004
1005 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL);
1006 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL);
1007 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL);
1008
1009 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB;
1010
1011 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB;
1012 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB;
1013 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB;
1014 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB;
1015 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB;
1016 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB;
1017
1018 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB;
1019 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB;
1020 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB;
1021
1022 if (elansc_pcinmi) {
1023 sc->sc_eih = nmi_establish(elanpex_nmi, sc);
1024
1025 /* Activate NMI instead of maskable interrupts for
1026 * all PCI exceptions:
1027 */
1028 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL;
1029 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL;
1030 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL;
1031 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL;
1032 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL;
1033 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL;
1034
1035 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL;
1036 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL;
1037 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL;
1038 } else
1039 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc);
1040
1041 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl);
1042 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq);
1043 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq);
1044 }
1045
1046 static void
1047 elanpex_attach(device_t parent, device_t self, void *aux)
1048 {
1049 struct elansc_softc *sc = device_private(parent);
1050
1051 aprint_naive(": PCI Exceptions\n");
1052 aprint_normal(": AMD Elan SC520 PCI Exceptions\n");
1053
1054 elanpex_intr_establish(self, sc);
1055
1056 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n",
1057 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL));
1058
1059 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n",
1060 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL));
1061
1062 aprint_debug_dev(self, "PCIHOSTMAP %04x\n",
1063 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP));
1064
1065 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
1066 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) |
1067 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE);
1068
1069 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume,
1070 elanpex_shutdown))
1071 aprint_error_dev(self, "could not establish power hooks\n");
1072 }
1073
1074 static bool
1075 elanpex_shutdown(device_t self, int flags)
1076 {
1077 struct elansc_softc *sc = device_private(device_parent(self));
1078 uint8_t sysarbctl;
1079 uint16_t pcihostmap, mstirq, tgtirq;
1080
1081 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL);
1082 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB;
1083 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl);
1084
1085 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL);
1086 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB;
1087 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB;
1088 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB;
1089 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB;
1090 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB;
1091 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB;
1092 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq);
1093
1094 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL);
1095 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB;
1096 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB;
1097 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB;
1098 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq);
1099
1100 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh,
1101 MMCR_PCIHOSTMAP);
1102 /* Priority P2 (Master PIC IR1) */
1103 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP;
1104 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP,
1105 pcihostmap);
1106
1107 return true;
1108 }
1109
1110 static void
1111 elanpex_intr_disestablish(struct elansc_softc *sc)
1112 {
1113 elanpex_shutdown(sc->sc_pex, 0);
1114
1115 if (elansc_pcinmi)
1116 nmi_disestablish(sc->sc_eih);
1117 else
1118 intr_disestablish(sc->sc_eih);
1119 sc->sc_eih = NULL;
1120
1121 }
1122
1123 static int
1124 elanpex_detach(device_t self, int flags)
1125 {
1126 struct elansc_softc *sc = device_private(device_parent(self));
1127
1128 pmf_device_deregister(self);
1129 elanpex_intr_disestablish(sc);
1130
1131 return 0;
1132 }
1133
1134 static void
1135 elanpar_intr_establish(device_t self, struct elansc_softc *sc)
1136 {
1137 uint8_t adddecctl, wpvmap;
1138
1139 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP);
1140 wpvmap &= ~MMCR_WPVMAP_INT_MAP;
1141 if (elansc_wpvnmi)
1142 wpvmap |= MMCR_WPVMAP_INT_NMI;
1143 else
1144 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP);
1145 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap);
1146
1147 /* clear interrupt status */
1148 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
1149 MMCR_WPVSTA_WPV_STA);
1150
1151 /* establish interrupt */
1152 if (elansc_wpvnmi)
1153 sc->sc_pih = nmi_establish(elanpar_nmi, sc);
1154 else
1155 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc);
1156
1157 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL);
1158 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB;
1159 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl);
1160 }
1161
1162 static bool
1163 elanpar_shutdown(device_t self, int flags)
1164 {
1165 int i;
1166 struct elansc_softc *sc = device_private(device_parent(self));
1167
1168 for (i = 0; i < __arraycount(sc->sc_textpar); i++) {
1169 if (sc->sc_textpar[i] == -1)
1170 continue;
1171 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]);
1172 sc->sc_textpar[i] = -1;
1173 }
1174 if (sc->sc_pg0par != -1) {
1175 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par);
1176 sc->sc_pg0par = -1;
1177 }
1178 return true;
1179 }
1180
1181 static void
1182 elanpar_deferred_attach(device_t self)
1183 {
1184 struct elansc_softc *sc = device_private(device_parent(self));
1185
1186 elansc_protect_text(self, sc);
1187 }
1188
1189 static void
1190 elanpar_attach(device_t parent, device_t self, void *aux)
1191 {
1192 struct elansc_softc *sc = device_private(parent);
1193
1194 aprint_naive(": Programmable Address Regions\n");
1195 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n");
1196
1197 elansc_print_1(self, sc, MMCR_WPVMAP);
1198 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh);
1199
1200 sc->sc_pg0par = elansc_protect_pg0(self, sc);
1201 /* XXX grotty hack to avoid trapping writes by x86_patch()
1202 * to the kernel text on a MULTIPROCESSOR kernel.
1203 */
1204 config_interrupts(self, elanpar_deferred_attach);
1205
1206 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh);
1207
1208 elanpar_intr_establish(self, sc);
1209
1210 elansc_print_1(self, sc, MMCR_ADDDECCTL);
1211
1212 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume,
1213 elanpar_shutdown))
1214 aprint_error_dev(self, "could not establish power hooks\n");
1215 }
1216
1217 static void
1218 elanpar_intr_disestablish(struct elansc_softc *sc)
1219 {
1220 uint8_t adddecctl, wpvmap;
1221
1222 /* disable interrupt, acknowledge it, disestablish our
1223 * handler, unmap it
1224 */
1225 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL);
1226 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB;
1227 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl);
1228
1229 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA,
1230 MMCR_WPVSTA_WPV_STA);
1231
1232 if (elansc_wpvnmi)
1233 nmi_disestablish(sc->sc_pih);
1234 else
1235 intr_disestablish(sc->sc_pih);
1236 sc->sc_pih = NULL;
1237
1238 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP);
1239 wpvmap &= ~MMCR_WPVMAP_INT_MAP;
1240 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap);
1241 }
1242
1243 static int
1244 elanpar_detach(device_t self, int flags)
1245 {
1246 struct elansc_softc *sc = device_private(device_parent(self));
1247
1248 pmf_device_deregister(self);
1249
1250 elanpar_shutdown(self, 0);
1251
1252 elanpar_intr_disestablish(sc);
1253
1254 return 0;
1255 }
1256
1257 static void
1258 elansc_attach(device_t parent, device_t self, void *aux)
1259 {
1260 struct elansc_softc *sc = device_private(self);
1261 struct pcibus_attach_args *pba = aux;
1262 uint16_t rev;
1263 uint8_t cpuctl, picicr, ressta;
1264 #if NGPIO > 0
1265 int pin, reg, shift;
1266 uint16_t data;
1267 #endif
1268
1269 sc->sc_dev = self;
1270
1271 sc->sc_pc = pba->pba_pc;
1272 sc->sc_pciflags = pba->pba_flags;
1273 sc->sc_dmat = pba->pba_dmat;
1274 sc->sc_dmat64 = pba->pba_dmat64;
1275 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0);
1276
1277 aprint_naive(": System Controller\n");
1278 aprint_normal(": AMD Elan SC520 System Controller\n");
1279
1280 sc->sc_iot = pba->pba_iot;
1281 sc->sc_memt = pba->pba_memt;
1282 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0,
1283 &sc->sc_memh) != 0) {
1284 aprint_error_dev(sc->sc_dev, "unable to map registers\n");
1285 return;
1286 }
1287
1288 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH);
1289
1290 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID);
1291 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL);
1292
1293 aprint_normal_dev(sc->sc_dev,
1294 "product %d stepping %d.%d, CPU clock %s\n",
1295 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT,
1296 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT,
1297 (rev & REVID_MINSTEP),
1298 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]);
1299
1300 /*
1301 * SC520 rev A1 has a bug that affects the watchdog timer. If
1302 * the GP bus echo mode is enabled, writing to the watchdog control
1303 * register is blocked.
1304 *
1305 * The BIOS in some systems (e.g. the Soekris net4501) enables
1306 * GP bus echo for various reasons, so we need to switch it off
1307 * when we talk to the watchdog timer.
1308 *
1309 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this
1310 * XXX problem, so we'll just enable it for all Elan SC520s
1311 * XXX for now. --thorpej@NetBSD.org
1312 */
1313 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) |
1314 (0 << REVID_MAJSTEP_SHIFT) | (1)))
1315 sc->sc_echobug = 1;
1316
1317 /*
1318 * Determine cause of the last reset, and issue a warning if it
1319 * was due to watchdog expiry.
1320 */
1321 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA);
1322 if (ressta & RESSTA_WDT_RST_DET)
1323 aprint_error_dev(sc->sc_dev,
1324 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n");
1325 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta);
1326
1327 elansc_print_1(self, sc, MMCR_MPICMODE);
1328 elansc_print_1(self, sc, MMCR_SL1PICMODE);
1329 elansc_print_1(self, sc, MMCR_SL2PICMODE);
1330 elansc_print_1(self, sc, MMCR_PICICR);
1331
1332 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh,
1333 MMCR_MPICMODE);
1334 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE,
1335 sc->sc_mpicmode | __BIT(ELAN_IRQ));
1336
1337 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR);
1338 picicr = sc->sc_picicr;
1339 if (elansc_pcinmi || elansc_wpvnmi)
1340 picicr |= MMCR_PICICR_NMI_ENB;
1341 #if 0
1342 /* PC/AT compatibility */
1343 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE;
1344 #endif
1345 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr);
1346
1347 elansc_print_1(self, sc, MMCR_PICICR);
1348 elansc_print_1(self, sc, MMCR_MPICMODE);
1349
1350 mutex_enter(&sc->sc_mtx);
1351 /* Set up the watchdog registers with some defaults. */
1352 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30);
1353
1354 /* ...and clear it. */
1355 elansc_wdogctl_reset(sc);
1356 mutex_exit(&sc->sc_mtx);
1357
1358 if (!pmf_device_register1(self, elansc_suspend, elansc_resume,
1359 elansc_shutdown))
1360 aprint_error_dev(self, "could not establish power hooks\n");
1361
1362 #if NGPIO > 0
1363 /* Initialize GPIO pins array */
1364 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) {
1365 sc->sc_gpio_pins[pin].pin_num = pin;
1366 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT |
1367 GPIO_PIN_OUTPUT;
1368
1369 /* Read initial state */
1370 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
1371 shift = pin % 16;
1372 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
1373 if ((data & (1 << shift)) == 0)
1374 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT;
1375 else
1376 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT;
1377 if (elansc_gpio_pin_read(sc, pin) == 0)
1378 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW;
1379 else
1380 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH;
1381 }
1382
1383 /* Create controller tag */
1384 sc->sc_gpio_gc.gp_cookie = sc;
1385 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read;
1386 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write;
1387 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl;
1388
1389 #endif /* NGPIO */
1390
1391 elansc_rescan(sc->sc_dev, "elanparbus", NULL);
1392 elansc_rescan(sc->sc_dev, "elanpexbus", NULL);
1393 elansc_rescan(sc->sc_dev, "gpiobus", NULL);
1394
1395 /*
1396 * Hook up the watchdog timer.
1397 */
1398 sc->sc_smw.smw_name = device_xname(sc->sc_dev);
1399 sc->sc_smw.smw_cookie = sc;
1400 sc->sc_smw.smw_setmode = elansc_wdog_setmode;
1401 sc->sc_smw.smw_tickle = elansc_wdog_tickle;
1402 sc->sc_smw.smw_period = 32; /* actually 32.54 */
1403 if (sysmon_wdog_register(&sc->sc_smw) != 0) {
1404 aprint_error_dev(sc->sc_dev,
1405 "unable to register watchdog with sysmon\n");
1406 }
1407 elansc_attached = true;
1408 elansc_rescan(sc->sc_dev, "pcibus", NULL);
1409 }
1410
1411 static int
1412 elanpex_match(device_t parent, cfdata_t match, void *aux)
1413 {
1414 struct elansc_softc *sc = device_private(parent);
1415
1416 return sc->sc_pex == NULL;
1417 }
1418
1419 static int
1420 elanpar_match(device_t parent, cfdata_t match, void *aux)
1421 {
1422 struct elansc_softc *sc = device_private(parent);
1423
1424 return sc->sc_par == NULL;
1425 }
1426
1427 /* scan for new children */
1428 static int
1429 elansc_rescan(device_t self, const char *ifattr, const int *locators)
1430 {
1431 struct elansc_softc *sc = device_private(self);
1432
1433 if (ifattr_match(ifattr, "elanparbus") && sc->sc_par == NULL) {
1434 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL,
1435 NULL);
1436 }
1437
1438 if (ifattr_match(ifattr, "elanpexbus") && sc->sc_pex == NULL) {
1439 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL,
1440 NULL);
1441 }
1442
1443 if (ifattr_match(ifattr, "gpiobus") && sc->sc_gpio == NULL) {
1444 #if NGPIO > 0
1445 struct gpiobus_attach_args gba;
1446
1447 memset(&gba, 0, sizeof(gba));
1448
1449 gba.gba_gc = &sc->sc_gpio_gc;
1450 gba.gba_pins = sc->sc_gpio_pins;
1451 gba.gba_npins = ELANSC_PIO_NPINS;
1452 sc->sc_gpio = config_found_ia(sc->sc_dev, "gpiobus", &gba,
1453 gpiobus_print);
1454 #endif
1455 }
1456
1457 if (ifattr_match(ifattr, "pcibus") && sc->sc_pci == NULL) {
1458 struct pcibus_attach_args pba;
1459
1460 memset(&pba, 0, sizeof(pba));
1461 pba.pba_iot = sc->sc_iot;
1462 pba.pba_memt = sc->sc_memt;
1463 pba.pba_dmat = sc->sc_dmat;
1464 pba.pba_dmat64 = sc->sc_dmat64;
1465 pba.pba_pc = sc->sc_pc;
1466 pba.pba_flags = sc->sc_pciflags;
1467 pba.pba_bus = 0;
1468 pba.pba_bridgetag = NULL;
1469 sc->sc_pci = config_found_ia(self, "pcibus", &pba, pcibusprint);
1470 }
1471
1472 return 0;
1473 }
1474
1475 CFATTACH_DECL3_NEW(elanpar, 0,
1476 elanpar_match, elanpar_attach, elanpar_detach, NULL, NULL, NULL,
1477 DVF_DETACH_SHUTDOWN);
1478
1479 CFATTACH_DECL3_NEW(elanpex, 0,
1480 elanpex_match, elanpex_attach, elanpex_detach, NULL, NULL, NULL,
1481 DVF_DETACH_SHUTDOWN);
1482
1483 CFATTACH_DECL3_NEW(elansc, sizeof(struct elansc_softc),
1484 elansc_match, elansc_attach, elansc_detach, NULL, elansc_rescan,
1485 elansc_childdetached, DVF_DETACH_SHUTDOWN);
1486
1487 #if NGPIO > 0
1488 static int
1489 elansc_gpio_pin_read(void *arg, int pin)
1490 {
1491 struct elansc_softc *sc = arg;
1492 int reg, shift;
1493 uint16_t data;
1494
1495 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
1496 shift = pin % 16;
1497
1498 mutex_enter(&sc->sc_mtx);
1499 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
1500 mutex_exit(&sc->sc_mtx);
1501
1502 return ((data >> shift) & 0x1);
1503 }
1504
1505 static void
1506 elansc_gpio_pin_write(void *arg, int pin, int value)
1507 {
1508 struct elansc_softc *sc = arg;
1509 int reg, shift;
1510 uint16_t data;
1511
1512 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);
1513 shift = pin % 16;
1514
1515 mutex_enter(&sc->sc_mtx);
1516 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
1517 if (value == 0)
1518 data &= ~(1 << shift);
1519 else if (value == 1)
1520 data |= (1 << shift);
1521
1522 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
1523 mutex_exit(&sc->sc_mtx);
1524 }
1525
1526 static void
1527 elansc_gpio_pin_ctl(void *arg, int pin, int flags)
1528 {
1529 struct elansc_softc *sc = arg;
1530 int reg, shift;
1531 uint16_t data;
1532
1533 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);
1534 shift = pin % 16;
1535 mutex_enter(&sc->sc_mtx);
1536 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);
1537 if (flags & GPIO_PIN_INPUT)
1538 data &= ~(1 << shift);
1539 if (flags & GPIO_PIN_OUTPUT)
1540 data |= (1 << shift);
1541
1542 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);
1543 mutex_exit(&sc->sc_mtx);
1544 }
1545 #endif /* NGPIO */
NetBSD on the FriendlyARM MINI2440