sys/arch/i386/pci/elan520reg.h

   1 /*      $NetBSD: elan520reg.h,v 1.9 2008/01/07 08:01:45 dyoung Exp $    */
   2
   3 /*-
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Register definitions for the AMD Elan SC520 System Controller.
  34  */
  35
  36 #ifndef _I386_PCI_ELAN520REG_H_
  37 #define _I386_PCI_ELAN520REG_H_
  38
  39 #include <sys/cdefs.h>
  40
  41 #define MMCR_BASE_ADDR          0xfffef000
  42
  43 /*
  44  * Am5x86 CPU Registers.
  45  */
  46 #define MMCR_REVID              0x0000
  47 #define MMCR_CPUCTL             0x0002
  48
  49 #define REVID_PRODID            0xff00  /* product ID */
  50 #define REVID_PRODID_SHIFT      8
  51 #define REVID_MAJSTEP           0x00f0  /* stepping major */
  52 #define REVID_MAJSTEP_SHIFT     4
  53 #define REVID_MINSTEP           0x000f  /* stepping minor */
  54
  55 #define PRODID_ELAN_SC520       0x00    /* Elan SC520 */
  56
  57 #define CPUCTL_CPU_CLK_SPD_MASK 0x03    /* CPU clock speed */
  58 #define CPUCTL_CACHE_WR_MODE    0x10    /* cache mode (0 = wb, 1 = wt) */
  59
  60 /*
  61  * Performance Registers
  62  */
  63 #define MMCR_DBCTL      0x0040  /* SDRAM Buffer Control */
  64
  65 #define MMCR_DBCTL_RAB_ENB      __BIT(4)        /* enable read-ahead */
  66 #define MMCR_DBCTL_WB_WM_MASK   __BITS(3,2)     /* write buffer watermark */
  67 #define MMCR_DBCTL_WB_WM_28DW   __SHIFTIN(0, MMCR_DBCTL_WB_WM_MASK)
  68 #define MMCR_DBCTL_WB_WM_24DW   __SHIFTIN(1, MMCR_DBCTL_WB_WM_MASK)
  69 #define MMCR_DBCTL_WB_WM_16DW   __SHIFTIN(2, MMCR_DBCTL_WB_WM_MASK)
  70 #define MMCR_DBCTL_WB_WM_8DW    __SHIFTIN(3, MMCR_DBCTL_WB_WM_MASK)
  71 #define MMCR_DBCTL_WB_FLUSH     __BIT(1)        /* write 1 to flush wr buf */
  72 #define MMCR_DBCTL_WB_ENB       __BIT(0)        /* enable write buffer */
  73 #define MMCR_HBCTL      0x0060  /* Host Bridge Control */
  74 #define MMCR_HBCTL_PCI_RST              __BIT(15)
  75 #define MMCR_HBCTL_T_PURGE_RD_ENB       __BIT(10)
  76 #define MMCR_HBCTL_T_DLYTR_ENB_MASK     __BITS(9,8)
  77 #define MMCR_HBCTL_T_DLYTR_ENB_WAIT     \
  78     __SHIFTIN(0, MMCR_HBCTL_T_DLYTR_ENB_MASK)
  79 #define MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY\
  80     __SHIFTIN(1, MMCR_HBCTL_T_DLYTR_ENB_MASK)
  81 #define MMCR_HBCTL_T_DLYTR_ENB_RSVD0    \
  82     __SHIFTIN(2, MMCR_HBCTL_T_DLYTR_ENB_MASK)
  83 #define MMCR_HBCTL_T_DLYTR_ENB_RSVD1    \
  84     __SHIFTIN(3, MMCR_HBCTL_T_DLYTR_ENB_MASK)
  85 #define MMCR_HBCTL_M_WPOST_ENB          __BIT(3)
  86 #define MMCR_SYSARBCTL  0x0070  /* System Arbiter Control */
  87 #define MMCR_SYSARBCTL_CNCR_MODE_ENB    __BIT(1)
  88 #define MMCR_SYSARBCTL_GNT_TO_INT_ENB   __BIT(0)        /* 1: interrupt when the
  89                                                          * PCI bus arbiter
  90                                                          * detects a time-out
  91                                                          */
  92
  93 #define MMCR_PCIARBSTA  0x71    /* PCI Bus Arbiter Status */
  94 #define MMCR_PCIARBSTA_GNT_TO_STA       __BIT(7)
  95 #define MMCR_PCIARBSTA_GNT_TO_ID        __BITS(3, 0)
  96
  97 /*
  98  * PCI Host Bridge Registers
  99  */
 100 #define MMCR_HBMSTIRQCTL        0x66    /* Host Bridge Master Interrupt Ctrl */
 101
 102 #define MMCR_HBMSTIRQCTL_RSVD0                  __BITS(15, 14)
 103
 104 /* Interrupt Selects
 105  *
 106  * 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
 107  * 1: generate NMI
 108  */
 109 /* Master Retry Time-Out */
 110 #define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL        __BIT(13)
 111 /* Master Target Abort */
 112 #define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL        __BIT(12)
 113 /* Master Abort */
 114 #define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL        __BIT(11)
 115 /* Master System Error */
 116 #define MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL         __BIT(10)
 117 /* Master Received PERR */
 118 #define MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL         __BIT(9)
 119 /* Master Detected PERR */
 120 #define MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL         __BIT(8)
 121 #define MMCR_HBMSTIRQCTL_RSVD1                  __BITS(7, 6)
 122
 123 /* Interrupt Enables */
 124 /* Master Retry Time-Out */
 125 #define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB        __BIT(5)
 126 /* Master Target Abort */
 127 #define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB        __BIT(4)
 128 /* Master Abort */
 129 #define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB        __BIT(3)
 130 /* Master System Error */
 131 #define MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB         __BIT(2)
 132 /* Master Received PERR */
 133 #define MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB         __BIT(1)
 134 /* Master Detected PERR */
 135 #define MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB         __BIT(0)
 136
 137 /* Host Bridge Target Interrupt Ctrl.  16 bits. */
 138 #define MMCR_HBTGTIRQCTL        0x62
 139
 140 #define MMCR_HBTGTIRQCTL_RSVD0                  __BITS(15, 11)
 141
 142 /* Interrupt Selects
 143  *
 144  * 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
 145  * 1: generate NMI
 146  */
 147 #define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL        __BIT(10)
 148 #define MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL         __BIT(9)
 149 #define MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL         __BIT(8)
 150 #define MMCR_HBTGTIRQCTL_RSVD1                  __BITS(7, 3)
 151
 152 /* Interrupt Enables */
 153 /* Target Delayed Transaction Time-out */
 154 #define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB        __BIT(2)
 155 /* Target Address Parity */
 156 #define MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB         __BIT(1)
 157 /* Target Data Parity */
 158 #define MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB         __BIT(0)
 159
 160 /* Host Bridge Master Interrupt Status.  16 bits. */
 161 #define MMCR_HBMSTIRQSTA        0x68
 162
 163 /* Host Bridge Master Interrupt Address */
 164 #define MMCR_MSTINTADD          0x6c
 165
 166 #define MMCR_HBMSTIRQSTA_RSVD0                  __BITS(15, 12)
 167 #define MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID           __BITS(11, 8)
 168 #define MMCR_HBMSTIRQSTA_RSVD1                  __BITS(7, 6)
 169 #define MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA        __BIT(5)
 170 #define MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA        __BIT(4)
 171 #define MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA        __BIT(3)
 172 #define MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA         __BIT(2)
 173 #define MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA         __BIT(1)
 174 #define MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA         __BIT(0)
 175
 176 /* The PCI master interrupts that NetBSD is interested in. */
 177 #define MMCR_MSTIRQ_ACT (MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB |\
 178                          MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB |\
 179                          MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB |\
 180                          MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB |\
 181                          MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB |\
 182                          MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB)
 183
 184 /* Host Bridge Target Interrupt Status.  16 bits. */
 185 #define MMCR_HBTGTIRQSTA        0x64
 186
 187 #define MMCR_HBTGTIRQSTA_RSVD0                  __BITS(15, 12)
 188 /* Target Interrupt Identification */
 189 #define MMCR_HBTGTIRQSTA_T_IRQ_ID               __BITS(11, 8)
 190 #define MMCR_HBTGTIRQSTA_RSVD1                  __BITS(7, 3)
 191 /* Status bits.  Write 1 to clear. */
 192 #define MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA        __BIT(2)
 193 #define MMCR_HBTGTIRQSTA_T_APER_IRQ_STA         __BIT(1)
 194 #define MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA         __BIT(0)
 195
 196 /* The PCI target interrupts that NetBSD is interested in. */
 197 #define MMCR_TGTIRQ_ACT (MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA |\
 198                          MMCR_HBTGTIRQSTA_T_APER_IRQ_STA |\
 199                          MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA)
 200
 201 #define MMCR_PCIHOSTMAP 0x0d14  /* PCI Host Bridge Interrupt Mapping */
 202
 203 #define MMCR_PCIHOSTMAP_PCI_NMI_ENB     __BIT(8)
 204 #define MMCR_PCIHOSTMAP_PCI_IRQ_MAP     __BITS(4, 0)
 205
 206 /* Programmable Interrupt Controller.  8 bits. */
 207 #define MMCR_PICICR                     0xd00
 208 #define MMCR_PICICR_NMI_DONE            __BIT(7)
 209 #define MMCR_PICICR_NMI_ENB             __BIT(6)
 210 #define MMCR_PICICR_RSVD0               __BITS(5, 3)
 211 #define MMCR_PICICR_S2_GINT_MODE        __BIT(2)
 212 #define MMCR_PICICR_S1_GINT_MODE        __BIT(1)
 213 #define MMCR_PICICR_M_GINT_MODE         __BIT(0)
 214
 215 #define MMCR_MPICMODE           0xd02
 216 #define MMCR_SL1PICMODE         0xd03
 217 #define MMCR_SL2PICMODE         0xd04
 218
 219 #define MMCR_WPVMAP             0xd44
 220 #define MMCR_WPVMAP_RSVD0       __BITS(7, 5)
 221 /* map write-protection violations to an Elan SC520 interrupt priority,
 222  * 1 through 22
 223  */
 224 #define MMCR_WPVMAP_INT_MAP     __BITS(4, 0)
 225 /* no bits set -> disable */
 226 #define MMCR_WPVMAP_INT_OFF     0
 227 /* all bits set -> NMI */
 228 #define MMCR_WPVMAP_INT_NMI     MMCR_WPVMAP_INT_MAP
 229
 230 #define MMCR_ADDDECCTL          0x80
 231 #define MMCR_ADDDECCTL_WPV_INT_ENB      __BIT(7)
 232
 233 #define MMCR_WPVSTA             0x82
 234 #define MMCR_WPVSTA_WPV_STA             __BIT(15)
 235 #define MMCR_WPVSTA_WPV_RSVD0           __BITS(14, 10)
 236 #define MMCR_WPVSTA_WPV_MSTR            __BITS(9, 8)
 237 #define MMCR_WPVSTA_WPV_MSTR_CPU        __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR)
 238 #define MMCR_WPVSTA_WPV_MSTR_PCI        __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR)
 239 #define MMCR_WPVSTA_WPV_MSTR_GP         __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR)
 240 #define MMCR_WPVSTA_WPV_MSTR_RSVD       __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR)
 241 #define MMCR_WPVSTA_WPV_RSVD1           __BITS(7, 4)
 242 #define MMCR_WPVSTA_WPV_WINDOW          __BITS(3, 0)
 243
 244 #define MMCR_PAR(__i)           (0x88 + 4 * (__i))
 245 #define MMCR_PAR_TARGET         __BITS(31, 29)
 246 #define MMCR_PAR_TARGET_OFF     __SHIFTIN(0, MMCR_PAR_TARGET)
 247 #define MMCR_PAR_TARGET_GPIO    __SHIFTIN(1, MMCR_PAR_TARGET)
 248 #define MMCR_PAR_TARGET_GPMEM   __SHIFTIN(2, MMCR_PAR_TARGET)
 249 #define MMCR_PAR_TARGET_PCI     __SHIFTIN(3, MMCR_PAR_TARGET)
 250 #define MMCR_PAR_TARGET_BOOTCS  __SHIFTIN(4, MMCR_PAR_TARGET)
 251 #define MMCR_PAR_TARGET_ROMCS1  __SHIFTIN(5, MMCR_PAR_TARGET)
 252 #define MMCR_PAR_TARGET_ROMCS2  __SHIFTIN(6, MMCR_PAR_TARGET)
 253 #define MMCR_PAR_TARGET_SDRAM   __SHIFTIN(7, MMCR_PAR_TARGET)
 254 #define MMCR_PAR_ATTR           __BITS(28, 26)
 255 #define MMCR_PAR_ATTR_NOEXEC    __SHIFTIN(__BIT(2), MMCR_PAR_ATTR)
 256 #define MMCR_PAR_ATTR_NOCACHE   __SHIFTIN(__BIT(1), MMCR_PAR_ATTR)
 257 #define MMCR_PAR_ATTR_NOWRITE   __SHIFTIN(__BIT(0), MMCR_PAR_ATTR)
 258 #define MMCR_PAR_PG_SZ          __BIT(25)
 259 #define MMCR_PAR_SZ_ST_ADR      __BITS(24, 0)
 260 #define MMCR_PAR_4KB_SZ         __BITS(24, 18)
 261 #define MMCR_PAR_4KB_ST_ADR     __BITS(17, 0)
 262 #define MMCR_PAR_64KB_SZ        __BITS(24, 14)
 263 #define MMCR_PAR_64KB_ST_ADR    __BITS(13, 0)
 264 #define MMCR_PAR_IO_SZ          __BITS(24, 16)
 265 #define MMCR_PAR_IO_ST_ADR      __BITS(15, 0)
 266
 267 /*
 268  * General Purpose Bus Registers
 269  */
 270 #define MMCR_GPECHO             0x0c00  /* GP echo mode */
 271 #define MMCR_GPCSDW             0x0c01  /* GP chip sel data width */
 272 #define MMCR_CPCSQUAL           0x0c02  /* GP chip sel qualification */
 273 #define MMCR_GPCSRT             0x0c08  /* GP chip sel recovery time */
 274 #define MMCR_GPCSPW             0x0c09  /* GP chip sel pulse width */
 275 #define MMCR_GPCSOFF            0x0c0a  /* GP chip sel offset */
 276 #define MMCR_GPRDW              0x0c0b  /* GP read pulse width */
 277 #define MMCR_GPRDOFF            0x0c0c  /* GP read offset */
 278 #define MMCR_GPWRW              0x0c0d  /* GP write pulse width */
 279 #define MMCR_GPWROFF            0x0c0e  /* GP write offset */
 280 #define MMCR_GPALEW             0x0c0f  /* GPALE pulse width */
 281 #define MMCR_GPALEOFF           0x0c10  /* GPALE offset */
 282
 283 #define GPECHO_GP_ECHO_ENB      0x01    /* GP bus echo mode enable */
 284
 285 /*
 286  * Programmable Input/Output Registers
 287  */
 288 #define MMCR_PIOPFS15_0         0x0c20  /* PIO15-PIO0 pin func sel */
 289 #define MMCR_PIOPFS31_16        0x0c22  /* PIO31-PIO16 pin func sel */
 290 #define MMCR_CSPFS              0x0c24  /* chip sel pin func sel */
 291 #define MMCR_CLKSEL             0x0c26  /* clock select */
 292 #define MMCR_DSCTL              0x0c28  /* drive strength control */
 293 #define MMCR_PIODIR15_0         0x0c2a  /* PIO15-PIO0 direction */
 294 #define MMCR_PIODIR31_16        0x0c2c  /* PIO31-PIO16 direction */
 295 #define MMCR_PIODATA15_0        0x0c30  /* PIO15-PIO0 data */
 296 #define MMCR_PIODATA31_16       0x0c32  /* PIO31-PIO16 data */
 297 #define MMCR_PIOSET15_0         0x0c34  /* PIO15-PIO0 set */
 298 #define MMCR_PIOSET31_16        0x0c36  /* PIO31-PIO16 set */
 299 #define MMCR_PIOCLR15_0         0x0c38  /* PIO15-PIO0 clear */
 300 #define MMCR_PIOCLR31_16        0x0c3a  /* PIO31-PIO16 clear */
 301
 302 #define ELANSC_PIO_NPINS        32      /* total number of PIO pins */
 303
 304 /*
 305  * Watchdog Timer Registers.
 306  */
 307 #define MMCR_WDTMRCTL           0x0cb0  /* watchdog timer control */
 308 #define MMCR_WDTMRCNTL          0x0cb2  /* watchdog timer count low */
 309 #define MMCR_WDTMRCNTH          0x0cb4  /* watchdog timer count high */
 310
 311 #define WDTMRCTL_EXP_SEL_MASK   0x00ff  /* exponent select */
 312 #define WDTMRCTL_EXP_SEL14      0x0001  /*      496us/492us */
 313 #define WDTMRCTL_EXP_SEL24      0x0002  /*      508ms/503ms */
 314 #define WDTMRCTL_EXP_SEL25      0x0004  /*      1.02s/1.01s */
 315 #define WDTMRCTL_EXP_SEL26      0x0008  /*      2.03s/2.01s */
 316 #define WDTMRCTL_EXP_SEL27      0x0010  /*      4.07s/4.03s */
 317 #define WDTMRCTL_EXP_SEL28      0x0020  /*      8.13s/8.05s */
 318 #define WDTMRCTL_EXP_SEL29      0x0040  /*      16.27s/16.11s */
 319 #define WDTMRCTL_EXP_SEL30      0x0080  /*      32.54s/32.21s */
 320 #define WDTMRCTL_IRQ_FLG        0x1000  /* interrupt request */
 321 #define WDTMRCTL_WRST_ENB       0x4000  /* watchdog timer reset enable */
 322 #define WDTMRCTL_ENB            0x8000  /* watchdog timer enable */
 323
 324 #define WDTMRCTL_UNLOCK1        0x3333
 325 #define WDTMRCTL_UNLOCK2        0xcccc
 326
 327 #define WDTMRCTL_RESET1         0xaaaa
 328 #define WDTMRCTL_RESET2         0x5555
 329
 330 /*
 331  * Reset Generation Registers.
 332  */
 333 #define MMCR_SYSINFO            0x0d70  /* system board information */
 334 #define MMCR_RESCFG             0x0d72  /* reset configuration */
 335 #define MMCR_RESSTA             0x0d74  /* reset status */
 336
 337 #define RESCFG_SYS_RST          0x01    /* software system reset */
 338 #define RESCFG_GP_RST           0x02    /* assert GP bus reset */
 339 #define RESCFG_PRG_RST_ENB      0x04    /* programmable reset enable */
 340 #define RESCFG_ICE_ON_RST       0x08    /* enter AMDebug(tm) on reset */
 341
 342 #define RESSTA_PWRGOOD_DET      0x01    /* POWERGOOD reset detect */
 343 #define RESSTA_PRGRST_DET       0x02    /* programmable reset detect */
 344 #define RESSTA_SD_RST_DET       0x04    /* CPU shutdown reset detect */
 345 #define RESSTA_WDT_RST_DET      0x08    /* watchdog timer reset detect */
 346 #define RESSTA_ICE_SRST_DET     0x10    /* AMDebug(tm) soft reset detect */
 347 #define RESSTA_ICE_HRST_DET     0x20    /* AMDebug(tm) soft reset detect */
 348 #define RESSTA_SCP_RST          0x40    /* SCP reset detect */
 349
 350 #endif /* _I386_PCI_ELAN520REG_H_ */