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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / arch / i386 / pci / pci_intr_fixup.c
blobc1adb8f5b4a4daedf0f5459c2c665e88a78d9687
1 /* $NetBSD: pci_intr_fixup.c,v 1.46 2006/12/10 04:16:46 uwe Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1999, by UCHIYAMA Yasushi
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. The name of the developer may NOT be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58 /*
59 * PCI Interrupt Router support.
60 */
61
62 #include <sys/cdefs.h>
63 __KERNEL_RCSID(0, "$NetBSD: pci_intr_fixup.c,v 1.46 2006/12/10 04:16:46 uwe Exp $");
64
65 #include "opt_pcibios.h"
66 #include "opt_pcifixup.h"
67
68 #include <sys/param.h>
69 #include <sys/systm.h>
70 #include <sys/kernel.h>
71 #include <sys/malloc.h>
72 #include <sys/queue.h>
73 #include <sys/device.h>
74
75 #include <machine/bus.h>
76 #include <machine/intr.h>
77
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcidevs.h>
81
82 #include <i386/pci/pci_intr_fixup.h>
83 #include <i386/pci/pcibios.h>
84
85 struct pciintr_link_map {
86 int link;
87 int clink;
88 int irq;
89 uint16_t bitmap;
90 int fixup_stage;
91 SIMPLEQ_ENTRY(pciintr_link_map) list;
92 };
93
94 pciintr_icu_tag_t pciintr_icu_tag;
95 pciintr_icu_handle_t pciintr_icu_handle;
96
97 #ifdef PCIBIOS_IRQS_HINT
98 int pcibios_irqs_hint = PCIBIOS_IRQS_HINT;
99 #endif
100
101 struct pciintr_link_map *pciintr_link_lookup(int);
102 struct pciintr_link_map *pciintr_link_alloc(struct pcibios_intr_routing *,
103 int);
104 struct pcibios_intr_routing *pciintr_pir_lookup(int, int);
105 static int pciintr_bitmap_count_irq(int, int *);
106 static int pciintr_bitmap_find_lowest_irq(int, int *);
107 int pciintr_link_init (void);
108 #ifdef PCIBIOS_INTR_GUESS
109 int pciintr_guess_irq(void);
110 #endif
111 int pciintr_link_fixup(void);
112 int pciintr_link_route(uint16_t *);
113 int pciintr_irq_release(uint16_t *);
114 int pciintr_header_fixup(pci_chipset_tag_t);
115 void pciintr_do_header_fixup(pci_chipset_tag_t, pcitag_t, void*);
116
117 SIMPLEQ_HEAD(, pciintr_link_map) pciintr_link_map_list;
118
119 const struct pciintr_icu_table {
120 pci_vendor_id_t piit_vendor;
121 pci_product_id_t piit_product;
122 int (*piit_init)(pci_chipset_tag_t,
123 bus_space_tag_t, pcitag_t, pciintr_icu_tag_t *,
124 pciintr_icu_handle_t *);
125 void (*piit_uninit)(pciintr_icu_handle_t);
126 } pciintr_icu_table[] = {
127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371MX,
128 piix_init, piix_uninit },
129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371AB_ISA,
130 piix_init, piix_uninit },
131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371FB_ISA,
132 piix_init, piix_uninit },
133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82371SB_ISA,
134 piix_init, piix_uninit },
135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ISA,
136 piix_init, piix_uninit },
137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_LPC,
138 piix_init, piix_uninit }, /* ICH */
139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_LPC,
140 piix_init, piix_uninit }, /* ICH0 */
141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LPC,
142 ich_init, NULL }, /* ICH2 */
143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BAM_LPC,
144 ich_init, NULL }, /* ICH2M */
145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_LPC,
146 ich_init, NULL }, /* ICH3S */
147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CAM_LPC,
148 ich_init, NULL }, /* ICH3M */
149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_LPC,
150 ich_init, NULL }, /* ICH4 */
151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ISA,
152 ich_init, NULL }, /* ICH4M */
153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LPC,
154 ich_init, NULL }, /* ICH5 */
155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LPC,
156 ich_init, NULL }, /* ICH6/ICH6R */
157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FBM_LPC,
158 ich_init, NULL }, /* ICH6M */
159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LPC,
160 ich_init, NULL }, /* ICH7/ICH7R */
161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_LPC,
162 ich_init, NULL }, /* ICH7-M */
163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GHM_LPC,
164 ich_init, NULL }, /* ICH7DH/ICH7-M DH */
165
166 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C558,
167 opti82c558_init, NULL },
168 { PCI_VENDOR_OPTI, PCI_PRODUCT_OPTI_82C700,
169 opti82c700_init, NULL },
170
171 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C586_ISA,
172 via82c586_init, NULL },
173 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C596A,
174 via82c586_init, NULL },
175 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT82C686A_ISA,
176 via82c586_init, NULL },
177
178 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8231,
179 via8231_init, NULL },
180 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233,
181 via82c586_init, NULL },
182 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8233A,
183 via8231_init, NULL },
184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8235,
185 via8231_init, NULL },
186 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8237,
187 via8231_init, NULL },
188
189
190 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_85C503,
191 sis85c503_init, NULL },
192 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_962,
193 sis85c503_init, NULL },
194 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_963,
195 sis85c503_init, NULL },
196
197 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC756_PMC,
198 amd756_init, NULL },
199 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC766_PMC,
200 amd756_init, NULL },
201 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_PMC,
202 amd756_init, NULL },
203
204 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1533,
205 ali1543_init, NULL },
206 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1543,
207 ali1543_init, NULL },
208
209 { 0, 0,
210 NULL, NULL },
211 };
212
213 const struct pciintr_icu_table *pciintr_icu_lookup(pcireg_t);
214
215 const struct pciintr_icu_table *
216 pciintr_icu_lookup(pcireg_t id)
217 {
218 const struct pciintr_icu_table *piit;
219
220 for (piit = pciintr_icu_table;
221 piit->piit_init != NULL;
222 piit++) {
223 if (PCI_VENDOR(id) == piit->piit_vendor &&
224 PCI_PRODUCT(id) == piit->piit_product)
225 return (piit);
226 }
227
228 return (NULL);
229 }
230
231 struct pciintr_link_map *
232 pciintr_link_lookup(int link)
233 {
234 struct pciintr_link_map *l;
235
236 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
237 if (l->link == link)
238 return (l);
239 }
240
241 return (NULL);
242 }
243
244 struct pciintr_link_map *
245 pciintr_link_alloc(struct pcibios_intr_routing *pir, int pin)
246 {
247 int link = pir->linkmap[pin].link, clink, irq;
248 struct pciintr_link_map *l, *lstart;
249
250 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */
251 /*
252 * Get the canonical link value for this entry.
253 */
254 if (pciintr_icu_getclink(pciintr_icu_tag, pciintr_icu_handle,
255 link, &clink) != 0) {
256 /*
257 * ICU doesn't understand the link value.
258 * Just ignore this PIR entry.
259 */
260 #ifdef DIAGNOSTIC
261 printf("pciintr_link_alloc: bus %d device %d: "
262 "link 0x%02x invalid\n",
263 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link);
264 #endif
265 return (NULL);
266 }
267
268 /*
269 * Check the link value by asking the ICU for the
270 * canonical link value.
271 * Also, determine if this PIRQ is mapped to an IRQ.
272 */
273 if (pciintr_icu_get_intr(pciintr_icu_tag, pciintr_icu_handle,
274 clink, &irq) != 0) {
275 /*
276 * ICU doesn't understand the canonical link value.
277 * Just ignore this PIR entry.
278 */
279 #ifdef DIAGNOSTIC
280 printf("pciintr_link_alloc: "
281 "bus %d device %d link 0x%02x: "
282 "PIRQ 0x%02x invalid\n",
283 pir->bus, PIR_DEVFUNC_DEVICE(pir->device), link,
284 clink);
285 #endif
286 return (NULL);
287 }
288 }
289
290 l = malloc(sizeof(*l), M_DEVBUF, M_NOWAIT);
291 if (l == NULL)
292 panic("pciintr_link_alloc");
293
294 memset(l, 0, sizeof(*l));
295
296 l->link = link;
297 l->bitmap = pir->linkmap[pin].bitmap;
298 if (pciintr_icu_tag != NULL) { /* compatible PCI ICU found */
299 l->clink = clink;
300 l->irq = irq; /* maybe X86_PCI_INTERRUPT_LINE_NO_CONNECTION */
301 } else {
302 l->clink = link; /* only for PCIBIOSVERBOSE diagnostic */
303 l->irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
304 }
305
306 lstart = SIMPLEQ_FIRST(&pciintr_link_map_list);
307 if (lstart == NULL || lstart->link < l->link)
308 SIMPLEQ_INSERT_TAIL(&pciintr_link_map_list, l, list);
309 else
310 SIMPLEQ_INSERT_HEAD(&pciintr_link_map_list, l, list);
311
312 return (l);
313 }
314
315 struct pcibios_intr_routing *
316 pciintr_pir_lookup(int bus, int device)
317 {
318 struct pcibios_intr_routing *pir;
319 int entry;
320
321 if (pcibios_pir_table == NULL)
322 return (NULL);
323
324 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) {
325 pir = &pcibios_pir_table[entry];
326 if (pir->bus == bus &&
327 PIR_DEVFUNC_DEVICE(pir->device) == device)
328 return (pir);
329 }
330
331 return (NULL);
332 }
333
334 static int
335 pciintr_bitmap_count_irq(int irq_bitmap, int *irqp)
336 {
337 int i, bit, count = 0, irq = X86_PCI_INTERRUPT_LINE_NO_CONNECTION;
338
339 if (irq_bitmap != 0) {
340 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) {
341 if (irq_bitmap & bit) {
342 irq = i;
343 count++;
344 }
345 }
346 }
347 *irqp = irq;
348 return (count);
349 }
350
351 static int
352 pciintr_bitmap_find_lowest_irq(int irq_bitmap, int *irqp)
353 {
354 int i, bit;
355
356 if (irq_bitmap != 0) {
357 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) {
358 if (irq_bitmap & bit) {
359 *irqp = i;
360 return (1); /* found */
361 }
362 }
363 }
364 return (0); /* not found */
365 }
366
367 int
368 pciintr_link_init(void)
369 {
370 int entry, pin, link;
371 struct pcibios_intr_routing *pir;
372 struct pciintr_link_map *l;
373
374 if (pcibios_pir_table == NULL) {
375 /* No PIR table; can't do anything. */
376 printf("pciintr_link_init: no PIR table\n");
377 return (1);
378 }
379
380 SIMPLEQ_INIT(&pciintr_link_map_list);
381
382 for (entry = 0; entry < pcibios_pir_table_nentries; entry++) {
383 pir = &pcibios_pir_table[entry];
384 for (pin = 0; pin < PCI_INTERRUPT_PIN_MAX; pin++) {
385 link = pir->linkmap[pin].link;
386 if (link == 0) {
387 /* No connection for this pin. */
388 continue;
389 }
390 /*
391 * Multiple devices may be wired to the same
392 * interrupt; check to see if we've seen this
393 * one already. If not, allocate a new link
394 * map entry and stuff it in the map.
395 */
396 l = pciintr_link_lookup(link);
397 if (l == NULL) {
398 (void) pciintr_link_alloc(pir, pin);
399 } else if (pir->linkmap[pin].bitmap != l->bitmap) {
400 /*
401 * violates PCI IRQ Routing Table Specification
402 */
403 #ifdef DIAGNOSTIC
404 printf("pciintr_link_init: "
405 "bus %d device %d link 0x%02x: "
406 "bad irq bitmap 0x%04x, "
407 "should be 0x%04x\n",
408 pir->bus, PIR_DEVFUNC_DEVICE(pir->device),
409 link, pir->linkmap[pin].bitmap, l->bitmap);
410 #endif
411 /* safer value. */
412 l->bitmap &= pir->linkmap[pin].bitmap;
413 /* XXX - or, should ignore this entry? */
414 }
415 }
416 }
417
418 return (0);
419 }
420
421 #ifdef PCIBIOS_INTR_GUESS
422 /*
423 * No compatible PCI ICU found.
424 * Hopes the BIOS already setup the ICU.
425 */
426 int
427 pciintr_guess_irq(void)
428 {
429 struct pciintr_link_map *l;
430 int irq, guessed = 0;
431
432 /*
433 * Stage 1: If only one IRQ is available for the link, use it.
434 */
435 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
436 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION)
437 continue;
438 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) {
439 l->irq = irq;
440 l->fixup_stage = 1;
441 #ifdef PCIINTR_DEBUG
442 printf("pciintr_guess_irq (stage 1): "
443 "guessing PIRQ 0x%02x to be IRQ %d\n",
444 l->clink, l->irq);
445 #endif
446 guessed = 1;
447 }
448 }
449
450 return (guessed ? 0 : -1);
451 }
452 #endif /* PCIBIOS_INTR_GUESS */
453
454 int
455 pciintr_link_fixup(void)
456 {
457 struct pciintr_link_map *l;
458 int irq;
459 uint16_t pciirq = 0;
460
461 /*
462 * First stage: Attempt to connect PIRQs which aren't
463 * yet connected.
464 */
465 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
466 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
467 /*
468 * Interrupt is already connected. Don't do
469 * anything to it.
470 * In this case, l->fixup_stage == 0.
471 */
472 pciirq |= 1 << l->irq;
473 #ifdef PCIINTR_DEBUG
474 printf("pciintr_link_fixup: PIRQ 0x%02x already "
475 "connected to IRQ %d\n", l->clink, l->irq);
476 #endif
477 continue;
478 }
479 /*
480 * Interrupt isn't connected. Attempt to assign it to an IRQ.
481 */
482 #ifdef PCIINTR_DEBUG
483 printf("pciintr_link_fixup: PIRQ 0x%02x not connected",
484 l->clink);
485 #endif
486 /*
487 * Just do the easy case now; we'll defer the harder ones
488 * to Stage 2.
489 */
490 if (pciintr_bitmap_count_irq(l->bitmap, &irq) == 1) {
491 l->irq = irq;
492 l->fixup_stage = 1;
493 pciirq |= 1 << irq;
494 #ifdef PCIINTR_DEBUG
495 printf(", assigning IRQ %d", l->irq);
496 #endif
497 }
498 #ifdef PCIINTR_DEBUG
499 printf("\n");
500 #endif
501 }
502
503 /*
504 * Stage 2: Attempt to connect PIRQs which we didn't
505 * connect in Stage 1.
506 */
507 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
508 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION)
509 continue;
510 if (pciintr_bitmap_find_lowest_irq(l->bitmap & pciirq,
511 &l->irq)) {
512 /*
513 * This IRQ is a valid PCI IRQ already
514 * connected to another PIRQ, and also an
515 * IRQ our PIRQ can use; connect it up!
516 */
517 l->fixup_stage = 2;
518 #ifdef PCIINTR_DEBUG
519 printf("pciintr_link_fixup (stage 2): "
520 "assigning IRQ %d to PIRQ 0x%02x\n",
521 l->irq, l->clink);
522 #endif
523 }
524 }
525
526 #ifdef PCIBIOS_IRQS_HINT
527 /*
528 * Stage 3: The worst case. I need configuration hint that
529 * user supplied a mask for the PCI irqs
530 */
531 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
532 if (l->irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION)
533 continue;
534 if (pciintr_bitmap_find_lowest_irq(
535 l->bitmap & pcibios_irqs_hint, &l->irq)) {
536 l->fixup_stage = 3;
537 #ifdef PCIINTR_DEBUG
538 printf("pciintr_link_fixup (stage 3): "
539 "assigning IRQ %d to PIRQ 0x%02x\n",
540 l->irq, l->clink);
541 #endif
542 }
543 }
544 #endif /* PCIBIOS_IRQS_HINT */
545
546 return (0);
547 }
548
549 int
550 pciintr_link_route(uint16_t *pciirq)
551 {
552 struct pciintr_link_map *l;
553 int rv = 0;
554
555 *pciirq = 0;
556
557 SIMPLEQ_FOREACH(l, &pciintr_link_map_list, list) {
558 if (l->fixup_stage == 0) {
559 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
560 /* Appropriate interrupt was not found. */
561 #ifdef DIAGNOSTIC
562 printf("pciintr_link_route: "
563 "PIRQ 0x%02x: no IRQ, try "
564 "\"options PCIBIOS_IRQS_HINT=0x%04x\"\n",
565 l->clink,
566 /* suggest irq 9/10/11, if possible */
567 (l->bitmap & 0x0e00) ? (l->bitmap & 0x0e00)
568 : l->bitmap);
569 #endif
570 } else {
571 /* BIOS setting has no problem */
572 #ifdef PCIINTR_DEBUG
573 printf("pciintr_link_route: "
574 "route of PIRQ 0x%02x -> "
575 "IRQ %d preserved BIOS setting\n",
576 l->clink, l->irq);
577 #endif
578 *pciirq |= (1 << l->irq);
579 }
580 continue; /* nothing to do. */
581 }
582
583 if (pciintr_icu_set_intr(pciintr_icu_tag, pciintr_icu_handle,
584 l->clink, l->irq) != 0 ||
585 pciintr_icu_set_trigger(pciintr_icu_tag,
586 pciintr_icu_handle,
587 l->irq, IST_LEVEL) != 0) {
588 printf("pciintr_link_route: route of PIRQ 0x%02x -> "
589 "IRQ %d failed\n", l->clink, l->irq);
590 rv = 1;
591 } else {
592 /*
593 * Succssfully routed interrupt. Mark this as
594 * a PCI interrupt.
595 */
596 *pciirq |= (1 << l->irq);
597 }
598 }
599
600 return (rv);
601 }
602
603 int
604 pciintr_irq_release(uint16_t *pciirq)
605 {
606 int i, bit;
607 uint16_t bios_pciirq;
608 int reg;
609
610 #ifdef PCIINTR_DEBUG
611 printf("pciintr_irq_release: fixup pciirq level/edge map 0x%04x\n",
612 *pciirq);
613 #endif
614
615 /* Get bios level/edge setting. */
616 bios_pciirq = 0;
617 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) {
618 (void)pciintr_icu_get_trigger(pciintr_icu_tag,
619 pciintr_icu_handle, i, &reg);
620 if (reg == IST_LEVEL)
621 bios_pciirq |= bit;
622 }
623
624 #ifdef PCIINTR_DEBUG
625 printf("pciintr_irq_release: bios pciirq level/edge map 0x%04x\n",
626 bios_pciirq);
627 #endif /* PCIINTR_DEBUG */
628
629 /* fixup final level/edge setting. */
630 *pciirq |= bios_pciirq;
631 for (i = 0, bit = 1; i < 16; i++, bit <<= 1) {
632 if ((*pciirq & bit) == 0)
633 reg = IST_EDGE;
634 else
635 reg = IST_LEVEL;
636 (void) pciintr_icu_set_trigger(pciintr_icu_tag,
637 pciintr_icu_handle, i, reg);
638
639 }
640
641 #ifdef PCIINTR_DEBUG
642 printf("pciintr_irq_release: final pciirq level/edge map 0x%04x\n",
643 *pciirq);
644 #endif /* PCIINTR_DEBUG */
645
646 return (0);
647 }
648
649 int
650 pciintr_header_fixup(pci_chipset_tag_t pc)
651 {
652 PCIBIOS_PRINTV(("------------------------------------------\n"));
653 PCIBIOS_PRINTV((" device vendor product pin PIRQ IRQ stage\n"));
654 PCIBIOS_PRINTV(("------------------------------------------\n"));
655 pci_device_foreach(pc, pcibios_max_bus, pciintr_do_header_fixup, NULL);
656 PCIBIOS_PRINTV(("------------------------------------------\n"));
657
658 return (0);
659 }
660
661 void
662 pciintr_do_header_fixup(pci_chipset_tag_t pc, pcitag_t tag,
663 void *context)
664 {
665 struct pcibios_intr_routing *pir;
666 struct pciintr_link_map *l;
667 int pin, irq, link;
668 int bus, device, function;
669 pcireg_t intr, id;
670
671 pci_decompose_tag(pc, tag, &bus, &device, &function);
672 id = pci_conf_read(pc, tag, PCI_ID_REG);
673
674 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
675 pin = PCI_INTERRUPT_PIN(intr);
676 irq = PCI_INTERRUPT_LINE(intr);
677
678 #if 0
679 if (pin == 0) {
680 /*
681 * No interrupt used.
682 */
683 return;
684 }
685 #endif
686
687 pir = pciintr_pir_lookup(bus, device);
688 if (pir == NULL || (link = pir->linkmap[pin - 1].link) == 0) {
689 /*
690 * Interrupt not connected; no
691 * need to change.
692 */
693 return;
694 }
695
696 l = pciintr_link_lookup(link);
697 if (l == NULL) {
698 #ifdef PCIINTR_DEBUG
699 /*
700 * No link map entry.
701 * Probably pciintr_icu_getclink() or pciintr_icu_get_intr()
702 * was failed.
703 */
704 printf("pciintr_header_fixup: no entry for link 0x%02x "
705 "(%d:%d:%d:%c)\n", link, bus, device, function,
706 '@' + pin);
707 #endif
708 return;
709 }
710
711 #ifdef PCIBIOSVERBOSE
712 if (pcibiosverbose) {
713 PCIBIOS_PRINTV(("%03d:%02d:%d 0x%04x 0x%04x %c 0x%02x",
714 bus, device, function, PCI_VENDOR(id), PCI_PRODUCT(id),
715 '@' + pin, l->clink));
716 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION)
717 PCIBIOS_PRINTV((" -"));
718 else
719 PCIBIOS_PRINTV((" %3d", l->irq));
720 PCIBIOS_PRINTV((" %d ", l->fixup_stage));
721 }
722 #endif
723
724 /*
725 * IRQs 14 and 15 are reserved for PCI IDE interrupts; don't muck
726 * with them.
727 */
728 if (irq == 14 || irq == 15) {
729 PCIBIOS_PRINTV((" WARNING: ignored\n"));
730 return;
731 }
732
733 if (l->irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
734 /* Appropriate interrupt was not found. */
735 if (pciintr_icu_tag == NULL &&
736 irq != 0 && irq != X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
737 /*
738 * Do not print warning,
739 * if no compatible PCI ICU found,
740 * but the irq is already assigned by BIOS.
741 */
742 PCIBIOS_PRINTV(("\n"));
743 } else {
744 PCIBIOS_PRINTV((" WARNING: missing IRQ\n"));
745 }
746 return;
747 }
748
749 if (l->irq == irq) {
750 /* don't have to reconfigure */
751 PCIBIOS_PRINTV((" already assigned\n"));
752 return;
753 }
754
755 if (irq == 0 || irq == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) {
756 PCIBIOS_PRINTV((" fixed up\n"));
757 } else {
758 /* routed by BIOS, but inconsistent */
759 #ifdef PCI_INTR_FIXUP_FORCE
760 /* believe PCI IRQ Routing table */
761 PCIBIOS_PRINTV((" WARNING: overriding irq %d\n", irq));
762 #else
763 /* believe PCI Interrupt Configuration Register (default) */
764 PCIBIOS_PRINTV((" WARNING: preserving irq %d\n", irq));
765 return;
766 #endif
767 }
768
769 intr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
770 intr |= (l->irq << PCI_INTERRUPT_LINE_SHIFT);
771 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
772 }
773
774 int
775 pci_intr_fixup(pci_chipset_tag_t pc, bus_space_tag_t iot, uint16_t *pciirq)
776 {
777 const struct pciintr_icu_table *piit = NULL;
778 pcitag_t icutag;
779 pcireg_t icuid;
780 int error = 0;
781
782 /*
783 * Attempt to initialize our PCI interrupt router. If
784 * the PIR Table is present in ROM, use the location
785 * specified by the PIR Table, and use the compat ID,
786 * if present. Otherwise, we have to look for the router
787 * ourselves (the PCI-ISA bridge).
788 *
789 * A number of buggy BIOS implementations leave the router
790 * entry as 000:00:0, which is typically not the correct
791 * device/function. If the router device address is set to
792 * this value, and the compatible router entry is undefined
793 * (zero is the correct value to indicate undefined), then we
794 * work on the basis it is most likely an error, and search
795 * the entire device-space of bus 0 (but obviously starting
796 * with 000:00:0, in case that really is the right one).
797 */
798 if (pcibios_pir_header.signature != 0 &&
799 (pcibios_pir_header.router_bus != 0 ||
800 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc) != 0 ||
801 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc) != 0 ||
802 pcibios_pir_header.compat_router != 0)) {
803 icutag = pci_make_tag(pc, pcibios_pir_header.router_bus,
804 PIR_DEVFUNC_DEVICE(pcibios_pir_header.router_devfunc),
805 PIR_DEVFUNC_FUNCTION(pcibios_pir_header.router_devfunc));
806 icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
807 if ((piit = pciintr_icu_lookup(icuid)) == NULL) {
808 /*
809 * if we fail to look up an ICU at given
810 * PCI address, try compat ID next.
811 */
812 icuid = pcibios_pir_header.compat_router;
813 piit = pciintr_icu_lookup(icuid);
814 }
815 } else {
816 int device, maxdevs = pci_bus_maxdevs(pc, 0);
817
818 /*
819 * Search configuration space for a known interrupt
820 * router.
821 */
822 for (device = 0; device < maxdevs; device++) {
823 const struct pci_quirkdata *qd;
824 int function, nfuncs;
825 pcireg_t bhlcr;
826
827 icutag = pci_make_tag(pc, 0, device, 0);
828 icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
829
830 /* Invalid vendor ID value? */
831 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID)
832 continue;
833 /* XXX Not invalid, but we've done this ~forever. */
834 if (PCI_VENDOR(icuid) == 0)
835 continue;
836
837 qd = pci_lookup_quirkdata(PCI_VENDOR(icuid),
838 PCI_PRODUCT(icuid));
839
840 bhlcr = pci_conf_read(pc, icutag, PCI_BHLC_REG);
841 if (PCI_HDRTYPE_MULTIFN(bhlcr) ||
842 (qd != NULL &&
843 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
844 nfuncs = 8;
845 else
846 nfuncs = 1;
847
848 for (function = 0; function < nfuncs; function++) {
849 icutag = pci_make_tag(pc, 0, device, function);
850 icuid = pci_conf_read(pc, icutag, PCI_ID_REG);
851
852 /* Invalid vendor ID value? */
853 if (PCI_VENDOR(icuid) == PCI_VENDOR_INVALID)
854 continue;
855 /* Not invalid, but we've done this ~forever */
856 if (PCI_VENDOR(icuid) == 0)
857 continue;
858
859 piit = pciintr_icu_lookup(icuid);
860 if (piit != NULL)
861 goto found;
862 }
863 }
864
865 /*
866 * Invalidate the ICU ID. If we failed to find the
867 * interrupt router (piit == NULL) we don't want to
868 * display a spurious device address below containing
869 * the product information of the last device we
870 * looked at.
871 */
872 icuid = 0;
873 found:;
874 }
875
876 if (piit == NULL) {
877 printf("pci_intr_fixup: no compatible PCI ICU found");
878 if (pcibios_pir_header.signature != 0 && icuid != 0)
879 printf(": ICU vendor 0x%04x product 0x%04x",
880 PCI_VENDOR(icuid), PCI_PRODUCT(icuid));
881 printf("\n");
882 #ifdef PCIBIOS_INTR_GUESS
883 if (pciintr_link_init())
884 return (-1); /* non-fatal */
885 if (pciintr_guess_irq())
886 return (-1); /* non-fatal */
887 if (pciintr_header_fixup(pc))
888 return (1); /* fatal */
889 return (0); /* success! */
890 #else
891 return (-1); /* non-fatal */
892 #endif
893 }
894
895 /*
896 * Initialize the PCI ICU.
897 */
898 if ((*piit->piit_init)(pc, iot, icutag, &pciintr_icu_tag,
899 &pciintr_icu_handle) != 0)
900 return (-1); /* non-fatal */
901
902 /*
903 * Initialize the PCI interrupt link map.
904 */
905 if (pciintr_link_init()) {
906 error = -1; /* non-fatal */
907 goto cleanup;
908 }
909
910 /*
911 * Fix up the link->IRQ mappings.
912 */
913 if (pciintr_link_fixup() != 0) {
914 error = -1; /* non-fatal */
915 goto cleanup;
916 }
917
918 /*
919 * Now actually program the PCI ICU with the new
920 * routing information.
921 */
922 if (pciintr_link_route(pciirq) != 0) {
923 error = 1; /* fatal */
924 goto cleanup;
925 }
926
927 /*
928 * Now that we've routed all of the PIRQs, rewrite the PCI
929 * configuration headers to reflect the new mapping.
930 */
931 if (pciintr_header_fixup(pc) != 0) {
932 error = 1; /* fatal */
933 goto cleanup;
934 }
935
936 /*
937 * Free any unused PCI IRQs for ISA devices.
938 */
939 if (pciintr_irq_release(pciirq) != 0) {
940 error = -1; /* non-fatal */
941 goto cleanup;
942 }
943
944 /*
945 * All done!
946 */
947 cleanup:
948 if (piit->piit_uninit != NULL)
949 (*piit->piit_uninit)(pciintr_icu_handle);
950 return (error);
951 }
NetBSD on the FriendlyARM MINI2440