sys/arch/i386/pci/piixreg.h

   1 /*      $NetBSD: piixreg.h,v 1.1.34.3 2004/09/21 13:17:08 skrll Exp $   */
   2
   3 /*
   4  * Copyright (c) 1999, by UCHIYAMA Yasushi
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. The name of the developer may NOT be used to endorse or promote products
  13  *    derived from this software without specific prior written permission.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * Register definitions for the Intel PIIX PCI-ISA bridge interrupt controller
  30  * and ICHn I/O controller hub
  31  */
  32
  33 /*
  34  * PIRQ[A-D]# - PIRQ ROUTE CONTROL REGISTERS
  35  * PCI Configuration registers 0x60, 0x61, 0x62, 0x63
  36  *
  37  * PIRQ[E-H]# - PIRQ ROUTE CONTROL REGISTERS (ICH2 and later only)
  38  * PCI Configuration registers 0x68, 0x69, 0x6a, 0x6b
  39  */
  40
  41 #define PIIX_LEGAL_LINK(link)   ((link) >= 0 && (link) <= piix_max_link)
  42
  43 #define PIIX_PIRQ_MASK          0xdef8
  44 #define PIIX_LEGAL_IRQ(irq)     ((irq) >= 0 && (irq) <= 15 &&           \
  45                                  ((1 << (irq)) & PIIX_PIRQ_MASK) != 0)
  46
  47 #define PIIX_CFG_PIRQ           0x60    /* PCI configuration space */
  48 #define PIIX_CFG_PIRQ2          0x68    /* PCI configuration space */
  49 #define PIIX_CFG_PIRQ_NONE      0x80
  50 #define PIIX_CFG_PIRQ_MASK      0x0f
  51 #define PIIX_PIRQ(reg, x)       (((reg) >> ((x) << 3)) & 0xff)
  52
  53 /*
  54  * ELCR - EDGE/LEVEL CONTROL REGISTER
  55  *
  56  * PCI I/O registers 0x4d0, 0x4d1
  57  */
  58 #define PIIX_REG_ELCR           0x4d0
  59 #define PIIX_REG_ELCR_SIZE      2