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1 /* $NetBSD$ */
2 /* OpenBSD: via8231reg.h,v 1.4 2005/10/26 21:38:28 mickey Exp */
4 /*
5 * Copyright (c) 2005, by Michael Shalayeff
6 * Copyright (c) 2003, by Matthew Gream
7 * Copyright (c) 1999, by UCHIYAMA Yasushi
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. The name of the developer may NOT be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
31 /*
32 * Register definitions for the VIA8231 PCI to ISA Bridge
33 */
35 /*
36 * Edge Triggered Interrupt Select register. (0x54)
37 * bits 7-4: reserved
38 * bit 3: Edge Triggered Interrupt Select for PCI Interrupt A
39 * bit 2: Edge Triggered Interrupt Select for PCI Interrupt B
40 * bit 1: Edge Triggered Interrupt Select for PCI Interrupt C
41 * bit 0: Edge Triggered Interrupt Select for PCI Interrupt D
42 * 0 = Non-invert (level)
43 * 1 = Invert (edge)
44 *
45 * PIRQ Select register. (0x55 - 0x57)
46 * (0x55)
47 * bits 7-4: PINTA# Routing
48 * bits 3-0: reserved
49 * (0x56)
50 * bits 7-4: PINTC# Routing
51 * bits 3-0: PINTB# Routing
52 * (0x57)
53 * bits 7-4: PINTD# Routing
54 * bits 3-0: reserved
55 * PIRQ Select register. (0x44 - 0x47)
56 * (0x44)
57 * bits 7-4: PINTF# Routing
58 * bits 3-0: PINTE# Routing
59 * (0x45)
60 * bits 7-4: PINTH# Routing
61 * bits 3-0: PINTG# Routing
62 * (0x46)
63 * bit 4: EFGH/ABCD share (1 -- use above mappings)
64 * bit 3: Edge Triggered Interrupt Select for PCI Interrupt H
65 * bit 2: Edge Triggered Interrupt Select for PCI Interrupt G
66 * bit 1: Edge Triggered Interrupt Select for PCI Interrupt F
67 * bit 0: Edge Triggered Interrupt Select for PCI Interrupt E
68 *
69 * 0000: Disabled 0100: IRQ4 1000: Reserved 1100: IRQ12
70 * 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved
71 * 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14
72 * 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15
73 */
74 #define VIA8231_CFG_PIR 0x54
75 #define VIA8237_CFG_PIR 0x44
77 #define VIA8231_TRIGGER_CNFG_MASK 0x000000ff
78 #define VIA8231_TRIGGER_CNFG_SHFT 0
79 #define VIA8237_TRIGGER_CNFG_MASK 0x000f0000
80 #define VIA8237_TRIGGER_CNFG_SHFT 16
81 #define VIA8231_TRIGGER_CNFG_LEVEL 0
82 #define VIA8231_TRIGGER_CNFG_EDGE 1
83 #define VIA8237_TRIGGER_CNFG_ENA 0x00100000
85 #define VIA8231_GET_TRIGGER(ph) \
86 ((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
87 & VIA8231_TRIGGER_CNFG_MASK) >> VIA8231_TRIGGER_CNFG_SHFT)
88 #define VIA8237_GET_TRIGGER(ph) \
89 ((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
90 & VIA8237_TRIGGER_CNFG_MASK) >> VIA8237_TRIGGER_CNFG_SHFT)
92 #define VIA8231_SET_TRIGGER(ph, n) \
93 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
94 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
95 & ~VIA8231_TRIGGER_CNFG_MASK) | ((n) << VIA8231_TRIGGER_CNFG_SHFT))
96 #define VIA8237_SET_TRIGGER(ph, n) \
97 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
98 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
99 & ~VIA8237_TRIGGER_CNFG_MASK) | ((n) << VIA8237_TRIGGER_CNFG_SHFT))
102 #define VIA8231_ROUTING_CNFG_MASK 0xffffff00
104 #define VIA8231_ROUTING_CNFG_DISABLED 0
105 #define VIA8237_ROUTING_CNFG_MASK 0xffff
106 #define VIA8237_ROUTING_CNFG_SHFT 0
108 #define VIA8231_GET_ROUTING(ph) \
109 ((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
110 & VIA8231_ROUTING_CNFG_MASK) >> VIA8231_ROUTING_CNFG_SHFT)
111 #define VIA8237_GET_ROUTING(ph) \
112 ((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
113 & VIA8237_ROUTING_CNFG_MASK) >> VIA8237_ROUTING_CNFG_SHFT)
115 #define VIA8231_SET_ROUTING(ph, n) \
116 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
117 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
118 & ~VIA8231_ROUTING_CNFG_MASK) | ((n) << VIA8231_ROUTING_CNFG_SHFT))
119 #define VIA8237_SET_ROUTING(ph, n) \
120 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
121 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
122 & ~VIA8237_ROUTING_CNFG_MASK) | \
123 ((n) << VIA8237_ROUTING_CNFG_SHFT) | VIA8237_TRIGGER_CNFG_ENA)
126 #define VIA8231_PIRQ_MASK 0xdefa
127 #define VIA8231_PIRQ_LEGAL(irq) \
128 ((irq) >= 0 && (irq) <= 15 && ((1 << (irq)) & VIA8231_PIRQ_MASK))
129 #define VIA8231_LINK_MAX 3
130 #define VIA8237_LINK_MAX 7
131 #define VIA8231_LINK_LEGAL(link) \
132 ((link) >= 0 && (link) <= VIA8231_LINK_MAX)
133 #define VIA8237_LINK_LEGAL(link) \
134 ((link) >= 0 && (link) <= VIA8237_LINK_MAX)
135 #define VIA8231_TRIG_LEGAL(trig) \
136 ((trig) == IST_LEVEL || (trig) == IST_EDGE)