sys/arch/powerpc/include/oea/hid.h

   1 /*      $NetBSD: hid.h,v 1.8 2008/05/25 10:16:04 phx Exp $      */
   2
   3 /*-
   4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _POWERPC_OEA_HID_H_
  30 #define _POWERPC_OEA_HID_H_
  31
  32 /* Hardware Implementation Dependent registers for the PowerPC */
  33
  34 #define HID0_EMCP       0x80000000  /* Enable MCP */
  35 #define HID0_DBP        0x40000000  /* Disable 60x bus parity generation */
  36 #define HID0_EBA        0x20000000  /* Enable 60x bus address parity checking */
  37 #define HID0_EBD        0x10000000  /* Enable 60x bus data parity checking */
  38 #define HID0_BCLK       0x08000000  /* CLK_OUT clock type selection */
  39 #define HID0_EICE       0x04000000  /* Enable ICE output */
  40 #define HID0_TBEN       0x04000000  /* Time base enable (7450) */
  41 #define HID0_ECLK       0x02000000  /* CLK_OUT clock type selection */
  42 #define HID0_PAR        0x01000000  /* Disable precharge of ARTRY */
  43 #define HID0_STEN       0x01000000  /* Software table search enable (7450) */
  44 #define HID0_DOZE       0x00800000  /* Enable doze mode */
  45 #define HID0_HIGH_BAT_EN 0x00800000  /* Enable additional BATs (74[45][578]) */
  46 #define HID0_NAP        0x00400000  /* Enable nap mode */
  47 #define HID0_SLEEP      0x00200000  /* Enable sleep mode */
  48 #define HID0_DPM        0x00100000  /* Enable Dynamic power management */
  49 #define HID0_RISEG      0x00080000  /* Read I-SEG */
  50 #define HID0_BHTCLR     0x00040000  /* Clear branch history table (7450) */
  51 #define HID0_EIEC       0x00040000  /* Enable internal error checking */
  52 #define HID0_XAEN       0x00020000  /* Enable eXtended Addressing (7450) */
  53 #define HID0_NHR        0x00010000  /* Not hard reset */
  54 #define HID0_ICE        0x00008000  /* Enable i-cache */
  55 #define HID0_DCE        0x00004000  /* Enable d-cache */
  56 #define HID0_ILOCK      0x00002000  /* i-cache lock */
  57 #define HID0_DLOCK      0x00001000  /* d-cache lock */
  58 #define HID0_ICFI       0x00000800  /* i-cache flush invalidate */
  59 #define HID0_DCFI       0x00000400  /* d-cache flush invalidate */
  60 #define HID0_SPD        0x00000200  /* Disable speculative cache access */
  61 #define HID0_IFEM       0x00000100  /* Enable M-bit for I-fetch */
  62 #define HID0_XBSEN      0x00000100  /* Extended BAT block size enable (7455+) */
  63 #define HID0_SGE        0x00000080  /* Enable store gathering */
  64 #define HID0_DCFA       0x00000040  /* Data cache flush assist */
  65 #define HID0_BTIC       0x00000020  /* Enable BTIC */
  66 #define HID0_LRSTK      0x00000010  /* Link register stack enable (7450) */
  67 #define HID0_ABE        0x00000008  /* Enable address broadcast */
  68 #define HID0_FOLD       0x00000008  /* Branch folding enable (7450) */
  69 #define HID0_BHT        0x00000004  /* Enable branch history table */
  70 #define HID0_BTCD       0x00000002  /* Branch target addr cache disable (604) */
  71 #define HID0_NOPTI      0x00000001  /* No-op the dcbt(st) */
  72
  73 #define HID0_BITMASK "\020" \
  74     "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \
  75     "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \
  76     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \
  77     "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI"
  78
  79 #define HID0_7450_BITMASK "\020" \
  80     "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \
  81     "\030HIGH_BAT_EN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \
  82     "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \
  83     "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
  84
  85 /*
  86  *  HID0 bit definitions per CPU model
  87  *
  88  * bit  603     604     750     7400    7410    7450
  89  *   0  EMCP    EMCP    EMCP    EMCP    EMCP    -
  90  *   1  -       ECP     DBP     -       -       -
  91  *   2  EBA     EBA     EBA     EBA     EDA     -
  92  *   3  EBD     EBD     EBD     EBD     EBD     -
  93  *   4  SBCLK   -       BCLK    BCKL    BCLK    -
  94  *   5  EICE    -       -       -       -       TBEN
  95  *   6  ECLK    -       ECLK    ECLK    ECLK    -
  96  *   7  PAR     PAR     PAR     PAR     PAR     STEN
  97  *   8  DOZE    -       DOZE    DOZE    DOZE    HIGH_BAT_EN
  98  *   9  NAP     -       NAP     NAP     NAP     NAP
  99  *  10  SLEEP   -       SLEEP   SLEEP   SLEEP   SLEEP
 100  *  11  DPM     -       DPM     DPM     DPM     DPM
 101  *  12  RISEG   -       -       RISEG   -       -
 102  *  13  -       -       -       EIEC    EIEC    BHTCLR
 103  *  14  -       -       -       -       -       XAEN
 104  *  15  -       NHR     NHR     NHR     NHR     NHR
 105  *  16  ICE     ICE     ICE     ICE     ICE     ICE
 106  *  17  DCE     DCE     DCE     DCE     DCE     DCE
 107  *  18  ILOCK   ILOCK   ILOCK   ILOCK   ILOCK   ILOCK
 108  *  19  DLOCK   DLOCK   DLOCK   DLOCK   DLOCK   DLOCK
 109  *  20  ICFI    ICFI    ICFI    ICFI    ICFI    ICFI
 110  *  21  DCFI    DCFI    DCFI    DCFI    DCFI    DCFI
 111  *  22  -       -       SPD     SPD     SPG     SPD
 112  *  23  -       -       IFEM    IFTT    IFTT    XBSEN
 113  *  24  -       SIE     SGE     SGE     SGE     SGE
 114  *  25  -       -       DCFA    DCFA    DCFA    -
 115  *  26  -       -       BTIC    BTIC    BTIC    BTIC
 116  *  27  FBIOB   -       -       -       -       LRSTK
 117  *  28  -       -       ABE     -       -       FOLD
 118  *  29  -       BHT     BHT     BHT     BHT     BHT
 119  *  30  -       BTCD    -       NOPDST  NOPDST  NOPDST
 120  *  31  NOOPTI  -       NOOPTI  NOPTI   NOPTI   NOPTI
 121  *
 122  *  604: ECP = Enable cache parity checking
 123  *  604: SIE = Serial instruction execution disable
 124  *  604: BTCD = Branch target address cache disable
 125  * 7450: TBEN = Time Base Enable
 126  * 7450: STEN = Software table lookup enable
 127  * 7450: BHTCLR = Branch history clear
 128  * 7450: LRSTK = Link Register Stack Enable
 129  * 7450: FOLD = Branch folding enable
 130  */
 131
 132 #define HID1_EMCP       0x80000000      /* Machine Check Signal Enable */
 133 #define HID1_EBA        0x20000000      /* Enable/Disable 60x/MPX Bus Address
 134                                            Parity Checking */
 135 #define HID1_EBD        0x10000000      /* Enable/Disable 60x/MPX Bus Data
 136                                            Parity Checking */
 137 #define HID1_BCLK       0x08000000      /* CLK_OUT */
 138 #define HID1_ECLK       0x02000000      /* CLK_OUT */
 139 #define HID1_PAR        0x01000000      /* Disable Precharge for ... */
 140 #define HID1_DFS4       0x00800000      /* Dynamic Freq Switch / 4 (7448) */
 141 #define HID1_DFS2       0x00400000      /* Dynamic Freq Switch / 2 (7447A) */
 142
 143 #endif /* _POWERPC_OEA_HID_H_ */