sys/arch/sun68k/include/intr.h

   1 /*      $NetBSD: intr.h,v 1.19 2008/06/15 07:23:26 tsutsui Exp $        */
   2
   3 /*
   4  * Copyright (c) 2001 Matt Fredette.
   5  * Copyright (c) 1998 Matt Thomas.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The name of the company nor the names of the authors may be used to
  17  *    endorse or promote products derived from this software without specific
  18  *    prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  24  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  25  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  26  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #ifndef _SUN68K_INTR_H_
  34 #define _SUN68K_INTR_H_
  35
  36 #include <sys/queue.h>
  37 #include <m68k/psl.h>
  38
  39 /*
  40  * Interrupt levels.
  41  */
  42 #define IPL_NONE        0
  43 #define IPL_SOFTCLOCK   1
  44 #define IPL_SOFTBIO     2
  45 #define IPL_SOFTNET     3
  46 #define IPL_SOFTSERIAL  4
  47 #define IPL_VM          5
  48 #define IPL_SCHED       6
  49 #define IPL_HIGH        7
  50 #define NIPL            8
  51
  52 #define _IPL_SOFT_LEVEL1        1
  53 #define _IPL_SOFT_LEVEL2        2
  54 #define _IPL_SOFT_LEVEL3        3
  55 #define _IPL_SOFT_LEVEL_MIN     1
  56 #define _IPL_SOFT_LEVEL_MAX     3
  57
  58 #ifdef _KERNEL
  59
  60 extern int idepth;
  61
  62 static inline bool
  63 cpu_intr_p(void)
  64 {
  65
  66         return idepth != 0;
  67 }
  68
  69 extern const uint16_t ipl2psl_table[NIPL];
  70
  71 typedef int ipl_t;
  72 typedef struct {
  73         uint16_t _psl;
  74 } ipl_cookie_t;
  75
  76 static inline ipl_cookie_t
  77 makeiplcookie(ipl_t ipl)
  78 {
  79
  80         return (ipl_cookie_t){._psl = ipl2psl_table[ipl]};
  81 }
  82
  83 static inline int
  84 splraiseipl(ipl_cookie_t icookie)
  85 {
  86
  87         return _splraise(icookie._psl);
  88 }
  89
  90 /* These connect interrupt handlers. */
  91 typedef int (*isr_func_t)(void *);
  92 void isr_add_autovect(isr_func_t, void *, int);
  93 void isr_add_vectored(isr_func_t, void *, int, int);
  94 void isr_add_custom(int, void *);
  95
  96 /*
  97  * Define inline functions for PSL manipulation.
  98  * These are as close to macros as one can get.
  99  * When not optimizing gcc will call the locore.s
 100  * functions by the same names, so breakpoints on
 101  * these functions will work normally, etc.
 102  * (See the GCC extensions info document.)
 103  */
 104
 105 static __inline int _getsr(void);
 106
 107 /* Get current sr value. */
 108 static __inline int
 109 _getsr(void)
 110 {
 111         int rv;
 112
 113         __asm volatile ("clrl %0; movew %%sr,%0" : "=&d" (rv));
 114         return (rv);
 115 }
 116
 117 /*
 118  * The rest of this is sun68k specific, because other ports may
 119  * need to do special things in spl0() (i.e. simulate SIR).
 120  * Suns have a REAL interrupt register, so spl0() and splx(s)
 121  * have no need to check for any simulated interrupts, etc.
 122  */
 123
 124 #define spl0()  _spl0()         /* we have real software interrupts */
 125 #define splx(x) _spl(x)
 126
 127 /* IPL used by soft interrupts: netintr(), softclock() */
 128 #define splsoftclock()  splraise1()
 129 #define splsoftbio()    splraise1()
 130 #define splsoftnet()    splraise1()
 131 #define splsoftserial() splraise3()
 132
 133 /*
 134  * Note that the VM code runs at spl7 during kernel
 135  * initialization, and later at spl0, so we have to
 136  * use splraise to avoid enabling interrupts early.
 137  */
 138 #define splvm()         splraise4()
 139
 140 /* Zilog Serial hardware interrupts (hard-wired at 6) */
 141 #define splzs()         splserial()
 142 #define IPL_ZS          IPL_SERIAL
 143
 144 /* Block out all interrupts (except NMI of course). */
 145 #define splhigh()       spl7()
 146 #define splsched()      spl7()
 147
 148 /* This returns true iff the spl given is spl0. */
 149 #define is_spl0(s)      (((s) & PSL_IPL7) == 0)
 150
 151 #endif  /* _KERNEL */
 152
 153 #endif  /* _SUN68K_INTR_H */