sys/dev/cardbus/njs_cardbus.c

   1 /*      $NetBSD: njs_cardbus.c,v 1.10 2008/07/09 19:08:44 joerg Exp $   */
   2
   3 /*-
   4  * Copyright (c) 2004 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by ITOH Yasufumi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __KERNEL_RCSID(0, "$NetBSD: njs_cardbus.c,v 1.10 2008/07/09 19:08:44 joerg Exp $");
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/kernel.h>
  38 #include <sys/device.h>
  39
  40 #include <sys/bus.h>
  41 #include <sys/intr.h>
  42
  43 #include <dev/scsipi/scsi_all.h>
  44 #include <dev/scsipi/scsipi_all.h>
  45 #include <dev/scsipi/scsiconf.h>
  46
  47 #include <dev/cardbus/cardbusvar.h>
  48 #include <dev/pci/pcidevs.h>
  49
  50 #include <dev/ic/ninjascsi32reg.h>
  51 #include <dev/ic/ninjascsi32var.h>
  52
  53 #define NJSC32_CARDBUS_BASEADDR_IO      CARDBUS_BASE0_REG
  54 #define NJSC32_CARDBUS_BASEADDR_MEM     CARDBUS_BASE1_REG
  55
  56 struct njsc32_cardbus_softc {
  57         struct njsc32_softc     sc_njsc32;
  58
  59         /* CardBus-specific goo */
  60         cardbus_devfunc_t       sc_ct;          /* our CardBus devfuncs */
  61         cardbus_intr_line_t     sc_intrline;    /* our interrupt line */
  62         cardbustag_t            sc_tag;
  63
  64         bus_space_handle_t      sc_regmaph;
  65         bus_size_t              sc_regmap_size;
  66 };
  67
  68 static int      njs_cardbus_match(device_t, cfdata_t, void *);
  69 static void     njs_cardbus_attach(device_t, device_t, void *);
  70 static int      njs_cardbus_detach(device_t, int);
  71
  72 CFATTACH_DECL_NEW(njs_cardbus, sizeof(struct njsc32_cardbus_softc),
  73     njs_cardbus_match, njs_cardbus_attach, njs_cardbus_detach, NULL);
  74
  75 static const struct njsc32_cardbus_product {
  76         cardbus_vendor_id_t     p_vendor;
  77         cardbus_product_id_t    p_product;
  78         njsc32_model_t          p_model;
  79         int                     p_clk;          /* one of NJSC32_CLK_* */
  80 } njsc32_cardbus_products[] = {
  81         { PCI_VENDOR_IODATA,    PCI_PRODUCT_IODATA_CBSCII,
  82           NJSC32_MODEL_32BI,    NJSC32_CLK_40M },
  83         { PCI_VENDOR_WORKBIT,   PCI_PRODUCT_WORKBIT_NJSC32BI,
  84           NJSC32_MODEL_32BI,    NJSC32_CLK_40M },
  85         { PCI_VENDOR_WORKBIT,   PCI_PRODUCT_WORKBIT_NJSC32UDE,
  86           NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE,    NJSC32_CLK_40M },
  87         { PCI_VENDOR_WORKBIT,   PCI_PRODUCT_WORKBIT_NJSC32BI_KME,
  88           NJSC32_MODEL_32BI,    NJSC32_CLK_40M },
  89
  90         { 0,                            0,
  91           NJSC32_MODEL_INVALID,         0 },
  92 };
  93
  94 static const struct njsc32_cardbus_product *
  95 njs_cardbus_lookup(const struct cardbus_attach_args *ca)
  96 {
  97         const struct njsc32_cardbus_product *p;
  98
  99         for (p = njsc32_cardbus_products;
 100             p->p_model != NJSC32_MODEL_INVALID; p++) {
 101                 if (CARDBUS_VENDOR(ca->ca_id) == p->p_vendor &&
 102                     CARDBUS_PRODUCT(ca->ca_id) == p->p_product)
 103                         return p;
 104         }
 105
 106         return NULL;
 107 }
 108
 109 static int
 110 njs_cardbus_match(device_t parent, cfdata_t match, void *aux)
 111 {
 112         struct cardbus_attach_args *ca = aux;
 113
 114         if (njs_cardbus_lookup(ca))
 115                 return 1;
 116
 117         return 0;
 118 }
 119
 120 static void
 121 njs_cardbus_attach(device_t parent, device_t self, void *aux)
 122 {
 123         struct cardbus_attach_args *ca = aux;
 124         struct njsc32_cardbus_softc *csc = device_private(self);
 125         struct njsc32_softc *sc = &csc->sc_njsc32;
 126         const struct njsc32_cardbus_product *prod;
 127         cardbus_devfunc_t ct = ca->ca_ct;
 128         cardbus_chipset_tag_t cc = ct->ct_cc;
 129         cardbus_function_tag_t cf = ct->ct_cf;
 130         pcireg_t reg;
 131         int csr;
 132         u_int8_t latency = 0x20;
 133
 134         if ((prod = njs_cardbus_lookup(ca)) == NULL)
 135                 panic("njs_cardbus_attach");
 136
 137         printf(": Workbit NinjaSCSI-32 SCSI adapter\n");
 138         sc->sc_dev = self;
 139         sc->sc_model = prod->p_model;
 140         sc->sc_clk = prod->p_clk;
 141
 142         csc->sc_ct = ct;
 143         csc->sc_tag = ca->ca_tag;
 144         csc->sc_intrline = ca->ca_intrline;
 145
 146         /*
 147          * Map the device.
 148          */
 149         csr = PCI_COMMAND_MASTER_ENABLE;
 150
 151         /*
 152          * Map registers.
 153          * Try memory map first, and then try I/O.
 154          */
 155         if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM,
 156             PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
 157             &sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) {
 158                 if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph,
 159                     NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) {
 160                         /* failed -- undo map and try I/O */
 161                         Cardbus_mapreg_unmap(csc->sc_ct,
 162                             NJSC32_CARDBUS_BASEADDR_MEM,
 163                             sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size);
 164                         goto try_io;
 165                 }
 166 #ifdef NJSC32_DEBUG
 167                 printf("%s: memory space mapped\n", device_xname(self));
 168 #endif
 169                 csr |= PCI_COMMAND_MEM_ENABLE;
 170                 sc->sc_flags = NJSC32_MEM_MAPPED;
 171                 (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
 172         } else {
 173         try_io:
 174                 if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO,
 175                     PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh,
 176                     NULL, &csc->sc_regmap_size) == 0) {
 177 #ifdef NJSC32_DEBUG
 178                         printf("%s: io space mapped\n", device_xname(self));
 179 #endif
 180                         csr |= PCI_COMMAND_IO_ENABLE;
 181                         sc->sc_flags = NJSC32_IO_MAPPED;
 182                         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE);
 183                 } else {
 184                         aprint_error_dev(self, "unable to map device registers\n");
 185                         return;
 186                 }
 187         }
 188
 189         /* Make sure the right access type is on the CardBus bridge. */
 190         (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
 191
 192         /* Enable the appropriate bits in the PCI CSR. */
 193         reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
 194         reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
 195         reg |= csr;
 196         cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
 197
 198         /*
 199          * Make sure the latency timer is set to some reasonable
 200          * value.
 201          */
 202         reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG);
 203         if (CARDBUS_LATTIMER(reg) < latency) {
 204                 reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
 205                 reg |= (latency << CARDBUS_LATTIMER_SHIFT);
 206                 cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg);
 207         }
 208
 209         sc->sc_dmat = ca->ca_dmat;
 210
 211         /*
 212          * Establish the interrupt.
 213          */
 214         sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
 215             njsc32_intr, sc);
 216         if (sc->sc_ih == NULL) {
 217                 aprint_error_dev(self,
 218                                  "unable to establish interrupt\n");
 219                 return;
 220         }
 221
 222         /* CardBus device cannot supply termination power. */
 223         sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR;
 224
 225         /* attach */
 226         njsc32_attach(sc);
 227 }
 228
 229 static int
 230 njs_cardbus_detach(device_t self, int flags)
 231 {
 232         struct njsc32_cardbus_softc *csc = device_private(self);
 233         struct njsc32_softc *sc = &csc->sc_njsc32;
 234         int rv;
 235
 236         rv = njsc32_detach(sc, flags);
 237         if (rv)
 238                 return rv;
 239
 240         if (sc->sc_ih)
 241                 cardbus_intr_disestablish(csc->sc_ct->ct_cc,
 242                     csc->sc_ct->ct_cf, sc->sc_ih);
 243
 244         if (sc->sc_flags & NJSC32_IO_MAPPED)
 245                 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO,
 246                     sc->sc_regt, sc->sc_regh, csc->sc_regmap_size);
 247         if (sc->sc_flags & NJSC32_MEM_MAPPED)
 248                 Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM,
 249                     sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size);
 250
 251         return 0;
 252 }