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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ic / atw.c
blob00897599f0ba34168a8f9d630a88e7c7a8116d8d
1 /* $NetBSD: atw.c,v 1.147 2009/11/12 19:30:49 dyoung Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.147 2009/11/12 19:30:49 dyoung Exp $");
38
39 #include "bpfilter.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/callout.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/ioctl.h>
49 #include <sys/errno.h>
50 #include <sys/device.h>
51 #include <sys/kauth.h>
52 #include <sys/time.h>
53 #include <lib/libkern/libkern.h>
54
55 #include <machine/endian.h>
56
57 #include <uvm/uvm_extern.h>
58
59 #include <net/if.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_ether.h>
63
64 #include <net80211/ieee80211_netbsd.h>
65 #include <net80211/ieee80211_var.h>
66 #include <net80211/ieee80211_radiotap.h>
67
68 #if NBPFILTER > 0
69 #include <net/bpf.h>
70 #endif
71
72 #include <sys/bus.h>
73 #include <sys/intr.h>
74
75 #include <dev/ic/atwreg.h>
76 #include <dev/ic/rf3000reg.h>
77 #include <dev/ic/si4136reg.h>
78 #include <dev/ic/atwvar.h>
79 #include <dev/ic/smc93cx6var.h>
80
81 /* XXX TBD open questions
82 *
83 *
84 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps
85 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC
86 * handle this for me?
87 *
88 */
89 /* device attachment
90 *
91 * print TOFS[012]
92 *
93 * device initialization
94 *
95 * clear ATW_FRCTL_MAXPSP to disable max power saving
96 * set ATW_TXBR_ALCUPDATE to enable ALC
97 * set TOFS[012]? (hope not)
98 * disable rx/tx
99 * set ATW_PAR_SWR (software reset)
100 * wait for ATW_PAR_SWR clear
101 * disable interrupts
102 * ack status register
103 * enable interrupts
104 *
105 * rx/tx initialization
106 *
107 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
108 * allocate and init descriptor rings
109 * write ATW_PAR_DSL (descriptor skip length)
110 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB
111 * write ATW_NAR_SQ for one/both transmit descriptor rings
112 * write ATW_NAR_SQ for one/both transmit descriptor rings
113 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
114 *
115 * rx/tx end
116 *
117 * stop DMA
118 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
119 * flush tx w/ ATW_NAR_HF
120 *
121 * scan
122 *
123 * initialize rx/tx
124 *
125 * BSS join: (re)association response
126 *
127 * set ATW_FRCTL_AID
128 *
129 * optimizations ???
130 *
131 */
132
133 #define ATW_REFSLAVE /* slavishly do what the reference driver does */
134
135 int atw_pseudo_milli = 1;
136 int atw_magic_delay1 = 100 * 1000;
137 int atw_magic_delay2 = 100 * 1000;
138 /* more magic multi-millisecond delays (units: microseconds) */
139 int atw_nar_delay = 20 * 1000;
140 int atw_magic_delay4 = 10 * 1000;
141 int atw_rf_delay1 = 10 * 1000;
142 int atw_rf_delay2 = 5 * 1000;
143 int atw_plcphd_delay = 2 * 1000;
144 int atw_bbp_io_enable_delay = 20 * 1000;
145 int atw_bbp_io_disable_delay = 2 * 1000;
146 int atw_writewep_delay = 1000;
147 int atw_beacon_len_adjust = 4;
148 int atw_dwelltime = 200;
149 int atw_xindiv2 = 0;
150
151 #ifdef ATW_DEBUG
152 int atw_debug = 0;
153
154 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x
155 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x
156 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x
157 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x
158 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x)
159 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x)
160
161 static void atw_dump_pkt(struct ifnet *, struct mbuf *);
162 static void atw_print_regs(struct atw_softc *, const char *);
163
164 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */
165 # ifdef ATW_BBPDEBUG
166 static void atw_rf3000_print(struct atw_softc *);
167 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *);
168 # endif /* ATW_BBPDEBUG */
169
170 # ifdef ATW_SYNDEBUG
171 static void atw_si4126_print(struct atw_softc *);
172 static int atw_si4126_read(struct atw_softc *, u_int, u_int *);
173 # endif /* ATW_SYNDEBUG */
174
175 #else
176 #define ATW_DPRINTF(x)
177 #define ATW_DPRINTF2(x)
178 #define ATW_DPRINTF3(x)
179 #define DPRINTF(sc, x) /* nothing */
180 #define DPRINTF2(sc, x) /* nothing */
181 #define DPRINTF3(sc, x) /* nothing */
182 #endif
183
184 /* ifnet methods */
185 int atw_init(struct ifnet *);
186 int atw_ioctl(struct ifnet *, u_long, void *);
187 void atw_start(struct ifnet *);
188 void atw_stop(struct ifnet *, int);
189 void atw_watchdog(struct ifnet *);
190
191 /* Device attachment */
192 void atw_attach(struct atw_softc *);
193 int atw_detach(struct atw_softc *);
194 static void atw_evcnt_attach(struct atw_softc *);
195 static void atw_evcnt_detach(struct atw_softc *);
196
197 /* Rx/Tx process */
198 int atw_add_rxbuf(struct atw_softc *, int);
199 void atw_idle(struct atw_softc *, u_int32_t);
200 void atw_rxdrain(struct atw_softc *);
201 void atw_txdrain(struct atw_softc *);
202
203 /* Device (de)activation and power state */
204 void atw_reset(struct atw_softc *);
205
206 /* Interrupt handlers */
207 void atw_linkintr(struct atw_softc *, u_int32_t);
208 void atw_rxintr(struct atw_softc *);
209 void atw_txintr(struct atw_softc *, uint32_t);
210
211 /* 802.11 state machine */
212 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int);
213 static void atw_next_scan(void *);
214 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *,
215 struct ieee80211_node *, int, int, u_int32_t);
216 static int atw_tune(struct atw_softc *);
217
218 /* Device initialization */
219 static void atw_bbp_io_init(struct atw_softc *);
220 static void atw_cfp_init(struct atw_softc *);
221 static void atw_cmdr_init(struct atw_softc *);
222 static void atw_ifs_init(struct atw_softc *);
223 static void atw_nar_init(struct atw_softc *);
224 static void atw_response_times_init(struct atw_softc *);
225 static void atw_rf_reset(struct atw_softc *);
226 static void atw_test1_init(struct atw_softc *);
227 static void atw_tofs0_init(struct atw_softc *);
228 static void atw_tofs2_init(struct atw_softc *);
229 static void atw_txlmt_init(struct atw_softc *);
230 static void atw_wcsr_init(struct atw_softc *);
231
232 /* Key management */
233 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *);
234 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *,
235 const u_int8_t[IEEE80211_ADDR_LEN]);
236 static void atw_key_update_begin(struct ieee80211com *);
237 static void atw_key_update_end(struct ieee80211com *);
238
239 /* RAM/ROM utilities */
240 static void atw_clear_sram(struct atw_softc *);
241 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int);
242 static int atw_read_srom(struct atw_softc *);
243
244 /* BSS setup */
245 static void atw_predict_beacon(struct atw_softc *);
246 static void atw_start_beacon(struct atw_softc *, int);
247 static void atw_write_bssid(struct atw_softc *);
248 static void atw_write_ssid(struct atw_softc *);
249 static void atw_write_sup_rates(struct atw_softc *);
250 static void atw_write_wep(struct atw_softc *);
251
252 /* Media */
253 static int atw_media_change(struct ifnet *);
254
255 static void atw_filter_setup(struct atw_softc *);
256
257 /* 802.11 utilities */
258 static uint64_t atw_get_tsft(struct atw_softc *);
259 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t,
260 uint32_t);
261 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *);
262 static void atw_node_free(struct ieee80211_node *);
263
264 /*
265 * Tuner/transceiver/modem
266 */
267 static void atw_bbp_io_enable(struct atw_softc *, int);
268
269 /* RFMD RF3000 Baseband Processor */
270 static int atw_rf3000_init(struct atw_softc *);
271 static int atw_rf3000_tune(struct atw_softc *, u_int);
272 static int atw_rf3000_write(struct atw_softc *, u_int, u_int);
273
274 /* Silicon Laboratories Si4126 RF/IF Synthesizer */
275 static void atw_si4126_tune(struct atw_softc *, u_int);
276 static void atw_si4126_write(struct atw_softc *, u_int, u_int);
277
278 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE;
279 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE;
280
281 const char *atw_tx_state[] = {
282 "STOPPED",
283 "RUNNING - read descriptor",
284 "RUNNING - transmitting",
285 "RUNNING - filling fifo", /* XXX */
286 "SUSPENDED",
287 "RUNNING -- write descriptor",
288 "RUNNING -- write last descriptor",
289 "RUNNING - fifo full"
290 };
291
292 const char *atw_rx_state[] = {
293 "STOPPED",
294 "RUNNING - read descriptor",
295 "RUNNING - check this packet, pre-fetch next",
296 "RUNNING - wait for reception",
297 "SUSPENDED",
298 "RUNNING - write descriptor",
299 "RUNNING - flush fifo",
300 "RUNNING - fifo drain"
301 };
302
303 static inline int
304 is_running(struct ifnet *ifp)
305 {
306 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP);
307 }
308
309 int
310 atw_activate(device_t self, enum devact act)
311 {
312 struct atw_softc *sc = device_private(self);
313
314 switch (act) {
315 case DVACT_DEACTIVATE:
316 if_deactivate(&sc->sc_if);
317 return 0;
318 default:
319 return EOPNOTSUPP;
320 }
321 }
322
323 bool
324 atw_suspend(device_t self, pmf_qual_t qual)
325 {
326 struct atw_softc *sc = device_private(self);
327
328 atw_rxdrain(sc);
329 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
330
331 return true;
332 }
333
334 /* Returns -1 on failure. */
335 static int
336 atw_read_srom(struct atw_softc *sc)
337 {
338 struct seeprom_descriptor sd;
339 uint32_t test0, fail_bits;
340
341 (void)memset(&sd, 0, sizeof(sd));
342
343 test0 = ATW_READ(sc, ATW_TEST0);
344
345 switch (sc->sc_rev) {
346 case ATW_REVISION_BA:
347 case ATW_REVISION_CA:
348 fail_bits = ATW_TEST0_EPNE;
349 break;
350 default:
351 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM;
352 break;
353 }
354 if ((test0 & fail_bits) != 0) {
355 aprint_error_dev(sc->sc_dev, "bad or missing/bad SROM\n");
356 return -1;
357 }
358
359 switch (test0 & ATW_TEST0_EPTYP_MASK) {
360 case ATW_TEST0_EPTYP_93c66:
361 ATW_DPRINTF(("%s: 93c66 SROM\n", device_xname(sc->sc_dev)));
362 sc->sc_sromsz = 512;
363 sd.sd_chip = C56_66;
364 break;
365 case ATW_TEST0_EPTYP_93c46:
366 ATW_DPRINTF(("%s: 93c46 SROM\n", device_xname(sc->sc_dev)));
367 sc->sc_sromsz = 128;
368 sd.sd_chip = C46;
369 break;
370 default:
371 printf("%s: unknown SROM type %" __PRIuBITS "\n",
372 device_xname(sc->sc_dev),
373 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK));
374 return -1;
375 }
376
377 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT);
378
379 if (sc->sc_srom == NULL) {
380 aprint_error_dev(sc->sc_dev, "unable to allocate SROM buffer\n");
381 return -1;
382 }
383
384 (void)memset(sc->sc_srom, 0, sc->sc_sromsz);
385
386 /* ADM8211 has a single 32-bit register for controlling the
387 * 93cx6 SROM. Bit SRS enables the serial port. There is no
388 * "ready" bit. The ADM8211 input/output sense is the reverse
389 * of read_seeprom's.
390 */
391 sd.sd_tag = sc->sc_st;
392 sd.sd_bsh = sc->sc_sh;
393 sd.sd_regsize = 4;
394 sd.sd_control_offset = ATW_SPR;
395 sd.sd_status_offset = ATW_SPR;
396 sd.sd_dataout_offset = ATW_SPR;
397 sd.sd_CK = ATW_SPR_SCLK;
398 sd.sd_CS = ATW_SPR_SCS;
399 sd.sd_DI = ATW_SPR_SDO;
400 sd.sd_DO = ATW_SPR_SDI;
401 sd.sd_MS = ATW_SPR_SRS;
402 sd.sd_RDY = 0;
403
404 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) {
405 aprint_error_dev(sc->sc_dev, "could not read SROM\n");
406 free(sc->sc_srom, M_DEVBUF);
407 return -1;
408 }
409 #ifdef ATW_DEBUG
410 {
411 int i;
412 ATW_DPRINTF(("\nSerial EEPROM:\n\t"));
413 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) {
414 if (((i % 8) == 0) && (i != 0)) {
415 ATW_DPRINTF(("\n\t"));
416 }
417 ATW_DPRINTF((" 0x%x", sc->sc_srom[i]));
418 }
419 ATW_DPRINTF(("\n"));
420 }
421 #endif /* ATW_DEBUG */
422 return 0;
423 }
424
425 #ifdef ATW_DEBUG
426 static void
427 atw_print_regs(struct atw_softc *sc, const char *where)
428 {
429 #define PRINTREG(sc, reg) \
430 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \
431 device_xname(sc->sc_dev), reg, ATW_READ(sc, reg)))
432
433 ATW_DPRINTF2(("%s: %s\n", device_xname(sc->sc_dev), where));
434
435 PRINTREG(sc, ATW_PAR);
436 PRINTREG(sc, ATW_FRCTL);
437 PRINTREG(sc, ATW_TDR);
438 PRINTREG(sc, ATW_WTDP);
439 PRINTREG(sc, ATW_RDR);
440 PRINTREG(sc, ATW_WRDP);
441 PRINTREG(sc, ATW_RDB);
442 PRINTREG(sc, ATW_CSR3A);
443 PRINTREG(sc, ATW_TDBD);
444 PRINTREG(sc, ATW_TDBP);
445 PRINTREG(sc, ATW_STSR);
446 PRINTREG(sc, ATW_CSR5A);
447 PRINTREG(sc, ATW_NAR);
448 PRINTREG(sc, ATW_CSR6A);
449 PRINTREG(sc, ATW_IER);
450 PRINTREG(sc, ATW_CSR7A);
451 PRINTREG(sc, ATW_LPC);
452 PRINTREG(sc, ATW_TEST1);
453 PRINTREG(sc, ATW_SPR);
454 PRINTREG(sc, ATW_TEST0);
455 PRINTREG(sc, ATW_WCSR);
456 PRINTREG(sc, ATW_WPDR);
457 PRINTREG(sc, ATW_GPTMR);
458 PRINTREG(sc, ATW_GPIO);
459 PRINTREG(sc, ATW_BBPCTL);
460 PRINTREG(sc, ATW_SYNCTL);
461 PRINTREG(sc, ATW_PLCPHD);
462 PRINTREG(sc, ATW_MMIWADDR);
463 PRINTREG(sc, ATW_MMIRADDR1);
464 PRINTREG(sc, ATW_MMIRADDR2);
465 PRINTREG(sc, ATW_TXBR);
466 PRINTREG(sc, ATW_CSR15A);
467 PRINTREG(sc, ATW_ALCSTAT);
468 PRINTREG(sc, ATW_TOFS2);
469 PRINTREG(sc, ATW_CMDR);
470 PRINTREG(sc, ATW_PCIC);
471 PRINTREG(sc, ATW_PMCSR);
472 PRINTREG(sc, ATW_PAR0);
473 PRINTREG(sc, ATW_PAR1);
474 PRINTREG(sc, ATW_MAR0);
475 PRINTREG(sc, ATW_MAR1);
476 PRINTREG(sc, ATW_ATIMDA0);
477 PRINTREG(sc, ATW_ABDA1);
478 PRINTREG(sc, ATW_BSSID0);
479 PRINTREG(sc, ATW_TXLMT);
480 PRINTREG(sc, ATW_MIBCNT);
481 PRINTREG(sc, ATW_BCNT);
482 PRINTREG(sc, ATW_TSFTH);
483 PRINTREG(sc, ATW_TSC);
484 PRINTREG(sc, ATW_SYNRF);
485 PRINTREG(sc, ATW_BPLI);
486 PRINTREG(sc, ATW_CAP0);
487 PRINTREG(sc, ATW_CAP1);
488 PRINTREG(sc, ATW_RMD);
489 PRINTREG(sc, ATW_CFPP);
490 PRINTREG(sc, ATW_TOFS0);
491 PRINTREG(sc, ATW_TOFS1);
492 PRINTREG(sc, ATW_IFST);
493 PRINTREG(sc, ATW_RSPT);
494 PRINTREG(sc, ATW_TSFTL);
495 PRINTREG(sc, ATW_WEPCTL);
496 PRINTREG(sc, ATW_WESK);
497 PRINTREG(sc, ATW_WEPCNT);
498 PRINTREG(sc, ATW_MACTEST);
499 PRINTREG(sc, ATW_FER);
500 PRINTREG(sc, ATW_FEMR);
501 PRINTREG(sc, ATW_FPSR);
502 PRINTREG(sc, ATW_FFER);
503 #undef PRINTREG
504 }
505 #endif /* ATW_DEBUG */
506
507 /*
508 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end.
509 */
510 void
511 atw_attach(struct atw_softc *sc)
512 {
513 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
514 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
515 };
516 struct ieee80211com *ic = &sc->sc_ic;
517 struct ifnet *ifp = &sc->sc_if;
518 int country_code, error, i, nrate, srom_major;
519 u_int32_t reg;
520 static const char *type_strings[] = {"Intersil (not supported)",
521 "RFMD", "Marvel (not supported)"};
522
523 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual);
524
525 sc->sc_txth = atw_txthresh_tab_lo;
526
527 SIMPLEQ_INIT(&sc->sc_txfreeq);
528 SIMPLEQ_INIT(&sc->sc_txdirtyq);
529
530 #ifdef ATW_DEBUG
531 atw_print_regs(sc, "atw_attach");
532 #endif /* ATW_DEBUG */
533
534 /*
535 * Allocate the control data structures, and create and load the
536 * DMA map for it.
537 */
538 if ((error = bus_dmamem_alloc(sc->sc_dmat,
539 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
540 1, &sc->sc_cdnseg, 0)) != 0) {
541 aprint_error_dev(sc->sc_dev,
542 "unable to allocate control data, error = %d\n",
543 error);
544 goto fail_0;
545 }
546
547 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg,
548 sizeof(struct atw_control_data), (void **)&sc->sc_control_data,
549 BUS_DMA_COHERENT)) != 0) {
550 aprint_error_dev(sc->sc_dev,
551 "unable to map control data, error = %d\n",
552 error);
553 goto fail_1;
554 }
555
556 if ((error = bus_dmamap_create(sc->sc_dmat,
557 sizeof(struct atw_control_data), 1,
558 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
559 aprint_error_dev(sc->sc_dev,
560 "unable to create control data DMA map, error = %d\n",
561 error);
562 goto fail_2;
563 }
564
565 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
566 sc->sc_control_data, sizeof(struct atw_control_data), NULL,
567 0)) != 0) {
568 aprint_error_dev(sc->sc_dev,
569 "unable to load control data DMA map, error = %d\n", error);
570 goto fail_3;
571 }
572
573 /*
574 * Create the transmit buffer DMA maps.
575 */
576 sc->sc_ntxsegs = ATW_NTXSEGS;
577 for (i = 0; i < ATW_TXQUEUELEN; i++) {
578 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
579 sc->sc_ntxsegs, MCLBYTES, 0, 0,
580 &sc->sc_txsoft[i].txs_dmamap)) != 0) {
581 aprint_error_dev(sc->sc_dev,
582 "unable to create tx DMA map %d, error = %d\n", i,
583 error);
584 goto fail_4;
585 }
586 }
587
588 /*
589 * Create the receive buffer DMA maps.
590 */
591 for (i = 0; i < ATW_NRXDESC; i++) {
592 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
593 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
594 aprint_error_dev(sc->sc_dev,
595 "unable to create rx DMA map %d, error = %d\n", i,
596 error);
597 goto fail_5;
598 }
599 }
600 for (i = 0; i < ATW_NRXDESC; i++) {
601 sc->sc_rxsoft[i].rxs_mbuf = NULL;
602 }
603
604 switch (sc->sc_rev) {
605 case ATW_REVISION_AB:
606 case ATW_REVISION_AF:
607 sc->sc_sramlen = ATW_SRAM_A_SIZE;
608 break;
609 case ATW_REVISION_BA:
610 case ATW_REVISION_CA:
611 sc->sc_sramlen = ATW_SRAM_B_SIZE;
612 break;
613 }
614
615 /* Reset the chip to a known state. */
616 atw_reset(sc);
617
618 if (atw_read_srom(sc) == -1)
619 return;
620
621 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
622 ATW_SR_RFTYPE_MASK);
623
624 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
625 ATW_SR_BBPTYPE_MASK);
626
627 if (sc->sc_rftype >= __arraycount(type_strings)) {
628 aprint_error_dev(sc->sc_dev, "unknown RF\n");
629 return;
630 }
631 if (sc->sc_bbptype >= __arraycount(type_strings)) {
632 aprint_error_dev(sc->sc_dev, "unknown BBP\n");
633 return;
634 }
635
636 printf("%s: %s RF, %s BBP", device_xname(sc->sc_dev),
637 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]);
638
639 /* XXX There exists a Linux driver which seems to use RFType = 0 for
640 * MARVEL. My bug, or theirs?
641 */
642
643 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
644
645 switch (sc->sc_rftype) {
646 case ATW_RFTYPE_INTERSIL:
647 reg |= ATW_SYNCTL_CS1;
648 break;
649 case ATW_RFTYPE_RFMD:
650 reg |= ATW_SYNCTL_CS0;
651 break;
652 case ATW_RFTYPE_MARVEL:
653 break;
654 }
655
656 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
657 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
658
659 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
660
661 switch (sc->sc_bbptype) {
662 case ATW_BBPTYPE_INTERSIL:
663 reg |= ATW_BBPCTL_TWI;
664 break;
665 case ATW_BBPTYPE_RFMD:
666 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |
667 ATW_BBPCTL_CCA_ACTLO;
668 break;
669 case ATW_BBPTYPE_MARVEL:
670 break;
671 case ATW_C_BBPTYPE_RFMD:
672 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n",
673 device_xname(sc->sc_dev));
674 break;
675 }
676
677 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;
678 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;
679
680 /*
681 * From this point forward, the attachment cannot fail. A failure
682 * before this point releases all resources that may have been
683 * allocated.
684 */
685 sc->sc_flags |= ATWF_ATTACHED;
686
687 ATW_DPRINTF((" SROM MAC %04x%04x%04x",
688 htole16(sc->sc_srom[ATW_SR_MAC00]),
689 htole16(sc->sc_srom[ATW_SR_MAC01]),
690 htole16(sc->sc_srom[ATW_SR_MAC10])));
691
692 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION],
693 ATW_SR_MAJOR_MASK);
694
695 if (srom_major < 2)
696 sc->sc_rf3000_options1 = 0;
697 else if (sc->sc_rev == ATW_REVISION_BA) {
698 sc->sc_rf3000_options1 =
699 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03],
700 ATW_SR_CR28_MASK);
701 } else
702 sc->sc_rf3000_options1 = 0;
703
704 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
705 ATW_SR_CR29_MASK);
706
707 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
708 ATW_SR_CTRY_MASK);
709
710 #define ADD_CHANNEL(_ic, _chan) do { \
711 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \
712 _ic->ic_channels[_chan].ic_freq = \
713 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\
714 } while (0)
715
716 /* Find available channels */
717 switch (country_code) {
718 case COUNTRY_MMK2: /* 1-14 */
719 ADD_CHANNEL(ic, 14);
720 /*FALLTHROUGH*/
721 case COUNTRY_ETSI: /* 1-13 */
722 for (i = 1; i <= 13; i++)
723 ADD_CHANNEL(ic, i);
724 break;
725 case COUNTRY_FCC: /* 1-11 */
726 case COUNTRY_IC: /* 1-11 */
727 for (i = 1; i <= 11; i++)
728 ADD_CHANNEL(ic, i);
729 break;
730 case COUNTRY_MMK: /* 14 */
731 ADD_CHANNEL(ic, 14);
732 break;
733 case COUNTRY_FRANCE: /* 10-13 */
734 for (i = 10; i <= 13; i++)
735 ADD_CHANNEL(ic, i);
736 break;
737 default: /* assume channels 10-11 */
738 case COUNTRY_SPAIN: /* 10-11 */
739 for (i = 10; i <= 11; i++)
740 ADD_CHANNEL(ic, i);
741 break;
742 }
743
744 /* Read the MAC address. */
745 reg = ATW_READ(sc, ATW_PAR0);
746 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK);
747 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK);
748 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK);
749 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK);
750 reg = ATW_READ(sc, ATW_PAR1);
751 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK);
752 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK);
753
754 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) {
755 printf(" could not get mac address, attach failed\n");
756 return;
757 }
758
759 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr));
760
761 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
762 ifp->if_softc = sc;
763 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST |
764 IFF_NOTRAILERS;
765 ifp->if_ioctl = atw_ioctl;
766 ifp->if_start = atw_start;
767 ifp->if_watchdog = atw_watchdog;
768 ifp->if_init = atw_init;
769 ifp->if_stop = atw_stop;
770 IFQ_SET_READY(&ifp->if_snd);
771
772 ic->ic_ifp = ifp;
773 ic->ic_phytype = IEEE80211_T_DS;
774 ic->ic_opmode = IEEE80211_M_STA;
775 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS |
776 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR;
777
778 nrate = 0;
779 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2;
780 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4;
781 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11;
782 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22;
783 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate;
784
785 /*
786 * Call MI attach routines.
787 */
788
789 if_attach(ifp);
790 ieee80211_ifattach(ic);
791
792 atw_evcnt_attach(sc);
793
794 sc->sc_newstate = ic->ic_newstate;
795 ic->ic_newstate = atw_newstate;
796
797 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
798 ic->ic_recv_mgmt = atw_recv_mgmt;
799
800 sc->sc_node_free = ic->ic_node_free;
801 ic->ic_node_free = atw_node_free;
802
803 sc->sc_node_alloc = ic->ic_node_alloc;
804 ic->ic_node_alloc = atw_node_alloc;
805
806 ic->ic_crypto.cs_key_delete = atw_key_delete;
807 ic->ic_crypto.cs_key_set = atw_key_set;
808 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin;
809 ic->ic_crypto.cs_key_update_end = atw_key_update_end;
810
811 /* possibly we should fill in our own sc_send_prresp, since
812 * the ADM8211 is probably sending probe responses in ad hoc
813 * mode.
814 */
815
816 /* complete initialization */
817 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status);
818 callout_init(&sc->sc_scan_ch, 0);
819
820 #if NBPFILTER > 0
821 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
822 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
823 #endif
824
825 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu));
826 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
827 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT);
828
829 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu));
830 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
831 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT);
832
833 ieee80211_announce(ic);
834 return;
835
836 /*
837 * Free any resources we've allocated during the failed attach
838 * attempt. Do this in reverse order and fall through.
839 */
840 fail_5:
841 for (i = 0; i < ATW_NRXDESC; i++) {
842 if (sc->sc_rxsoft[i].rxs_dmamap == NULL)
843 continue;
844 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap);
845 }
846 fail_4:
847 for (i = 0; i < ATW_TXQUEUELEN; i++) {
848 if (sc->sc_txsoft[i].txs_dmamap == NULL)
849 continue;
850 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap);
851 }
852 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
853 fail_3:
854 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
855 fail_2:
856 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
857 sizeof(struct atw_control_data));
858 fail_1:
859 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
860 fail_0:
861 return;
862 }
863
864 static struct ieee80211_node *
865 atw_node_alloc(struct ieee80211_node_table *nt)
866 {
867 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc;
868 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt);
869
870 DPRINTF(sc, ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni));
871 return ni;
872 }
873
874 static void
875 atw_node_free(struct ieee80211_node *ni)
876 {
877 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc;
878
879 DPRINTF(sc, ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni,
880 ether_sprintf(ni->ni_bssid)));
881 (*sc->sc_node_free)(ni);
882 }
883
884
885 static void
886 atw_test1_reset(struct atw_softc *sc)
887 {
888 switch (sc->sc_rev) {
889 case ATW_REVISION_BA:
890 if (1 /* XXX condition on transceiver type */) {
891 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR);
892 }
893 break;
894 case ATW_REVISION_CA:
895 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK);
896 break;
897 default:
898 break;
899 }
900 }
901
902 /*
903 * atw_reset:
904 *
905 * Perform a soft reset on the ADM8211.
906 */
907 void
908 atw_reset(struct atw_softc *sc)
909 {
910 int i;
911 uint32_t lpc;
912
913 ATW_WRITE(sc, ATW_NAR, 0x0);
914 DELAY(atw_nar_delay);
915
916 /* Reference driver has a cryptic remark indicating that this might
917 * power-on the chip. I know that it turns off power-saving....
918 */
919 ATW_WRITE(sc, ATW_FRCTL, 0x0);
920
921 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR);
922
923 for (i = 0; i < 50000 / atw_pseudo_milli; i++) {
924 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0)
925 break;
926 DELAY(atw_pseudo_milli);
927 }
928
929 /* ... and then pause 100ms longer for good measure. */
930 DELAY(atw_magic_delay1);
931
932 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", device_xname(sc->sc_dev), i));
933
934 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR))
935 aprint_error_dev(sc->sc_dev, "reset failed to complete\n");
936
937 /*
938 * Initialize the PCI Access Register.
939 */
940 sc->sc_busmode = ATW_PAR_PBL_8DW;
941
942 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
943 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev),
944 ATW_READ(sc, ATW_PAR), sc->sc_busmode));
945
946 atw_test1_reset(sc);
947
948 /* Turn off maximum power saving, etc. */
949 ATW_WRITE(sc, ATW_FRCTL, 0x0);
950
951 DELAY(atw_magic_delay2);
952
953 /* Recall EEPROM. */
954 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD);
955
956 DELAY(atw_magic_delay4);
957
958 lpc = ATW_READ(sc, ATW_LPC);
959
960 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc));
961
962 /* A reset seems to affect the SRAM contents, so put them into
963 * a known state.
964 */
965 atw_clear_sram(sc);
966
967 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid));
968 }
969
970 static void
971 atw_clear_sram(struct atw_softc *sc)
972 {
973 memset(sc->sc_sram, 0, sizeof(sc->sc_sram));
974 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
975 /* XXX not for revision 0x20. */
976 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen);
977 }
978
979 /* TBD atw_init
980 *
981 * set MAC based on ic->ic_bss->myaddr
982 * write WEP keys
983 * set TX rate
984 */
985
986 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass
987 * without receiving a beacon with the preferred BSSID & SSID.
988 * atw_write_bssid & atw_write_ssid set the BSSID & SSID.
989 */
990 static void
991 atw_wcsr_init(struct atw_softc *sc)
992 {
993 uint32_t wcsr;
994
995 wcsr = ATW_READ(sc, ATW_WCSR);
996 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
997 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK);
998 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */
999
1000 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n",
1001 device_xname(sc->sc_dev), __func__, ATW_READ(sc, ATW_WCSR)));
1002 }
1003
1004 /* Turn off power management. Set Rx store-and-forward mode. */
1005 static void
1006 atw_cmdr_init(struct atw_softc *sc)
1007 {
1008 uint32_t cmdr;
1009 cmdr = ATW_READ(sc, ATW_CMDR);
1010 cmdr &= ~ATW_CMDR_APM;
1011 cmdr |= ATW_CMDR_RTE;
1012 cmdr &= ~ATW_CMDR_DRT_MASK;
1013 cmdr |= ATW_CMDR_DRT_SF;
1014
1015 ATW_WRITE(sc, ATW_CMDR, cmdr);
1016 }
1017
1018 static void
1019 atw_tofs2_init(struct atw_softc *sc)
1020 {
1021 uint32_t tofs2;
1022 /* XXX this magic can probably be figured out from the RFMD docs */
1023 #ifndef ATW_REFSLAVE
1024 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
1025 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
1026 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
1027 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
1028 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
1029 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
1030 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
1031 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
1032 #else
1033 /* XXX new magic from reference driver source */
1034 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
1035 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */
1036 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */
1037 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
1038 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
1039 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
1040 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */
1041 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */
1042 #endif
1043 ATW_WRITE(sc, ATW_TOFS2, tofs2);
1044 }
1045
1046 static void
1047 atw_nar_init(struct atw_softc *sc)
1048 {
1049 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB);
1050 }
1051
1052 static void
1053 atw_txlmt_init(struct atw_softc *sc)
1054 {
1055 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) |
1056 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK));
1057 }
1058
1059 static void
1060 atw_test1_init(struct atw_softc *sc)
1061 {
1062 uint32_t test1;
1063
1064 test1 = ATW_READ(sc, ATW_TEST1);
1065 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL);
1066 /* XXX magic 0x1 */
1067 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
1068 ATW_WRITE(sc, ATW_TEST1, test1);
1069 }
1070
1071 static void
1072 atw_rf_reset(struct atw_softc *sc)
1073 {
1074 /* XXX this resets an Intersil RF front-end? */
1075 /* TBD condition on Intersil RFType? */
1076 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
1077 DELAY(atw_rf_delay1);
1078 ATW_WRITE(sc, ATW_SYNRF, 0);
1079 DELAY(atw_rf_delay2);
1080 }
1081
1082 /* Set 16 TU max duration for the contention-free period (CFP). */
1083 static void
1084 atw_cfp_init(struct atw_softc *sc)
1085 {
1086 uint32_t cfpp;
1087
1088 cfpp = ATW_READ(sc, ATW_CFPP);
1089 cfpp &= ~ATW_CFPP_CFPMD;
1090 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD);
1091 ATW_WRITE(sc, ATW_CFPP, cfpp);
1092 }
1093
1094 static void
1095 atw_tofs0_init(struct atw_softc *sc)
1096 {
1097 /* XXX I guess that the Cardbus clock is 22 MHz?
1098 * I am assuming that the role of ATW_TOFS0_USCNT is
1099 * to divide the bus clock to get a 1 MHz clock---the datasheet is not
1100 * very clear on this point. It says in the datasheet that it is
1101 * possible for the ADM8211 to accommodate bus speeds between 22 MHz
1102 * and 33 MHz; maybe this is the way? I see a binary-only driver write
1103 * these values. These values are also the power-on default.
1104 */
1105 ATW_WRITE(sc, ATW_TOFS0,
1106 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) |
1107 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
1108 }
1109
1110 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */
1111 static void
1112 atw_ifs_init(struct atw_softc *sc)
1113 {
1114 uint32_t ifst;
1115 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver.
1116 * Go figure.
1117 */
1118 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
1119 __SHIFTIN(22 * 10 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */,
1120 ATW_IFST_SIFS_MASK) |
1121 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
1122 __SHIFTIN(IEEE80211_DUR_DS_EIFS, ATW_IFST_EIFS_MASK);
1123
1124 ATW_WRITE(sc, ATW_IFST, ifst);
1125 }
1126
1127 static void
1128 atw_response_times_init(struct atw_softc *sc)
1129 {
1130 /* XXX More magic. Relates to ACK timing? The datasheet seems to
1131 * indicate that the MAC expects at least SIFS + MIRT microseconds
1132 * to pass after it transmits a frame that requires a response;
1133 * it waits at most SIFS + MART microseconds for the response.
1134 * Surely this is not the ACK timeout?
1135 */
1136 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) |
1137 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK));
1138 }
1139
1140 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx
1141 * engines read and write baseband registers after Rx and before
1142 * Tx, respectively.
1143 */
1144 static void
1145 atw_bbp_io_init(struct atw_softc *sc)
1146 {
1147 uint32_t mmiraddr2;
1148
1149 /* XXX The reference driver does this, but is it *really*
1150 * necessary?
1151 */
1152 switch (sc->sc_rev) {
1153 case ATW_REVISION_AB:
1154 case ATW_REVISION_AF:
1155 mmiraddr2 = 0x0;
1156 break;
1157 default:
1158 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2);
1159 mmiraddr2 &=
1160 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK);
1161 break;
1162 }
1163
1164 switch (sc->sc_bbptype) {
1165 case ATW_BBPTYPE_INTERSIL:
1166 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL);
1167 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL);
1168 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL;
1169 break;
1170 case ATW_BBPTYPE_MARVEL:
1171 /* TBD find out the Marvel settings. */
1172 break;
1173 case ATW_BBPTYPE_RFMD:
1174 default:
1175 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD);
1176 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD);
1177 mmiraddr2 |= ATW_MMIRADDR2_RFMD;
1178 break;
1179 }
1180 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2);
1181 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK);
1182 }
1183
1184 /*
1185 * atw_init: [ ifnet interface function ]
1186 *
1187 * Initialize the interface. Must be called at splnet().
1188 */
1189 int
1190 atw_init(struct ifnet *ifp)
1191 {
1192 struct atw_softc *sc = ifp->if_softc;
1193 struct ieee80211com *ic = &sc->sc_ic;
1194 struct atw_txsoft *txs;
1195 struct atw_rxsoft *rxs;
1196 int i, error = 0;
1197
1198 if (device_is_active(sc->sc_dev)) {
1199 /*
1200 * Cancel any pending I/O.
1201 */
1202 atw_stop(ifp, 0);
1203 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) ||
1204 !device_is_active(sc->sc_dev))
1205 return 0;
1206
1207 /*
1208 * Reset the chip to a known state.
1209 */
1210 atw_reset(sc);
1211
1212 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n",
1213 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan),
1214 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
1215
1216 atw_wcsr_init(sc);
1217
1218 atw_cmdr_init(sc);
1219
1220 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s.
1221 *
1222 * XXX Set transmit power for ATIM, RTS, Beacon.
1223 */
1224 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) |
1225 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK));
1226
1227 atw_tofs2_init(sc);
1228
1229 atw_nar_init(sc);
1230
1231 atw_txlmt_init(sc);
1232
1233 atw_test1_init(sc);
1234
1235 atw_rf_reset(sc);
1236
1237 atw_cfp_init(sc);
1238
1239 atw_tofs0_init(sc);
1240
1241 atw_ifs_init(sc);
1242
1243 /* XXX Fall asleep after one second of inactivity.
1244 * XXX A frame may only dribble in for 65536us.
1245 */
1246 ATW_WRITE(sc, ATW_RMD,
1247 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK));
1248
1249 atw_response_times_init(sc);
1250
1251 atw_bbp_io_init(sc);
1252
1253 ATW_WRITE(sc, ATW_STSR, 0xffffffff);
1254
1255 if ((error = atw_rf3000_init(sc)) != 0)
1256 goto out;
1257
1258 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
1259 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", device_xname(sc->sc_dev),
1260 ATW_READ(sc, ATW_PAR), sc->sc_busmode));
1261
1262 /*
1263 * Initialize the transmit descriptor ring.
1264 */
1265 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1266 for (i = 0; i < ATW_NTXDESC; i++) {
1267 sc->sc_txdescs[i].at_ctl = 0;
1268 /* no transmit chaining */
1269 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */;
1270 sc->sc_txdescs[i].at_buf2 =
1271 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i)));
1272 }
1273 /* use ring mode */
1274 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER);
1275 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC,
1276 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1277 sc->sc_txfree = ATW_NTXDESC;
1278 sc->sc_txnext = 0;
1279
1280 /*
1281 * Initialize the transmit job descriptors.
1282 */
1283 SIMPLEQ_INIT(&sc->sc_txfreeq);
1284 SIMPLEQ_INIT(&sc->sc_txdirtyq);
1285 for (i = 0; i < ATW_TXQUEUELEN; i++) {
1286 txs = &sc->sc_txsoft[i];
1287 txs->txs_mbuf = NULL;
1288 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1289 }
1290
1291 /*
1292 * Initialize the receive descriptor and receive job
1293 * descriptor rings.
1294 */
1295 for (i = 0; i < ATW_NRXDESC; i++) {
1296 rxs = &sc->sc_rxsoft[i];
1297 if (rxs->rxs_mbuf == NULL) {
1298 if ((error = atw_add_rxbuf(sc, i)) != 0) {
1299 aprint_error_dev(sc->sc_dev,
1300 "unable to allocate or map rx buffer %d, "
1301 "error = %d\n", i, error);
1302 /*
1303 * XXX Should attempt to run with fewer receive
1304 * XXX buffers instead of just failing.
1305 */
1306 atw_rxdrain(sc);
1307 goto out;
1308 }
1309 } else
1310 atw_init_rxdesc(sc, i);
1311 }
1312 sc->sc_rxptr = 0;
1313
1314 /*
1315 * Initialize the interrupt mask and enable interrupts.
1316 */
1317 /* normal interrupts */
1318 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI |
1319 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC;
1320
1321 /* abnormal interrupts */
1322 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT |
1323 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS |
1324 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
1325
1326 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF |
1327 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
1328 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU;
1329 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT |
1330 ATW_INTR_TRT;
1331
1332 sc->sc_linkint_mask &= sc->sc_inten;
1333 sc->sc_rxint_mask &= sc->sc_inten;
1334 sc->sc_txint_mask &= sc->sc_inten;
1335
1336 ATW_WRITE(sc, ATW_IER, sc->sc_inten);
1337 ATW_WRITE(sc, ATW_STSR, 0xffffffff);
1338
1339 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n",
1340 device_xname(sc->sc_dev), ATW_READ(sc, ATW_IER), sc->sc_inten));
1341
1342 /*
1343 * Give the transmit and receive rings to the ADM8211.
1344 */
1345 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr));
1346 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext));
1347
1348 sc->sc_txthresh = 0;
1349 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST |
1350 sc->sc_txth[sc->sc_txthresh].txth_opmode;
1351
1352 /* common 802.11 configuration */
1353 ic->ic_flags &= ~IEEE80211_F_IBSSON;
1354 switch (ic->ic_opmode) {
1355 case IEEE80211_M_STA:
1356 break;
1357 case IEEE80211_M_AHDEMO: /* XXX */
1358 case IEEE80211_M_IBSS:
1359 ic->ic_flags |= IEEE80211_F_IBSSON;
1360 /*FALLTHROUGH*/
1361 case IEEE80211_M_HOSTAP: /* XXX */
1362 break;
1363 case IEEE80211_M_MONITOR: /* XXX */
1364 break;
1365 }
1366
1367 switch (ic->ic_opmode) {
1368 case IEEE80211_M_AHDEMO:
1369 case IEEE80211_M_HOSTAP:
1370 #ifndef IEEE80211_NO_HOSTAP
1371 ic->ic_bss->ni_intval = ic->ic_lintval;
1372 ic->ic_bss->ni_rssi = 0;
1373 ic->ic_bss->ni_rstamp = 0;
1374 #endif /* !IEEE80211_NO_HOSTAP */
1375 break;
1376 default: /* XXX */
1377 break;
1378 }
1379
1380 sc->sc_wepctl = 0;
1381
1382 atw_write_ssid(sc);
1383 atw_write_sup_rates(sc);
1384 atw_write_wep(sc);
1385
1386 ic->ic_state = IEEE80211_S_INIT;
1387
1388 /*
1389 * Set the receive filter. This will start the transmit and
1390 * receive processes.
1391 */
1392 atw_filter_setup(sc);
1393
1394 /*
1395 * Start the receive process.
1396 */
1397 ATW_WRITE(sc, ATW_RDR, 0x1);
1398
1399 /*
1400 * Note that the interface is now running.
1401 */
1402 ifp->if_flags |= IFF_RUNNING;
1403
1404 /* send no beacons, yet. */
1405 atw_start_beacon(sc, 0);
1406
1407 if (ic->ic_opmode == IEEE80211_M_MONITOR)
1408 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1409 else
1410 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1411 out:
1412 if (error) {
1413 ifp->if_flags &= ~IFF_RUNNING;
1414 sc->sc_tx_timer = 0;
1415 ifp->if_timer = 0;
1416 printf("%s: interface not running\n", device_xname(sc->sc_dev));
1417 }
1418 #ifdef ATW_DEBUG
1419 atw_print_regs(sc, "end of init");
1420 #endif /* ATW_DEBUG */
1421
1422 return (error);
1423 }
1424
1425 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL.
1426 * 0: MAC control of RF3000/Si4126.
1427 *
1428 * Applies power, or selects RF front-end? Sets reset condition.
1429 *
1430 * TBD support non-RFMD BBP, non-SiLabs synth.
1431 */
1432 static void
1433 atw_bbp_io_enable(struct atw_softc *sc, int enable)
1434 {
1435 if (enable) {
1436 ATW_WRITE(sc, ATW_SYNRF,
1437 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST);
1438 DELAY(atw_bbp_io_enable_delay);
1439 } else {
1440 ATW_WRITE(sc, ATW_SYNRF, 0);
1441 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */
1442 }
1443 }
1444
1445 static int
1446 atw_tune(struct atw_softc *sc)
1447 {
1448 int rc;
1449 u_int chan;
1450 struct ieee80211com *ic = &sc->sc_ic;
1451
1452 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1453 if (chan == IEEE80211_CHAN_ANY)
1454 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__);
1455
1456 if (chan == sc->sc_cur_chan)
1457 return 0;
1458
1459 DPRINTF(sc, ("%s: chan %d -> %d\n", device_xname(sc->sc_dev),
1460 sc->sc_cur_chan, chan));
1461
1462 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST);
1463
1464 atw_si4126_tune(sc, chan);
1465 if ((rc = atw_rf3000_tune(sc, chan)) != 0)
1466 printf("%s: failed to tune channel %d\n", device_xname(sc->sc_dev),
1467 chan);
1468
1469 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
1470 DELAY(atw_nar_delay);
1471 ATW_WRITE(sc, ATW_RDR, 0x1);
1472
1473 if (rc == 0) {
1474 sc->sc_cur_chan = chan;
1475 sc->sc_rxtap.ar_chan_freq = sc->sc_txtap.at_chan_freq =
1476 htole16(ic->ic_curchan->ic_freq);
1477 sc->sc_rxtap.ar_chan_flags = sc->sc_txtap.at_chan_flags =
1478 htole16(ic->ic_curchan->ic_flags);
1479 }
1480
1481 return rc;
1482 }
1483
1484 #ifdef ATW_SYNDEBUG
1485 static void
1486 atw_si4126_print(struct atw_softc *sc)
1487 {
1488 struct ifnet *ifp = &sc->sc_if;
1489 u_int addr, val;
1490
1491 val = 0;
1492
1493 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
1494 return;
1495
1496 for (addr = 0; addr <= 8; addr++) {
1497 printf("%s: synth[%d] = ", device_xname(sc->sc_dev), addr);
1498 if (atw_si4126_read(sc, addr, &val) == 0) {
1499 printf("<unknown> (quitting print-out)\n");
1500 break;
1501 }
1502 printf("%05x\n", val);
1503 }
1504 }
1505 #endif /* ATW_SYNDEBUG */
1506
1507 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer.
1508 *
1509 * The RF/IF synthesizer produces two reference frequencies for
1510 * the RF2948B transceiver. The first frequency the RF2948B requires
1511 * is two times the so-called "intermediate frequency" (IF). Since
1512 * a SAW filter on the radio fixes the IF at 374 MHz, I program the
1513 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second
1514 * frequency required by the transceiver is the radio frequency
1515 * (RF). This is a superheterodyne transceiver; for f(chan) the
1516 * center frequency of the channel we are tuning, RF = f(chan) -
1517 * IF.
1518 *
1519 * XXX I am told by SiLabs that the Si4126 will accept a broader range
1520 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without*
1521 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it
1522 * works, but I have still programmed for XINDIV2 = 1 to be safe.
1523 */
1524 static void
1525 atw_si4126_tune(struct atw_softc *sc, u_int chan)
1526 {
1527 u_int mhz;
1528 u_int R;
1529 u_int32_t gpio;
1530 u_int16_t gain;
1531
1532 #ifdef ATW_SYNDEBUG
1533 atw_si4126_print(sc);
1534 #endif /* ATW_SYNDEBUG */
1535
1536 if (chan == 14)
1537 mhz = 2484;
1538 else
1539 mhz = 2412 + 5 * (chan - 1);
1540
1541 /* Tune IF to 748 MHz to suit the IF LO input of the
1542 * RF2494B, which is 2 x IF. No need to set an IF divider
1543 * because an IF in 526 MHz - 952 MHz is allowed.
1544 *
1545 * XIN is 44.000 MHz, so divide it by two to get allowable
1546 * range of 2-25 MHz. SiLabs tells me that this is not
1547 * strictly necessary.
1548 */
1549
1550 if (atw_xindiv2)
1551 R = 44;
1552 else
1553 R = 88;
1554
1555 /* Power-up RF, IF synthesizers. */
1556 atw_si4126_write(sc, SI4126_POWER,
1557 SI4126_POWER_PDIB|SI4126_POWER_PDRB);
1558
1559 /* set LPWR, too? */
1560 atw_si4126_write(sc, SI4126_MAIN,
1561 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0);
1562
1563 /* Set the phase-locked loop gain. If RF2 N > 2047, then
1564 * set KP2 to 1.
1565 *
1566 * REFDIF This is different from the reference driver, which
1567 * always sets SI4126_GAIN to 0.
1568 */
1569 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);
1570
1571 atw_si4126_write(sc, SI4126_GAIN, gain);
1572
1573 /* XIN = 44 MHz.
1574 *
1575 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496,
1576 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz.
1577 *
1578 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88
1579 * so that 1496/88 * 44 MHz = 748 MHz.
1580 */
1581 atw_si4126_write(sc, SI4126_IFN, 1496);
1582
1583 atw_si4126_write(sc, SI4126_IFR, R);
1584
1585 #ifndef ATW_REFSLAVE
1586 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because
1587 * then RF1 becomes the active RF synthesizer, even on the Si4126,
1588 * which has no RF1!
1589 */
1590 atw_si4126_write(sc, SI4126_RF1R, R);
1591
1592 atw_si4126_write(sc, SI4126_RF1N, mhz - 374);
1593 #endif
1594
1595 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF,
1596 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44.
1597 * Now let's multiply it to mhz. So mhz - IF = N.
1598 */
1599 atw_si4126_write(sc, SI4126_RF2R, R);
1600
1601 atw_si4126_write(sc, SI4126_RF2N, mhz - 374);
1602
1603 /* wait 100us from power-up for RF, IF to settle */
1604 DELAY(100);
1605
1606 gpio = ATW_READ(sc, ATW_GPIO);
1607 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK);
1608 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK);
1609
1610 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) {
1611 /* Set a Prism RF front-end to a special mode for channel 14?
1612 *
1613 * Apparently the SMC2635W needs this, although I don't think
1614 * it has a Prism RF.
1615 */
1616 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK);
1617 }
1618 ATW_WRITE(sc, ATW_GPIO, gpio);
1619
1620 #ifdef ATW_SYNDEBUG
1621 atw_si4126_print(sc);
1622 #endif /* ATW_SYNDEBUG */
1623 }
1624
1625 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna
1626 * diversity.
1627 *
1628 * !!!
1629 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR).
1630 * !!!
1631 */
1632 static int
1633 atw_rf3000_init(struct atw_softc *sc)
1634 {
1635 int rc = 0;
1636
1637 atw_bbp_io_enable(sc, 1);
1638
1639 /* CCA is acquisition sensitive */
1640 rc = atw_rf3000_write(sc, RF3000_CCACTL,
1641 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));
1642
1643 if (rc != 0)
1644 goto out;
1645
1646 /* enable diversity */
1647 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE);
1648
1649 if (rc != 0)
1650 goto out;
1651
1652 /* sensible setting from a binary-only driver */
1653 rc = atw_rf3000_write(sc, RF3000_GAINCTL,
1654 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK));
1655
1656 if (rc != 0)
1657 goto out;
1658
1659 /* magic from a binary-only driver */
1660 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL,
1661 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK));
1662
1663 if (rc != 0)
1664 goto out;
1665
1666 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD);
1667
1668 if (rc != 0)
1669 goto out;
1670
1671 /* XXX Reference driver remarks that Abocom sets this to 50.
1672 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit
1673 * in the "reserved" area of register RF3000_OPTIONS1.
1674 */
1675 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1);
1676
1677 if (rc != 0)
1678 goto out;
1679
1680 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2);
1681
1682 if (rc != 0)
1683 goto out;
1684
1685 out:
1686 atw_bbp_io_enable(sc, 0);
1687 return rc;
1688 }
1689
1690 #ifdef ATW_BBPDEBUG
1691 static void
1692 atw_rf3000_print(struct atw_softc *sc)
1693 {
1694 struct ifnet *ifp = &sc->sc_if;
1695 u_int addr, val;
1696
1697 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
1698 return;
1699
1700 for (addr = 0x01; addr <= 0x15; addr++) {
1701 printf("%s: bbp[%d] = \n", device_xname(sc->sc_dev), addr);
1702 if (atw_rf3000_read(sc, addr, &val) != 0) {
1703 printf("<unknown> (quitting print-out)\n");
1704 break;
1705 }
1706 printf("%08x\n", val);
1707 }
1708 }
1709 #endif /* ATW_BBPDEBUG */
1710
1711 /* Set the power settings on the BBP for channel `chan'. */
1712 static int
1713 atw_rf3000_tune(struct atw_softc *sc, u_int chan)
1714 {
1715 int rc = 0;
1716 u_int32_t reg;
1717 u_int16_t txpower, lpf_cutoff, lna_gs_thresh;
1718
1719 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)];
1720 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)];
1721 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)];
1722
1723 /* odd channels: LSB, even channels: MSB */
1724 if (chan % 2 == 1) {
1725 txpower &= 0xFF;
1726 lpf_cutoff &= 0xFF;
1727 lna_gs_thresh &= 0xFF;
1728 } else {
1729 txpower >>= 8;
1730 lpf_cutoff >>= 8;
1731 lna_gs_thresh >>= 8;
1732 }
1733
1734 #ifdef ATW_BBPDEBUG
1735 atw_rf3000_print(sc);
1736 #endif /* ATW_BBPDEBUG */
1737
1738 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, "
1739 "lna_gs_thresh %02x\n",
1740 device_xname(sc->sc_dev), chan, txpower, lpf_cutoff, lna_gs_thresh));
1741
1742 atw_bbp_io_enable(sc, 1);
1743
1744 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL,
1745 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)
1746 goto out;
1747
1748 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0)
1749 goto out;
1750
1751 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0)
1752 goto out;
1753
1754 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0);
1755
1756 if (rc != 0)
1757 goto out;
1758
1759 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY);
1760
1761 if (rc != 0)
1762 goto out;
1763
1764 #ifdef ATW_BBPDEBUG
1765 atw_rf3000_print(sc);
1766 #endif /* ATW_BBPDEBUG */
1767
1768 out:
1769 atw_bbp_io_enable(sc, 0);
1770
1771 /* set beacon, rts, atim transmit power */
1772 reg = ATW_READ(sc, ATW_PLCPHD);
1773 reg &= ~ATW_PLCPHD_SERVICE_MASK;
1774 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK),
1775 ATW_PLCPHD_SERVICE_MASK);
1776 ATW_WRITE(sc, ATW_PLCPHD, reg);
1777 DELAY(atw_plcphd_delay);
1778
1779 return rc;
1780 }
1781
1782 /* Write a register on the RF3000 baseband processor using the
1783 * registers provided by the ADM8211 for this purpose.
1784 *
1785 * Return 0 on success.
1786 */
1787 static int
1788 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
1789 {
1790 u_int32_t reg;
1791 int i;
1792
1793 reg = sc->sc_bbpctl_wr |
1794 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) |
1795 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
1796
1797 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) {
1798 ATW_WRITE(sc, ATW_BBPCTL, reg);
1799 DELAY(2 * atw_pseudo_milli);
1800 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0)
1801 break;
1802 }
1803
1804 if (i < 0) {
1805 printf("%s: BBPCTL still busy\n", device_xname(sc->sc_dev));
1806 return ETIMEDOUT;
1807 }
1808 return 0;
1809 }
1810
1811 /* Read a register on the RF3000 baseband processor using the registers
1812 * the ADM8211 provides for this purpose.
1813 *
1814 * The 7-bit register address is addr. Record the 8-bit data in the register
1815 * in *val.
1816 *
1817 * Return 0 on success.
1818 *
1819 * XXX This does not seem to work. The ADM8211 must require more or
1820 * different magic to read the chip than to write it. Possibly some
1821 * of the magic I have derived from a binary-only driver concerns
1822 * the "chip address" (see the RF3000 manual).
1823 */
1824 #ifdef ATW_BBPDEBUG
1825 static int
1826 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val)
1827 {
1828 u_int32_t reg;
1829 int i;
1830
1831 for (i = 1000; --i >= 0; ) {
1832 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0)
1833 break;
1834 DELAY(100);
1835 }
1836
1837 if (i < 0) {
1838 printf("%s: start atw_rf3000_read, BBPCTL busy\n",
1839 device_xname(sc->sc_dev));
1840 return ETIMEDOUT;
1841 }
1842
1843 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
1844
1845 ATW_WRITE(sc, ATW_BBPCTL, reg);
1846
1847 for (i = 1000; --i >= 0; ) {
1848 DELAY(100);
1849 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0)
1850 break;
1851 }
1852
1853 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD);
1854
1855 if (i < 0) {
1856 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n",
1857 device_xname(sc->sc_dev), reg);
1858 return ETIMEDOUT;
1859 }
1860 if (val != NULL)
1861 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK);
1862 return 0;
1863 }
1864 #endif /* ATW_BBPDEBUG */
1865
1866 /* Write a register on the Si4126 RF/IF synthesizer using the registers
1867 * provided by the ADM8211 for that purpose.
1868 *
1869 * val is 18 bits of data, and val is the 4-bit address of the register.
1870 *
1871 * Return 0 on success.
1872 */
1873 static void
1874 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val)
1875 {
1876 uint32_t bits, mask, reg;
1877 const int nbits = 22;
1878
1879 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
1880 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0);
1881
1882 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) |
1883 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK);
1884
1885 reg = ATW_SYNRF_SELSYN;
1886 /* reference driver: reset Si4126 serial bus to initial
1887 * conditions?
1888 */
1889 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
1890 ATW_WRITE(sc, ATW_SYNRF, reg);
1891
1892 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) {
1893 if ((bits & mask) != 0)
1894 reg |= ATW_SYNRF_SYNDATA;
1895 else
1896 reg &= ~ATW_SYNRF_SYNDATA;
1897 ATW_WRITE(sc, ATW_SYNRF, reg);
1898 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);
1899 ATW_WRITE(sc, ATW_SYNRF, reg);
1900 }
1901 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
1902 ATW_WRITE(sc, ATW_SYNRF, 0x0);
1903 }
1904
1905 /* Read 18-bit data from the 4-bit address addr in Si4126
1906 * RF synthesizer and write the data to *val. Return 0 on success.
1907 *
1908 * XXX This does not seem to work. The ADM8211 must require more or
1909 * different magic to read the chip than to write it.
1910 */
1911 #ifdef ATW_SYNDEBUG
1912 static int
1913 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val)
1914 {
1915 u_int32_t reg;
1916 int i;
1917
1918 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
1919
1920 for (i = 1000; --i >= 0; ) {
1921 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0)
1922 break;
1923 DELAY(100);
1924 }
1925
1926 if (i < 0) {
1927 printf("%s: start atw_si4126_read, SYNCTL busy\n",
1928 device_xname(sc->sc_dev));
1929 return ETIMEDOUT;
1930 }
1931
1932 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK);
1933
1934 ATW_WRITE(sc, ATW_SYNCTL, reg);
1935
1936 for (i = 1000; --i >= 0; ) {
1937 DELAY(100);
1938 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0)
1939 break;
1940 }
1941
1942 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD);
1943
1944 if (i < 0) {
1945 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n",
1946 device_xname(sc->sc_dev), reg);
1947 return ETIMEDOUT;
1948 }
1949 if (val != NULL)
1950 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL),
1951 ATW_SYNCTL_DATA_MASK);
1952 return 0;
1953 }
1954 #endif /* ATW_SYNDEBUG */
1955
1956 /* XXX is the endianness correct? test. */
1957 #define atw_calchash(addr) \
1958 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0))
1959
1960 /*
1961 * atw_filter_setup:
1962 *
1963 * Set the ADM8211's receive filter.
1964 */
1965 static void
1966 atw_filter_setup(struct atw_softc *sc)
1967 {
1968 struct ieee80211com *ic = &sc->sc_ic;
1969 struct ethercom *ec = &sc->sc_ec;
1970 struct ifnet *ifp = &sc->sc_if;
1971 int hash;
1972 u_int32_t hashes[2];
1973 struct ether_multi *enm;
1974 struct ether_multistep step;
1975
1976 /* According to comments in tlp_al981_filter_setup
1977 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its
1978 * multicast filter to be set while it is running. Hopefully
1979 * the ADM8211 is not the same!
1980 */
1981 if ((ifp->if_flags & IFF_RUNNING) != 0)
1982 atw_idle(sc, ATW_NAR_SR);
1983
1984 sc->sc_opmode &= ~(ATW_NAR_PB|ATW_NAR_PR|ATW_NAR_MM);
1985 ifp->if_flags &= ~IFF_ALLMULTI;
1986
1987 /* XXX in scan mode, do not filter packets. Maybe this is
1988 * unnecessary.
1989 */
1990 if (ic->ic_state == IEEE80211_S_SCAN ||
1991 (ifp->if_flags & IFF_PROMISC) != 0) {
1992 sc->sc_opmode |= ATW_NAR_PR | ATW_NAR_PB;
1993 goto allmulti;
1994 }
1995
1996 hashes[0] = hashes[1] = 0x0;
1997
1998 /*
1999 * Program the 64-bit multicast hash filter.
2000 */
2001 ETHER_FIRST_MULTI(step, ec, enm);
2002 while (enm != NULL) {
2003 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
2004 ETHER_ADDR_LEN) != 0)
2005 goto allmulti;
2006
2007 hash = atw_calchash(enm->enm_addrlo);
2008 hashes[hash >> 5] |= 1 << (hash & 0x1f);
2009 ETHER_NEXT_MULTI(step, enm);
2010 sc->sc_opmode |= ATW_NAR_MM;
2011 }
2012 ifp->if_flags &= ~IFF_ALLMULTI;
2013 goto setit;
2014
2015 allmulti:
2016 sc->sc_opmode |= ATW_NAR_MM;
2017 ifp->if_flags |= IFF_ALLMULTI;
2018 hashes[0] = hashes[1] = 0xffffffff;
2019
2020 setit:
2021 ATW_WRITE(sc, ATW_MAR0, hashes[0]);
2022 ATW_WRITE(sc, ATW_MAR1, hashes[1]);
2023 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2024 DELAY(atw_nar_delay);
2025 ATW_WRITE(sc, ATW_RDR, 0x1);
2026
2027 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", device_xname(sc->sc_dev),
2028 ATW_READ(sc, ATW_NAR), sc->sc_opmode));
2029 }
2030
2031 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match
2032 * a beacon's BSSID and SSID against the preferred BSSID and SSID
2033 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives
2034 * no beacon with the preferred BSSID and SSID in the number of
2035 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF.
2036 */
2037 static void
2038 atw_write_bssid(struct atw_softc *sc)
2039 {
2040 struct ieee80211com *ic = &sc->sc_ic;
2041 u_int8_t *bssid;
2042
2043 bssid = ic->ic_bss->ni_bssid;
2044
2045 ATW_WRITE(sc, ATW_BSSID0,
2046 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |
2047 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |
2048 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |
2049 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK));
2050
2051 ATW_WRITE(sc, ATW_ABDA1,
2052 (ATW_READ(sc, ATW_ABDA1) &
2053 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) |
2054 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |
2055 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK));
2056
2057 DPRINTF(sc, ("%s: BSSID %s -> ", device_xname(sc->sc_dev),
2058 ether_sprintf(sc->sc_bssid)));
2059 DPRINTF(sc, ("%s\n", ether_sprintf(bssid)));
2060
2061 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid));
2062 }
2063
2064 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th
2065 * 16-bit word.
2066 */
2067 static void
2068 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen)
2069 {
2070 u_int i;
2071 u_int8_t *ptr;
2072
2073 memcpy(&sc->sc_sram[ofs], buf, buflen);
2074
2075 KASSERT(ofs % 2 == 0 && buflen % 2 == 0);
2076
2077 KASSERT(buflen + ofs <= sc->sc_sramlen);
2078
2079 ptr = &sc->sc_sram[ofs];
2080
2081 for (i = 0; i < buflen; i += 2) {
2082 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR |
2083 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));
2084 DELAY(atw_writewep_delay);
2085
2086 ATW_WRITE(sc, ATW_WESK,
2087 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));
2088 DELAY(atw_writewep_delay);
2089 }
2090 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */
2091
2092 if (sc->sc_if.if_flags & IFF_DEBUG) {
2093 int n_octets = 0;
2094 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n",
2095 device_xname(sc->sc_dev), buflen, ofs, sc->sc_wepctl);
2096 for (i = 0; i < buflen; i++) {
2097 printf(" %02x", ptr[i]);
2098 if (++n_octets % 24 == 0)
2099 printf("\n");
2100 }
2101 if (n_octets % 24 != 0)
2102 printf("\n");
2103 }
2104 }
2105
2106 static int
2107 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
2108 {
2109 struct atw_softc *sc = ic->ic_ifp->if_softc;
2110 u_int keyix = k->wk_keyix;
2111
2112 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix));
2113
2114 if (keyix >= IEEE80211_WEP_NKID)
2115 return 0;
2116 if (k->wk_keylen != 0)
2117 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
2118
2119 return 1;
2120 }
2121
2122 static int
2123 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
2124 const u_int8_t mac[IEEE80211_ADDR_LEN])
2125 {
2126 struct atw_softc *sc = ic->ic_ifp->if_softc;
2127
2128 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix));
2129
2130 if (k->wk_keyix >= IEEE80211_WEP_NKID)
2131 return 0;
2132
2133 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
2134
2135 return 1;
2136 }
2137
2138 static void
2139 atw_key_update_begin(struct ieee80211com *ic)
2140 {
2141 #ifdef ATW_DEBUG
2142 struct ifnet *ifp = ic->ic_ifp;
2143 struct atw_softc *sc = ifp->if_softc;
2144 #endif
2145
2146 DPRINTF(sc, ("%s:\n", __func__));
2147 }
2148
2149 static void
2150 atw_key_update_end(struct ieee80211com *ic)
2151 {
2152 struct ifnet *ifp = ic->ic_ifp;
2153 struct atw_softc *sc = ifp->if_softc;
2154
2155 DPRINTF(sc, ("%s:\n", __func__));
2156
2157 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0)
2158 return;
2159 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
2160 return;
2161 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST);
2162 atw_write_wep(sc);
2163 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2164 DELAY(atw_nar_delay);
2165 ATW_WRITE(sc, ATW_RDR, 0x1);
2166 }
2167
2168 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */
2169 static void
2170 atw_write_wep(struct atw_softc *sc)
2171 {
2172 #if 0
2173 struct ieee80211com *ic = &sc->sc_ic;
2174 u_int32_t reg;
2175 int i;
2176 #endif
2177 /* SRAM shared-key record format: key0 flags key1 ... key12 */
2178 u_int8_t buf[IEEE80211_WEP_NKID]
2179 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */];
2180
2181 sc->sc_wepctl = 0;
2182 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl);
2183
2184 memset(&buf[0][0], 0, sizeof(buf));
2185
2186 #if 0
2187 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
2188 if (ic->ic_nw_keys[i].wk_keylen > 5) {
2189 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT;
2190 } else if (ic->ic_nw_keys[i].wk_keylen != 0) {
2191 buf[i][1] = ATW_WEP_ENABLED;
2192 } else {
2193 buf[i][1] = 0;
2194 continue;
2195 }
2196 buf[i][0] = ic->ic_nw_keys[i].wk_key[0];
2197 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1],
2198 ic->ic_nw_keys[i].wk_keylen - 1);
2199 }
2200
2201 reg = ATW_READ(sc, ATW_MACTEST);
2202 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
2203 reg &= ~ATW_MACTEST_KEYID_MASK;
2204 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK);
2205 ATW_WRITE(sc, ATW_MACTEST, reg);
2206
2207 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0)
2208 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE;
2209
2210 switch (sc->sc_rev) {
2211 case ATW_REVISION_AB:
2212 case ATW_REVISION_AF:
2213 /* Bypass WEP on Rx. */
2214 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP;
2215 break;
2216 default:
2217 break;
2218 }
2219 #endif
2220
2221 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0],
2222 sizeof(buf));
2223
2224 sc->sc_flags |= ATWF_WEP_SRAM_VALID;
2225 }
2226
2227 static void
2228 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2229 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp)
2230 {
2231 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc;
2232
2233 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */
2234 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ)
2235 return;
2236
2237 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp);
2238
2239 switch (subtype) {
2240 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2241 case IEEE80211_FC0_SUBTYPE_BEACON:
2242 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2243 ic->ic_state == IEEE80211_S_RUN) {
2244 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc))
2245 (void)ieee80211_ibss_merge(ni);
2246 }
2247 break;
2248 default:
2249 break;
2250 }
2251 return;
2252 }
2253
2254 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211.
2255 * In ad hoc mode, the SSID is written to the beacons sent by the
2256 * ADM8211. In both ad hoc and infrastructure mode, beacons received
2257 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF
2258 * indications.
2259 */
2260 static void
2261 atw_write_ssid(struct atw_softc *sc)
2262 {
2263 struct ieee80211com *ic = &sc->sc_ic;
2264 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but
2265 * it only expects the element length, not its ID.
2266 */
2267 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)];
2268
2269 memset(buf, 0, sizeof(buf));
2270 buf[0] = ic->ic_bss->ni_esslen;
2271 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen);
2272
2273 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf,
2274 roundup(1 + ic->ic_bss->ni_esslen, 2));
2275 }
2276
2277 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211.
2278 * In ad hoc mode, the supported rates are written to beacons sent by the
2279 * ADM8211.
2280 */
2281 static void
2282 atw_write_sup_rates(struct atw_softc *sc)
2283 {
2284 struct ieee80211com *ic = &sc->sc_ic;
2285 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for
2286 * supported rates
2287 */
2288 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)];
2289
2290 memset(buf, 0, sizeof(buf));
2291
2292 buf[0] = ic->ic_bss->ni_rates.rs_nrates;
2293
2294 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates,
2295 ic->ic_bss->ni_rates.rs_nrates);
2296
2297 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf));
2298 }
2299
2300 /* Start/stop sending beacons. */
2301 void
2302 atw_start_beacon(struct atw_softc *sc, int start)
2303 {
2304 struct ieee80211com *ic = &sc->sc_ic;
2305 uint16_t chan;
2306 uint32_t bcnt, bpli, cap0, cap1, capinfo;
2307 size_t len;
2308
2309 if (!device_is_active(sc->sc_dev))
2310 return;
2311
2312 /* start beacons */
2313 len = sizeof(struct ieee80211_frame) +
2314 8 /* timestamp */ + 2 /* beacon interval */ +
2315 2 /* capability info */ +
2316 2 + ic->ic_bss->ni_esslen /* SSID element */ +
2317 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ +
2318 3 /* DS parameters */ +
2319 IEEE80211_CRC_LEN;
2320
2321 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK;
2322 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK;
2323 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK;
2324
2325 ATW_WRITE(sc, ATW_BCNT, bcnt);
2326 ATW_WRITE(sc, ATW_CAP1, cap1);
2327
2328 if (!start)
2329 return;
2330
2331 /* TBD use ni_capinfo */
2332
2333 capinfo = 0;
2334 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2335 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE;
2336 if (ic->ic_flags & IEEE80211_F_PRIVACY)
2337 capinfo |= IEEE80211_CAPINFO_PRIVACY;
2338
2339 switch (ic->ic_opmode) {
2340 case IEEE80211_M_IBSS:
2341 len += 4; /* IBSS parameters */
2342 capinfo |= IEEE80211_CAPINFO_IBSS;
2343 break;
2344 case IEEE80211_M_HOSTAP:
2345 /* XXX 6-byte minimum TIM */
2346 len += atw_beacon_len_adjust;
2347 capinfo |= IEEE80211_CAPINFO_ESS;
2348 break;
2349 default:
2350 return;
2351 }
2352
2353 /* set listen interval
2354 * XXX do software units agree w/ hardware?
2355 */
2356 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
2357 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);
2358
2359 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2360
2361 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK);
2362 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK);
2363 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK);
2364
2365 ATW_WRITE(sc, ATW_BCNT, bcnt);
2366 ATW_WRITE(sc, ATW_BPLI, bpli);
2367 ATW_WRITE(sc, ATW_CAP0, cap0);
2368 ATW_WRITE(sc, ATW_CAP1, cap1);
2369
2370 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n",
2371 device_xname(sc->sc_dev), bcnt));
2372
2373 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n",
2374 device_xname(sc->sc_dev), cap1));
2375 }
2376
2377 /* Return the 32 lsb of the last TSFT divisible by ival. */
2378 static inline uint32_t
2379 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival)
2380 {
2381 /* Following the reference driver's lead, I compute
2382 *
2383 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival)
2384 *
2385 * without using 64-bit arithmetic, using the following
2386 * relationship:
2387 *
2388 * (0x100000000 * H + L) % m
2389 * = ((0x100000000 % m) * H + L) % m
2390 * = (((0xffffffff + 1) % m) * H + L) % m
2391 * = ((0xffffffff % m + 1 % m) * H + L) % m
2392 * = ((0xffffffff % m + 1) * H + L) % m
2393 */
2394 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival;
2395 }
2396
2397 static uint64_t
2398 atw_get_tsft(struct atw_softc *sc)
2399 {
2400 int i;
2401 uint32_t tsfth, tsftl;
2402 for (i = 0; i < 2; i++) {
2403 tsfth = ATW_READ(sc, ATW_TSFTH);
2404 tsftl = ATW_READ(sc, ATW_TSFTL);
2405 if (ATW_READ(sc, ATW_TSFTH) == tsfth)
2406 break;
2407 }
2408 return ((uint64_t)tsfth << 32) | tsftl;
2409 }
2410
2411 /* If we've created an IBSS, write the TSF time in the ADM8211 to
2412 * the ieee80211com.
2413 *
2414 * Predict the next target beacon transmission time (TBTT) and
2415 * write it to the ADM8211.
2416 */
2417 static void
2418 atw_predict_beacon(struct atw_softc *sc)
2419 {
2420 #define TBTTOFS 20 /* TU */
2421
2422 struct ieee80211com *ic = &sc->sc_ic;
2423 uint64_t tsft;
2424 uint32_t ival, past_even, tbtt, tsfth, tsftl;
2425 union {
2426 uint64_t word;
2427 uint8_t tstamp[8];
2428 } u;
2429
2430 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) ||
2431 ((ic->ic_opmode == IEEE80211_M_IBSS) &&
2432 (ic->ic_flags & IEEE80211_F_SIBSS))) {
2433 tsft = atw_get_tsft(sc);
2434 u.word = htole64(tsft);
2435 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0],
2436 sizeof(ic->ic_bss->ni_tstamp));
2437 } else
2438 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf);
2439
2440 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU;
2441
2442 tsftl = tsft & 0xFFFFFFFF;
2443 tsfth = tsft >> 32;
2444
2445 /* We sent/received the last beacon `past' microseconds
2446 * after the interval divided the TSF timer.
2447 */
2448 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival);
2449
2450 /* Skip ten beacons so that the TBTT cannot pass before
2451 * we've programmed it. Ten is an arbitrary number.
2452 */
2453 tbtt = past_even + ival * 10;
2454
2455 ATW_WRITE(sc, ATW_TOFS1,
2456 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) |
2457 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |
2458 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
2459 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK));
2460 #undef TBTTOFS
2461 }
2462
2463 static void
2464 atw_next_scan(void *arg)
2465 {
2466 struct atw_softc *sc = arg;
2467 struct ieee80211com *ic = &sc->sc_ic;
2468 int s;
2469
2470 /* don't call atw_start w/o network interrupts blocked */
2471 s = splnet();
2472 if (ic->ic_state == IEEE80211_S_SCAN)
2473 ieee80211_next_scan(ic);
2474 splx(s);
2475 }
2476
2477 /* Synchronize the hardware state with the software state. */
2478 static int
2479 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2480 {
2481 struct ifnet *ifp = ic->ic_ifp;
2482 struct atw_softc *sc = ifp->if_softc;
2483 enum ieee80211_state ostate;
2484 int error = 0;
2485
2486 ostate = ic->ic_state;
2487 callout_stop(&sc->sc_scan_ch);
2488
2489 switch (nstate) {
2490 case IEEE80211_S_AUTH:
2491 case IEEE80211_S_ASSOC:
2492 atw_write_bssid(sc);
2493 error = atw_tune(sc);
2494 break;
2495 case IEEE80211_S_INIT:
2496 callout_stop(&sc->sc_scan_ch);
2497 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
2498 atw_start_beacon(sc, 0);
2499 break;
2500 case IEEE80211_S_SCAN:
2501 error = atw_tune(sc);
2502 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000,
2503 atw_next_scan, sc);
2504 break;
2505 case IEEE80211_S_RUN:
2506 error = atw_tune(sc);
2507 atw_write_bssid(sc);
2508 atw_write_ssid(sc);
2509 atw_write_sup_rates(sc);
2510
2511 if (ic->ic_opmode == IEEE80211_M_AHDEMO ||
2512 ic->ic_opmode == IEEE80211_M_MONITOR)
2513 break;
2514
2515 /* set listen interval
2516 * XXX do software units agree w/ hardware?
2517 */
2518 ATW_WRITE(sc, ATW_BPLI,
2519 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
2520 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval,
2521 ATW_BPLI_LI_MASK));
2522
2523 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", device_xname(sc->sc_dev),
2524 ATW_READ(sc, ATW_BPLI)));
2525
2526 atw_predict_beacon(sc);
2527
2528 switch (ic->ic_opmode) {
2529 case IEEE80211_M_AHDEMO:
2530 case IEEE80211_M_HOSTAP:
2531 case IEEE80211_M_IBSS:
2532 atw_start_beacon(sc, 1);
2533 break;
2534 case IEEE80211_M_MONITOR:
2535 case IEEE80211_M_STA:
2536 break;
2537 }
2538
2539 break;
2540 }
2541 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg);
2542 }
2543
2544 /*
2545 * atw_add_rxbuf:
2546 *
2547 * Add a receive buffer to the indicated descriptor.
2548 */
2549 int
2550 atw_add_rxbuf(struct atw_softc *sc, int idx)
2551 {
2552 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx];
2553 struct mbuf *m;
2554 int error;
2555
2556 MGETHDR(m, M_DONTWAIT, MT_DATA);
2557 if (m == NULL)
2558 return (ENOBUFS);
2559
2560 MCLGET(m, M_DONTWAIT);
2561 if ((m->m_flags & M_EXT) == 0) {
2562 m_freem(m);
2563 return (ENOBUFS);
2564 }
2565
2566 if (rxs->rxs_mbuf != NULL)
2567 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2568
2569 rxs->rxs_mbuf = m;
2570
2571 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
2572 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
2573 BUS_DMA_READ|BUS_DMA_NOWAIT);
2574 if (error) {
2575 aprint_error_dev(sc->sc_dev, "can't load rx DMA map %d, error = %d\n",
2576 idx, error);
2577 panic("atw_add_rxbuf"); /* XXX */
2578 }
2579
2580 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2581 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2582
2583 atw_init_rxdesc(sc, idx);
2584
2585 return (0);
2586 }
2587
2588 /*
2589 * Release any queued transmit buffers.
2590 */
2591 void
2592 atw_txdrain(struct atw_softc *sc)
2593 {
2594 struct atw_txsoft *txs;
2595
2596 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
2597 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
2598 if (txs->txs_mbuf != NULL) {
2599 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2600 m_freem(txs->txs_mbuf);
2601 txs->txs_mbuf = NULL;
2602 }
2603 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2604 sc->sc_txfree += txs->txs_ndescs;
2605 }
2606
2607 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 ||
2608 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) ||
2609 sc->sc_txfree != ATW_NTXDESC));
2610 sc->sc_if.if_flags &= ~IFF_OACTIVE;
2611 sc->sc_tx_timer = 0;
2612 }
2613
2614 /*
2615 * atw_stop: [ ifnet interface function ]
2616 *
2617 * Stop transmission on the interface.
2618 */
2619 void
2620 atw_stop(struct ifnet *ifp, int disable)
2621 {
2622 struct atw_softc *sc = ifp->if_softc;
2623 struct ieee80211com *ic = &sc->sc_ic;
2624
2625 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2626
2627 if (device_is_active(sc->sc_dev)) {
2628 /* Disable interrupts. */
2629 ATW_WRITE(sc, ATW_IER, 0);
2630
2631 /* Stop the transmit and receive processes. */
2632 ATW_WRITE(sc, ATW_NAR, 0);
2633 DELAY(atw_nar_delay);
2634 ATW_WRITE(sc, ATW_TDBD, 0);
2635 ATW_WRITE(sc, ATW_TDBP, 0);
2636 ATW_WRITE(sc, ATW_RDB, 0);
2637 }
2638
2639 sc->sc_opmode = 0;
2640
2641 atw_txdrain(sc);
2642
2643 /*
2644 * Mark the interface down and cancel the watchdog timer.
2645 */
2646 ifp->if_flags &= ~IFF_RUNNING;
2647 ifp->if_timer = 0;
2648
2649 if (disable)
2650 pmf_device_suspend(sc->sc_dev, &sc->sc_qual);
2651 }
2652
2653 /*
2654 * atw_rxdrain:
2655 *
2656 * Drain the receive queue.
2657 */
2658 void
2659 atw_rxdrain(struct atw_softc *sc)
2660 {
2661 struct atw_rxsoft *rxs;
2662 int i;
2663
2664 for (i = 0; i < ATW_NRXDESC; i++) {
2665 rxs = &sc->sc_rxsoft[i];
2666 if (rxs->rxs_mbuf == NULL)
2667 continue;
2668 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2669 m_freem(rxs->rxs_mbuf);
2670 rxs->rxs_mbuf = NULL;
2671 }
2672 }
2673
2674 /*
2675 * atw_detach:
2676 *
2677 * Detach an ADM8211 interface.
2678 */
2679 int
2680 atw_detach(struct atw_softc *sc)
2681 {
2682 struct ifnet *ifp = &sc->sc_if;
2683 struct atw_rxsoft *rxs;
2684 struct atw_txsoft *txs;
2685 int i;
2686
2687 /*
2688 * Succeed now if there isn't any work to do.
2689 */
2690 if ((sc->sc_flags & ATWF_ATTACHED) == 0)
2691 return (0);
2692
2693 pmf_device_deregister(sc->sc_dev);
2694
2695 callout_stop(&sc->sc_scan_ch);
2696
2697 ieee80211_ifdetach(&sc->sc_ic);
2698 if_detach(ifp);
2699
2700 for (i = 0; i < ATW_NRXDESC; i++) {
2701 rxs = &sc->sc_rxsoft[i];
2702 if (rxs->rxs_mbuf != NULL) {
2703 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2704 m_freem(rxs->rxs_mbuf);
2705 rxs->rxs_mbuf = NULL;
2706 }
2707 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap);
2708 }
2709 for (i = 0; i < ATW_TXQUEUELEN; i++) {
2710 txs = &sc->sc_txsoft[i];
2711 if (txs->txs_mbuf != NULL) {
2712 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2713 m_freem(txs->txs_mbuf);
2714 txs->txs_mbuf = NULL;
2715 }
2716 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap);
2717 }
2718 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
2719 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
2720 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
2721 sizeof(struct atw_control_data));
2722 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
2723
2724 if (sc->sc_srom)
2725 free(sc->sc_srom, M_DEVBUF);
2726
2727 atw_evcnt_detach(sc);
2728
2729 return (0);
2730 }
2731
2732 /* atw_shutdown: make sure the interface is stopped at reboot time. */
2733 bool
2734 atw_shutdown(device_t self, int flags)
2735 {
2736 struct atw_softc *sc = device_private(self);
2737
2738 atw_stop(&sc->sc_if, 1);
2739 return true;
2740 }
2741
2742 #if 0
2743 static void
2744 atw_workaround1(struct atw_softc *sc)
2745 {
2746 uint32_t test1;
2747
2748 test1 = ATW_READ(sc, ATW_TEST1);
2749
2750 sc->sc_misc_ev.ev_count++;
2751
2752 if ((test1 & ATW_TEST1_RXPKT1IN) != 0) {
2753 sc->sc_rxpkt1in_ev.ev_count++;
2754 return;
2755 }
2756 if (__SHIFTOUT(test1, ATW_TEST1_RRA_MASK) ==
2757 __SHIFTOUT(test1, ATW_TEST1_RWA_MASK)) {
2758 sc->sc_rxamatch_ev.ev_count++;
2759 return;
2760 }
2761 sc->sc_workaround1_ev.ev_count++;
2762 (void)atw_init(&sc->sc_if);
2763 }
2764 #endif
2765
2766 int
2767 atw_intr(void *arg)
2768 {
2769 struct atw_softc *sc = arg;
2770 struct ifnet *ifp = &sc->sc_if;
2771 u_int32_t status, rxstatus, txstatus, linkstatus;
2772 int handled = 0, txthresh;
2773
2774 #ifdef DEBUG
2775 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
2776 panic("%s: atw_intr: not enabled", device_xname(sc->sc_dev));
2777 #endif
2778
2779 /*
2780 * If the interface isn't running, the interrupt couldn't
2781 * possibly have come from us.
2782 */
2783 if ((ifp->if_flags & IFF_RUNNING) == 0 ||
2784 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
2785 return (0);
2786
2787 for (;;) {
2788 status = ATW_READ(sc, ATW_STSR);
2789
2790 if (status)
2791 ATW_WRITE(sc, ATW_STSR, status);
2792
2793 #ifdef ATW_DEBUG
2794 #define PRINTINTR(flag) do { \
2795 if ((status & flag) != 0) { \
2796 printf("%s" #flag, delim); \
2797 delim = ","; \
2798 } \
2799 } while (0)
2800
2801 if (atw_debug > 1 && status) {
2802 const char *delim = "<";
2803
2804 printf("%s: reg[STSR] = %x",
2805 device_xname(sc->sc_dev), status);
2806
2807 PRINTINTR(ATW_INTR_FBE);
2808 PRINTINTR(ATW_INTR_LINKOFF);
2809 PRINTINTR(ATW_INTR_LINKON);
2810 PRINTINTR(ATW_INTR_RCI);
2811 PRINTINTR(ATW_INTR_RDU);
2812 PRINTINTR(ATW_INTR_REIS);
2813 PRINTINTR(ATW_INTR_RPS);
2814 PRINTINTR(ATW_INTR_TCI);
2815 PRINTINTR(ATW_INTR_TDU);
2816 PRINTINTR(ATW_INTR_TLT);
2817 PRINTINTR(ATW_INTR_TPS);
2818 PRINTINTR(ATW_INTR_TRT);
2819 PRINTINTR(ATW_INTR_TUF);
2820 PRINTINTR(ATW_INTR_BCNTC);
2821 PRINTINTR(ATW_INTR_ATIME);
2822 PRINTINTR(ATW_INTR_TBTT);
2823 PRINTINTR(ATW_INTR_TSCZ);
2824 PRINTINTR(ATW_INTR_TSFTF);
2825 printf(">\n");
2826 }
2827 #undef PRINTINTR
2828 #endif /* ATW_DEBUG */
2829
2830 if ((status & sc->sc_inten) == 0)
2831 break;
2832
2833 handled = 1;
2834
2835 rxstatus = status & sc->sc_rxint_mask;
2836 txstatus = status & sc->sc_txint_mask;
2837 linkstatus = status & sc->sc_linkint_mask;
2838
2839 if (linkstatus) {
2840 atw_linkintr(sc, linkstatus);
2841 }
2842
2843 if (rxstatus) {
2844 /* Grab any new packets. */
2845 atw_rxintr(sc);
2846
2847 if (rxstatus & ATW_INTR_RDU) {
2848 printf("%s: receive ring overrun\n",
2849 device_xname(sc->sc_dev));
2850 /* Get the receive process going again. */
2851 ATW_WRITE(sc, ATW_RDR, 0x1);
2852 }
2853 }
2854
2855 if (txstatus) {
2856 /* Sweep up transmit descriptors. */
2857 atw_txintr(sc, txstatus);
2858
2859 if (txstatus & ATW_INTR_TLT) {
2860 DPRINTF(sc, ("%s: tx lifetime exceeded\n",
2861 device_xname(sc->sc_dev)));
2862 (void)atw_init(&sc->sc_if);
2863 }
2864
2865 if (txstatus & ATW_INTR_TRT) {
2866 DPRINTF(sc, ("%s: tx retry limit exceeded\n",
2867 device_xname(sc->sc_dev)));
2868 }
2869
2870 /* If Tx under-run, increase our transmit threshold
2871 * if another is available.
2872 */
2873 txthresh = sc->sc_txthresh + 1;
2874 if ((txstatus & ATW_INTR_TUF) &&
2875 sc->sc_txth[txthresh].txth_name != NULL) {
2876 /* Idle the transmit process. */
2877 atw_idle(sc, ATW_NAR_ST);
2878
2879 sc->sc_txthresh = txthresh;
2880 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF);
2881 sc->sc_opmode |=
2882 sc->sc_txth[txthresh].txth_opmode;
2883 printf("%s: transmit underrun; new "
2884 "threshold: %s\n", device_xname(sc->sc_dev),
2885 sc->sc_txth[txthresh].txth_name);
2886
2887 /* Set the new threshold and restart
2888 * the transmit process.
2889 */
2890 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2891 DELAY(atw_nar_delay);
2892 ATW_WRITE(sc, ATW_TDR, 0x1);
2893 /* XXX Log every Nth underrun from
2894 * XXX now on?
2895 */
2896 }
2897 }
2898
2899 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) {
2900 if (status & ATW_INTR_TPS)
2901 printf("%s: transmit process stopped\n",
2902 device_xname(sc->sc_dev));
2903 if (status & ATW_INTR_RPS)
2904 printf("%s: receive process stopped\n",
2905 device_xname(sc->sc_dev));
2906 (void)atw_init(ifp);
2907 break;
2908 }
2909
2910 if (status & ATW_INTR_FBE) {
2911 aprint_error_dev(sc->sc_dev, "fatal bus error\n");
2912 (void)atw_init(ifp);
2913 break;
2914 }
2915
2916 /*
2917 * Not handled:
2918 *
2919 * Transmit buffer unavailable -- normal
2920 * condition, nothing to do, really.
2921 *
2922 * Early receive interrupt -- not available on
2923 * all chips, we just use RI. We also only
2924 * use single-segment receive DMA, so this
2925 * is mostly useless.
2926 *
2927 * TBD others
2928 */
2929 }
2930
2931 /* Try to get more packets going. */
2932 atw_start(ifp);
2933
2934 return (handled);
2935 }
2936
2937 /*
2938 * atw_idle:
2939 *
2940 * Cause the transmit and/or receive processes to go idle.
2941 *
2942 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx
2943 * process in STSR if I clear SR or ST after the process has already
2944 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0
2945 * do not seem to be too reliable. Perhaps I have the sense of the
2946 * Rx bits switched with the Tx bits?
2947 */
2948 void
2949 atw_idle(struct atw_softc *sc, u_int32_t bits)
2950 {
2951 u_int32_t ackmask = 0, opmode, stsr, test0;
2952 int i, s;
2953
2954 s = splnet();
2955
2956 opmode = sc->sc_opmode & ~bits;
2957
2958 if (bits & ATW_NAR_SR)
2959 ackmask |= ATW_INTR_RPS;
2960
2961 if (bits & ATW_NAR_ST) {
2962 ackmask |= ATW_INTR_TPS;
2963 /* set ATW_NAR_HF to flush TX FIFO. */
2964 opmode |= ATW_NAR_HF;
2965 }
2966
2967 ATW_WRITE(sc, ATW_NAR, opmode);
2968 DELAY(atw_nar_delay);
2969
2970 for (i = 0; i < 1000; i++) {
2971 stsr = ATW_READ(sc, ATW_STSR);
2972 if ((stsr & ackmask) == ackmask)
2973 break;
2974 DELAY(10);
2975 }
2976
2977 ATW_WRITE(sc, ATW_STSR, stsr & ackmask);
2978
2979 if ((stsr & ackmask) == ackmask)
2980 goto out;
2981
2982 test0 = ATW_READ(sc, ATW_TEST0);
2983
2984 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 &&
2985 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) {
2986 printf("%s: transmit process not idle [%s]\n",
2987 device_xname(sc->sc_dev),
2988 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]);
2989 printf("%s: bits %08x test0 %08x stsr %08x\n",
2990 device_xname(sc->sc_dev), bits, test0, stsr);
2991 }
2992
2993 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 &&
2994 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) {
2995 DPRINTF2(sc, ("%s: receive process not idle [%s]\n",
2996 device_xname(sc->sc_dev),
2997 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)]));
2998 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n",
2999 device_xname(sc->sc_dev), bits, test0, stsr));
3000 }
3001 out:
3002 if ((bits & ATW_NAR_ST) != 0)
3003 atw_txdrain(sc);
3004 splx(s);
3005 return;
3006 }
3007
3008 /*
3009 * atw_linkintr:
3010 *
3011 * Helper; handle link-status interrupts.
3012 */
3013 void
3014 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus)
3015 {
3016 struct ieee80211com *ic = &sc->sc_ic;
3017
3018 if (ic->ic_state != IEEE80211_S_RUN)
3019 return;
3020
3021 if (linkstatus & ATW_INTR_LINKON) {
3022 DPRINTF(sc, ("%s: link on\n", device_xname(sc->sc_dev)));
3023 sc->sc_rescan_timer = 0;
3024 } else if (linkstatus & ATW_INTR_LINKOFF) {
3025 DPRINTF(sc, ("%s: link off\n", device_xname(sc->sc_dev)));
3026 if (ic->ic_opmode != IEEE80211_M_STA)
3027 return;
3028 sc->sc_rescan_timer = 3;
3029 sc->sc_if.if_timer = 1;
3030 }
3031 }
3032
3033 static inline int
3034 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh)
3035 {
3036 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
3037 return 0;
3038 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0)
3039 return 0;
3040 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0;
3041 }
3042
3043 /*
3044 * atw_rxintr:
3045 *
3046 * Helper; handle receive interrupts.
3047 */
3048 void
3049 atw_rxintr(struct atw_softc *sc)
3050 {
3051 static int rate_tbl[] = {2, 4, 11, 22, 44};
3052 struct ieee80211com *ic = &sc->sc_ic;
3053 struct ieee80211_node *ni;
3054 struct ieee80211_frame_min *wh;
3055 struct ifnet *ifp = &sc->sc_if;
3056 struct atw_rxsoft *rxs;
3057 struct mbuf *m;
3058 u_int32_t rxstat;
3059 int i, len, rate, rate0;
3060 u_int32_t rssi, ctlrssi;
3061
3062 for (i = sc->sc_rxptr;; i = sc->sc_rxptr) {
3063 rxs = &sc->sc_rxsoft[i];
3064
3065 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3066
3067 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat);
3068 ctlrssi = le32toh(sc->sc_rxdescs[i].ar_ctlrssi);
3069 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK);
3070
3071 if (rxstat & ATW_RXSTAT_OWN) {
3072 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
3073 break;
3074 }
3075
3076 sc->sc_rxptr = ATW_NEXTRX(i);
3077
3078 DPRINTF3(sc,
3079 ("%s: rx stat %08x ctlrssi %08x buf1 %08x buf2 %08x\n",
3080 device_xname(sc->sc_dev),
3081 rxstat, ctlrssi,
3082 le32toh(sc->sc_rxdescs[i].ar_buf1),
3083 le32toh(sc->sc_rxdescs[i].ar_buf2)));
3084
3085 /*
3086 * Make sure the packet fits in one buffer. This should
3087 * always be the case.
3088 */
3089 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) !=
3090 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) {
3091 printf("%s: incoming packet spilled, resetting\n",
3092 device_xname(sc->sc_dev));
3093 (void)atw_init(ifp);
3094 return;
3095 }
3096
3097 /*
3098 * If an error occurred, update stats, clear the status
3099 * word, and leave the packet buffer in place. It will
3100 * simply be reused the next time the ring comes around.
3101 */
3102 if ((rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_RXTOE)) != 0) {
3103 #define PRINTERR(bit, str) \
3104 if (rxstat & (bit)) \
3105 aprint_error_dev(sc->sc_dev, "receive error: %s\n", \
3106 str)
3107 ifp->if_ierrors++;
3108 PRINTERR(ATW_RXSTAT_DE, "descriptor error");
3109 PRINTERR(ATW_RXSTAT_RXTOE, "time-out");
3110 #if 0
3111 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error");
3112 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error");
3113 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error");
3114 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error");
3115 #endif
3116 #undef PRINTERR
3117 atw_init_rxdesc(sc, i);
3118 continue;
3119 }
3120
3121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3122 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
3123
3124 /*
3125 * No errors; receive the packet. Note the ADM8211
3126 * includes the CRC in promiscuous mode.
3127 */
3128 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK);
3129
3130 /*
3131 * Allocate a new mbuf cluster. If that fails, we are
3132 * out of memory, and must drop the packet and recycle
3133 * the buffer that's already attached to this descriptor.
3134 */
3135 m = rxs->rxs_mbuf;
3136 if (atw_add_rxbuf(sc, i) != 0) {
3137 ifp->if_ierrors++;
3138 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3139 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3140 atw_init_rxdesc(sc, i);
3141 continue;
3142 }
3143
3144 ifp->if_ipackets++;
3145 m->m_pkthdr.rcvif = ifp;
3146 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len);
3147
3148 rate = (rate0 < __arraycount(rate_tbl)) ? rate_tbl[rate0] : 0;
3149
3150 /* The RSSI comes straight from a register in the
3151 * baseband processor. I know that for the RF3000,
3152 * the RSSI register also contains the antenna-selection
3153 * bits. Mask those off.
3154 *
3155 * TBD Treat other basebands.
3156 * TBD Use short-preamble bit and such in RF3000_RXSTAT.
3157 */
3158 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD)
3159 rssi = ctlrssi & RF3000_RSSI_MASK;
3160 else
3161 rssi = ctlrssi;
3162
3163 #if NBPFILTER > 0
3164 /* Pass this up to any BPF listeners. */
3165 if (sc->sc_radiobpf != NULL) {
3166 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap;
3167
3168 tap->ar_rate = rate;
3169
3170 /* TBD verify units are dB */
3171 tap->ar_antsignal = (int)rssi;
3172 if (sc->sc_opmode & ATW_NAR_PR)
3173 tap->ar_flags = IEEE80211_RADIOTAP_F_FCS;
3174 else
3175 tap->ar_flags = 0;
3176
3177 if ((rxstat & ATW_RXSTAT_CRC32E) != 0)
3178 tap->ar_flags |= IEEE80211_RADIOTAP_F_BADFCS;
3179
3180 bpf_mtap2(sc->sc_radiobpf, tap,
3181 sizeof(sc->sc_rxtapu), m);
3182 }
3183 #endif /* NBPFILTER > 0 */
3184
3185 sc->sc_recv_ev.ev_count++;
3186
3187 if ((rxstat & (ATW_RXSTAT_CRC16E|ATW_RXSTAT_CRC32E|ATW_RXSTAT_ICVE|ATW_RXSTAT_SFDE|ATW_RXSTAT_SIGE)) != 0) {
3188 if (rxstat & ATW_RXSTAT_CRC16E)
3189 sc->sc_crc16e_ev.ev_count++;
3190 if (rxstat & ATW_RXSTAT_CRC32E)
3191 sc->sc_crc32e_ev.ev_count++;
3192 if (rxstat & ATW_RXSTAT_ICVE)
3193 sc->sc_icve_ev.ev_count++;
3194 if (rxstat & ATW_RXSTAT_SFDE)
3195 sc->sc_sfde_ev.ev_count++;
3196 if (rxstat & ATW_RXSTAT_SIGE)
3197 sc->sc_sige_ev.ev_count++;
3198 ifp->if_ierrors++;
3199 m_freem(m);
3200 continue;
3201 }
3202
3203 if (sc->sc_opmode & ATW_NAR_PR)
3204 m_adj(m, -IEEE80211_CRC_LEN);
3205
3206 wh = mtod(m, struct ieee80211_frame_min *);
3207 ni = ieee80211_find_rxnode(ic, wh);
3208 #if 0
3209 if (atw_hw_decrypted(sc, wh)) {
3210 wh->i_fc[1] &= ~IEEE80211_FC1_WEP;
3211 DPRINTF(sc, ("%s: hw decrypted\n", __func__));
3212 }
3213 #endif
3214 ieee80211_input(ic, m, ni, (int)rssi, 0);
3215 ieee80211_free_node(ni);
3216 }
3217 }
3218
3219 /*
3220 * atw_txintr:
3221 *
3222 * Helper; handle transmit interrupts.
3223 */
3224 void
3225 atw_txintr(struct atw_softc *sc, uint32_t status)
3226 {
3227 static char txstat_buf[sizeof("ffffffff<>" ATW_TXSTAT_FMT)];
3228 struct ifnet *ifp = &sc->sc_if;
3229 struct atw_txsoft *txs;
3230 u_int32_t txstat;
3231
3232 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n",
3233 device_xname(sc->sc_dev), sc->sc_flags));
3234
3235 /*
3236 * Go through our Tx list and free mbufs for those
3237 * frames that have been transmitted.
3238 */
3239 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
3240 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1,
3241 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3242
3243 #ifdef ATW_DEBUG
3244 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3245 int i;
3246 printf(" txsoft %p transmit chain:\n", txs);
3247 ATW_CDTXSYNC(sc, txs->txs_firstdesc,
3248 txs->txs_ndescs - 1,
3249 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3250 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) {
3251 printf(" descriptor %d:\n", i);
3252 printf(" at_status: 0x%08x\n",
3253 le32toh(sc->sc_txdescs[i].at_stat));
3254 printf(" at_flags: 0x%08x\n",
3255 le32toh(sc->sc_txdescs[i].at_flags));
3256 printf(" at_buf1: 0x%08x\n",
3257 le32toh(sc->sc_txdescs[i].at_buf1));
3258 printf(" at_buf2: 0x%08x\n",
3259 le32toh(sc->sc_txdescs[i].at_buf2));
3260 if (i == txs->txs_lastdesc)
3261 break;
3262 }
3263 ATW_CDTXSYNC(sc, txs->txs_firstdesc,
3264 txs->txs_ndescs - 1, BUS_DMASYNC_PREREAD);
3265 }
3266 #endif
3267
3268 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat);
3269 if (txstat & ATW_TXSTAT_OWN) {
3270 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1,
3271 BUS_DMASYNC_PREREAD);
3272 break;
3273 }
3274
3275 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
3276
3277 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
3278 0, txs->txs_dmamap->dm_mapsize,
3279 BUS_DMASYNC_POSTWRITE);
3280 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
3281 m_freem(txs->txs_mbuf);
3282 txs->txs_mbuf = NULL;
3283
3284 sc->sc_txfree += txs->txs_ndescs;
3285 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
3286
3287 KASSERT(!SIMPLEQ_EMPTY(&sc->sc_txfreeq) && sc->sc_txfree != 0);
3288 sc->sc_tx_timer = 0;
3289 ifp->if_flags &= ~IFF_OACTIVE;
3290
3291 if ((ifp->if_flags & IFF_DEBUG) != 0 &&
3292 (txstat & ATW_TXSTAT_ERRMASK) != 0) {
3293 snprintb(txstat_buf, sizeof(txstat_buf),
3294 ATW_TXSTAT_FMT, txstat & ATW_TXSTAT_ERRMASK);
3295 printf("%s: txstat %s %" __PRIuBITS "\n",
3296 device_xname(sc->sc_dev), txstat_buf,
3297 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK));
3298 }
3299
3300 sc->sc_xmit_ev.ev_count++;
3301
3302 /*
3303 * Check for errors and collisions.
3304 */
3305 if (txstat & ATW_TXSTAT_TUF)
3306 sc->sc_tuf_ev.ev_count++;
3307 if (txstat & ATW_TXSTAT_TLT)
3308 sc->sc_tlt_ev.ev_count++;
3309 if (txstat & ATW_TXSTAT_TRT)
3310 sc->sc_trt_ev.ev_count++;
3311 if (txstat & ATW_TXSTAT_TRO)
3312 sc->sc_tro_ev.ev_count++;
3313 if (txstat & ATW_TXSTAT_SOFBR)
3314 sc->sc_sofbr_ev.ev_count++;
3315
3316 if ((txstat & ATW_TXSTAT_ES) == 0)
3317 ifp->if_collisions +=
3318 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK);
3319 else
3320 ifp->if_oerrors++;
3321
3322 ifp->if_opackets++;
3323 }
3324
3325 KASSERT(txs != NULL || (ifp->if_flags & IFF_OACTIVE) == 0);
3326 }
3327
3328 /*
3329 * atw_watchdog: [ifnet interface function]
3330 *
3331 * Watchdog timer handler.
3332 */
3333 void
3334 atw_watchdog(struct ifnet *ifp)
3335 {
3336 struct atw_softc *sc = ifp->if_softc;
3337 struct ieee80211com *ic = &sc->sc_ic;
3338
3339 ifp->if_timer = 0;
3340 if (!device_is_active(sc->sc_dev))
3341 return;
3342
3343 if (sc->sc_rescan_timer != 0 && --sc->sc_rescan_timer == 0)
3344 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
3345 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0 &&
3346 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) {
3347 printf("%s: transmit timeout\n", ifp->if_xname);
3348 ifp->if_oerrors++;
3349 (void)atw_init(ifp);
3350 atw_start(ifp);
3351 }
3352 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0)
3353 ifp->if_timer = 1;
3354 ieee80211_watchdog(ic);
3355 }
3356
3357 static void
3358 atw_evcnt_detach(struct atw_softc *sc)
3359 {
3360 evcnt_detach(&sc->sc_sige_ev);
3361 evcnt_detach(&sc->sc_sfde_ev);
3362 evcnt_detach(&sc->sc_icve_ev);
3363 evcnt_detach(&sc->sc_crc32e_ev);
3364 evcnt_detach(&sc->sc_crc16e_ev);
3365 evcnt_detach(&sc->sc_recv_ev);
3366
3367 evcnt_detach(&sc->sc_tuf_ev);
3368 evcnt_detach(&sc->sc_tro_ev);
3369 evcnt_detach(&sc->sc_trt_ev);
3370 evcnt_detach(&sc->sc_tlt_ev);
3371 evcnt_detach(&sc->sc_sofbr_ev);
3372 evcnt_detach(&sc->sc_xmit_ev);
3373
3374 evcnt_detach(&sc->sc_rxpkt1in_ev);
3375 evcnt_detach(&sc->sc_rxamatch_ev);
3376 evcnt_detach(&sc->sc_workaround1_ev);
3377 evcnt_detach(&sc->sc_misc_ev);
3378 }
3379
3380 static void
3381 atw_evcnt_attach(struct atw_softc *sc)
3382 {
3383 evcnt_attach_dynamic(&sc->sc_recv_ev, EVCNT_TYPE_MISC,
3384 NULL, sc->sc_if.if_xname, "recv");
3385 evcnt_attach_dynamic(&sc->sc_crc16e_ev, EVCNT_TYPE_MISC,
3386 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC16 error");
3387 evcnt_attach_dynamic(&sc->sc_crc32e_ev, EVCNT_TYPE_MISC,
3388 &sc->sc_recv_ev, sc->sc_if.if_xname, "CRC32 error");
3389 evcnt_attach_dynamic(&sc->sc_icve_ev, EVCNT_TYPE_MISC,
3390 &sc->sc_recv_ev, sc->sc_if.if_xname, "ICV error");
3391 evcnt_attach_dynamic(&sc->sc_sfde_ev, EVCNT_TYPE_MISC,
3392 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP SFD error");
3393 evcnt_attach_dynamic(&sc->sc_sige_ev, EVCNT_TYPE_MISC,
3394 &sc->sc_recv_ev, sc->sc_if.if_xname, "PLCP Signal Field error");
3395
3396 evcnt_attach_dynamic(&sc->sc_xmit_ev, EVCNT_TYPE_MISC,
3397 NULL, sc->sc_if.if_xname, "xmit");
3398 evcnt_attach_dynamic(&sc->sc_tuf_ev, EVCNT_TYPE_MISC,
3399 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit underflow");
3400 evcnt_attach_dynamic(&sc->sc_tro_ev, EVCNT_TYPE_MISC,
3401 &sc->sc_xmit_ev, sc->sc_if.if_xname, "transmit overrun");
3402 evcnt_attach_dynamic(&sc->sc_trt_ev, EVCNT_TYPE_MISC,
3403 &sc->sc_xmit_ev, sc->sc_if.if_xname, "retry count exceeded");
3404 evcnt_attach_dynamic(&sc->sc_tlt_ev, EVCNT_TYPE_MISC,
3405 &sc->sc_xmit_ev, sc->sc_if.if_xname, "lifetime exceeded");
3406 evcnt_attach_dynamic(&sc->sc_sofbr_ev, EVCNT_TYPE_MISC,
3407 &sc->sc_xmit_ev, sc->sc_if.if_xname, "packet size mismatch");
3408
3409 evcnt_attach_dynamic(&sc->sc_misc_ev, EVCNT_TYPE_MISC,
3410 NULL, sc->sc_if.if_xname, "misc");
3411 evcnt_attach_dynamic(&sc->sc_workaround1_ev, EVCNT_TYPE_MISC,
3412 &sc->sc_misc_ev, sc->sc_if.if_xname, "workaround #1");
3413 evcnt_attach_dynamic(&sc->sc_rxamatch_ev, EVCNT_TYPE_MISC,
3414 &sc->sc_misc_ev, sc->sc_if.if_xname, "rra equals rwa");
3415 evcnt_attach_dynamic(&sc->sc_rxpkt1in_ev, EVCNT_TYPE_MISC,
3416 &sc->sc_misc_ev, sc->sc_if.if_xname, "rxpkt1in set");
3417 }
3418
3419 #ifdef ATW_DEBUG
3420 static void
3421 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0)
3422 {
3423 struct atw_softc *sc = ifp->if_softc;
3424 struct mbuf *m;
3425 int i, noctets = 0;
3426
3427 printf("%s: %d-byte packet\n", device_xname(sc->sc_dev),
3428 m0->m_pkthdr.len);
3429
3430 for (m = m0; m; m = m->m_next) {
3431 if (m->m_len == 0)
3432 continue;
3433 for (i = 0; i < m->m_len; i++) {
3434 printf(" %02x", ((u_int8_t*)m->m_data)[i]);
3435 if (++noctets % 24 == 0)
3436 printf("\n");
3437 }
3438 }
3439 printf("%s%s: %d bytes emitted\n",
3440 (noctets % 24 != 0) ? "\n" : "", device_xname(sc->sc_dev), noctets);
3441 }
3442 #endif /* ATW_DEBUG */
3443
3444 /*
3445 * atw_start: [ifnet interface function]
3446 *
3447 * Start packet transmission on the interface.
3448 */
3449 void
3450 atw_start(struct ifnet *ifp)
3451 {
3452 struct atw_softc *sc = ifp->if_softc;
3453 struct ieee80211_key *k;
3454 struct ieee80211com *ic = &sc->sc_ic;
3455 struct ieee80211_node *ni;
3456 struct ieee80211_frame_min *whm;
3457 struct ieee80211_frame *wh;
3458 struct atw_frame *hh;
3459 uint16_t hdrctl;
3460 struct mbuf *m0, *m;
3461 struct atw_txsoft *txs, *last_txs;
3462 struct atw_txdesc *txd;
3463 int npkt, rate;
3464 bus_dmamap_t dmamap;
3465 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg;
3466
3467 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n",
3468 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags));
3469
3470 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3471 return;
3472
3473 /*
3474 * Remember the previous number of free descriptors and
3475 * the first descriptor we'll use.
3476 */
3477 ofree = sc->sc_txfree;
3478 firsttx = lasttx = sc->sc_txnext;
3479
3480 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n",
3481 device_xname(sc->sc_dev), ofree, firsttx));
3482
3483 /*
3484 * Loop through the send queue, setting up transmit descriptors
3485 * until we drain the queue, or use up all available transmit
3486 * descriptors.
3487 */
3488 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
3489 sc->sc_txfree != 0) {
3490
3491 hdrctl = htole16(ATW_HDRCTL_UNKNOWN1);
3492
3493 /*
3494 * Grab a packet off the management queue, if it
3495 * is not empty. Otherwise, from the data queue.
3496 */
3497 IF_DEQUEUE(&ic->ic_mgtq, m0);
3498 if (m0 != NULL) {
3499 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif;
3500 m0->m_pkthdr.rcvif = NULL;
3501 } else if (ic->ic_state != IEEE80211_S_RUN)
3502 break; /* send no data until associated */
3503 else {
3504 IFQ_DEQUEUE(&ifp->if_snd, m0);
3505 if (m0 == NULL)
3506 break;
3507 #if NBPFILTER > 0
3508 if (ifp->if_bpf != NULL)
3509 bpf_mtap(ifp->if_bpf, m0);
3510 #endif /* NBPFILTER > 0 */
3511 ni = ieee80211_find_txnode(ic,
3512 mtod(m0, struct ether_header *)->ether_dhost);
3513 if (ni == NULL) {
3514 ifp->if_oerrors++;
3515 break;
3516 }
3517 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) {
3518 ieee80211_free_node(ni);
3519 ifp->if_oerrors++;
3520 break;
3521 }
3522 }
3523
3524 rate = MAX(ieee80211_get_rate(ni), 2);
3525
3526 whm = mtod(m0, struct ieee80211_frame_min *);
3527
3528 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0)
3529 k = NULL;
3530 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3531 m_freem(m0);
3532 ieee80211_free_node(ni);
3533 ifp->if_oerrors++;
3534 break;
3535 }
3536 #if 0
3537 if (IEEE80211_IS_MULTICAST(wh->i_addr1) &&
3538 m0->m_pkthdr.len > ic->ic_fragthreshold)
3539 hdrctl |= htole16(ATW_HDRCTL_MORE_FRAG);
3540 #endif
3541
3542 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold)
3543 hdrctl |= htole16(ATW_HDRCTL_RTSCTS);
3544
3545 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len,
3546 ic->ic_flags, ic->ic_fragthreshold, rate,
3547 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) {
3548 DPRINTF2(sc, ("%s: fail compute duration\n", __func__));
3549 m_freem(m0);
3550 break;
3551 }
3552
3553 /* XXX Misleading if fragmentation is enabled. Better
3554 * to fragment in software?
3555 */
3556 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur);
3557
3558 #if NBPFILTER > 0
3559 /*
3560 * Pass the packet to any BPF listeners.
3561 */
3562 if (ic->ic_rawbpf != NULL)
3563 bpf_mtap((void *)ic->ic_rawbpf, m0);
3564
3565 if (sc->sc_radiobpf != NULL) {
3566 struct atw_tx_radiotap_header *tap = &sc->sc_txtap;
3567
3568 tap->at_rate = rate;
3569
3570 bpf_mtap2(sc->sc_radiobpf, tap,
3571 sizeof(sc->sc_txtapu), m0);
3572 }
3573 #endif /* NBPFILTER > 0 */
3574
3575 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT);
3576
3577 if (ni != NULL)
3578 ieee80211_free_node(ni);
3579
3580 if (m0 == NULL) {
3581 ifp->if_oerrors++;
3582 break;
3583 }
3584
3585 /* just to make sure. */
3586 m0 = m_pullup(m0, sizeof(struct atw_frame));
3587
3588 if (m0 == NULL) {
3589 ifp->if_oerrors++;
3590 break;
3591 }
3592
3593 hh = mtod(m0, struct atw_frame *);
3594 wh = &hh->atw_ihdr;
3595
3596 /* Copy everything we need from the 802.11 header:
3597 * Frame Control; address 1, address 3, or addresses
3598 * 3 and 4. NIC fills in BSSID, SA.
3599 */
3600 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) {
3601 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS)
3602 panic("%s: illegal WDS frame",
3603 device_xname(sc->sc_dev));
3604 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN);
3605 } else
3606 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN);
3607
3608 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc;
3609
3610 /* initialize remaining Tx parameters */
3611 memset(&hh->u, 0, sizeof(hh->u));
3612
3613 hh->atw_rate = rate * 5;
3614 /* XXX this could be incorrect if M_FCS. _encap should
3615 * probably strip FCS just in case it sticks around in
3616 * bridged packets.
3617 */
3618 hh->atw_service = 0x00; /* XXX guess */
3619 hh->atw_paylen = htole16(m0->m_pkthdr.len -
3620 sizeof(struct atw_frame));
3621
3622 /* never fragment multicast frames */
3623 if (IEEE80211_IS_MULTICAST(hh->atw_dst))
3624 hh->atw_fragthr = htole16(IEEE80211_FRAG_MAX);
3625 else {
3626 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3627 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE))
3628 hdrctl |= htole16(ATW_HDRCTL_SHORT_PREAMBLE);
3629 hh->atw_fragthr = htole16(ic->ic_fragthreshold);
3630 }
3631
3632 hh->atw_rtylmt = 3;
3633 #if 0
3634 if (do_encrypt) {
3635 hdrctl |= htole16(ATW_HDRCTL_WEP);
3636 hh->atw_keyid = ic->ic_def_txkey;
3637 }
3638 #endif
3639
3640 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len);
3641 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len);
3642 if (txs->txs_d0.d_residue)
3643 hh->atw_head_plcplen |= htole16(0x8000);
3644 if (txs->txs_dn.d_residue)
3645 hh->atw_tail_plcplen |= htole16(0x8000);
3646 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur);
3647 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur);
3648
3649 hh->atw_hdrctl = hdrctl;
3650 hh->atw_fragnum = npkt << 4;
3651 #ifdef ATW_DEBUG
3652
3653 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3654 printf("%s: dst = %s, rate = 0x%02x, "
3655 "service = 0x%02x, paylen = 0x%04x\n",
3656 device_xname(sc->sc_dev), ether_sprintf(hh->atw_dst),
3657 hh->atw_rate, hh->atw_service, hh->atw_paylen);
3658
3659 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, "
3660 "dur1 = 0x%04x, dur2 = 0x%04x, "
3661 "dur3 = 0x%04x, rts_dur = 0x%04x\n",
3662 device_xname(sc->sc_dev), hh->atw_fc[0], hh->atw_fc[1],
3663 hh->atw_tail_plcplen, hh->atw_head_plcplen,
3664 hh->atw_tail_dur, hh->atw_head_dur);
3665
3666 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, "
3667 "fragnum = 0x%02x, rtylmt = 0x%04x\n",
3668 device_xname(sc->sc_dev), hh->atw_hdrctl,
3669 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt);
3670
3671 printf("%s: keyid = %d\n",
3672 device_xname(sc->sc_dev), hh->atw_keyid);
3673
3674 atw_dump_pkt(ifp, m0);
3675 }
3676 #endif /* ATW_DEBUG */
3677
3678 dmamap = txs->txs_dmamap;
3679
3680 /*
3681 * Load the DMA map. Copy and try (once) again if the packet
3682 * didn't fit in the alloted number of segments.
3683 */
3684 for (first = 1;
3685 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
3686 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first;
3687 first = 0) {
3688 MGETHDR(m, M_DONTWAIT, MT_DATA);
3689 if (m == NULL) {
3690 aprint_error_dev(sc->sc_dev, "unable to allocate Tx mbuf\n");
3691 break;
3692 }
3693 if (m0->m_pkthdr.len > MHLEN) {
3694 MCLGET(m, M_DONTWAIT);
3695 if ((m->m_flags & M_EXT) == 0) {
3696 aprint_error_dev(sc->sc_dev, "unable to allocate Tx "
3697 "cluster\n");
3698 m_freem(m);
3699 break;
3700 }
3701 }
3702 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
3703 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
3704 m_freem(m0);
3705 m0 = m;
3706 m = NULL;
3707 }
3708 if (error != 0) {
3709 aprint_error_dev(sc->sc_dev, "unable to load Tx buffer, "
3710 "error = %d\n", error);
3711 m_freem(m0);
3712 break;
3713 }
3714
3715 /*
3716 * Ensure we have enough descriptors free to describe
3717 * the packet.
3718 */
3719 if (dmamap->dm_nsegs > sc->sc_txfree) {
3720 /*
3721 * Not enough free descriptors to transmit
3722 * this packet. Unload the DMA map and
3723 * drop the packet. Notify the upper layer
3724 * that there are no more slots left.
3725 *
3726 * XXX We could allocate an mbuf and copy, but
3727 * XXX it is worth it?
3728 */
3729 bus_dmamap_unload(sc->sc_dmat, dmamap);
3730 m_freem(m0);
3731 break;
3732 }
3733
3734 /*
3735 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
3736 */
3737
3738 /* Sync the DMA map. */
3739 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
3740 BUS_DMASYNC_PREWRITE);
3741
3742 /* XXX arbitrary retry limit; 8 because I have seen it in
3743 * use already and maybe 0 means "no tries" !
3744 */
3745 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK));
3746
3747 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n",
3748 device_xname(sc->sc_dev), rate * 5));
3749 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
3750
3751 /*
3752 * Initialize the transmit descriptors.
3753 */
3754 for (nexttx = sc->sc_txnext, seg = 0;
3755 seg < dmamap->dm_nsegs;
3756 seg++, nexttx = ATW_NEXTTX(nexttx)) {
3757 /*
3758 * If this is the first descriptor we're
3759 * enqueueing, don't set the OWN bit just
3760 * yet. That could cause a race condition.
3761 * We'll do it below.
3762 */
3763 txd = &sc->sc_txdescs[nexttx];
3764 txd->at_ctl = ctl |
3765 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN));
3766
3767 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr);
3768 txd->at_flags =
3769 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len,
3770 ATW_TXFLAG_TBS1_MASK)) |
3771 ((nexttx == (ATW_NTXDESC - 1))
3772 ? htole32(ATW_TXFLAG_TER) : 0);
3773 lasttx = nexttx;
3774 }
3775
3776 /* Set `first segment' and `last segment' appropriately. */
3777 sc->sc_txdescs[sc->sc_txnext].at_flags |=
3778 htole32(ATW_TXFLAG_FS);
3779 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS);
3780
3781 #ifdef ATW_DEBUG
3782 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3783 printf(" txsoft %p transmit chain:\n", txs);
3784 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) {
3785 printf(" descriptor %d:\n", seg);
3786 printf(" at_ctl: 0x%08x\n",
3787 le32toh(sc->sc_txdescs[seg].at_ctl));
3788 printf(" at_flags: 0x%08x\n",
3789 le32toh(sc->sc_txdescs[seg].at_flags));
3790 printf(" at_buf1: 0x%08x\n",
3791 le32toh(sc->sc_txdescs[seg].at_buf1));
3792 printf(" at_buf2: 0x%08x\n",
3793 le32toh(sc->sc_txdescs[seg].at_buf2));
3794 if (seg == lasttx)
3795 break;
3796 }
3797 }
3798 #endif
3799
3800 /* Sync the descriptors we're using. */
3801 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
3802 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3803
3804 /*
3805 * Store a pointer to the packet so we can free it later,
3806 * and remember what txdirty will be once the packet is
3807 * done.
3808 */
3809 txs->txs_mbuf = m0;
3810 txs->txs_firstdesc = sc->sc_txnext;
3811 txs->txs_lastdesc = lasttx;
3812 txs->txs_ndescs = dmamap->dm_nsegs;
3813
3814 /* Advance the tx pointer. */
3815 sc->sc_txfree -= dmamap->dm_nsegs;
3816 sc->sc_txnext = nexttx;
3817
3818 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
3819 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
3820
3821 last_txs = txs;
3822 }
3823
3824 if (sc->sc_txfree != ofree) {
3825 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
3826 device_xname(sc->sc_dev), lasttx, firsttx));
3827 /*
3828 * Cause a transmit interrupt to happen on the
3829 * last packet we enqueued.
3830 */
3831 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC);
3832 ATW_CDTXSYNC(sc, lasttx, 1,
3833 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3834
3835 /*
3836 * The entire packet chain is set up. Give the
3837 * first descriptor to the chip now.
3838 */
3839 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN);
3840 ATW_CDTXSYNC(sc, firsttx, 1,
3841 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3842
3843 /* Wake up the transmitter. */
3844 ATW_WRITE(sc, ATW_TDR, 0x1);
3845
3846 if (txs == NULL || sc->sc_txfree == 0)
3847 ifp->if_flags |= IFF_OACTIVE;
3848
3849 /* Set a watchdog timer in case the chip flakes out. */
3850 sc->sc_tx_timer = 5;
3851 ifp->if_timer = 1;
3852 }
3853 }
3854
3855 /*
3856 * atw_ioctl: [ifnet interface function]
3857 *
3858 * Handle control requests from the operator.
3859 */
3860 int
3861 atw_ioctl(struct ifnet *ifp, u_long cmd, void *data)
3862 {
3863 struct atw_softc *sc = ifp->if_softc;
3864 struct ieee80211req *ireq;
3865 int s, error = 0;
3866
3867 s = splnet();
3868
3869 switch (cmd) {
3870 case SIOCSIFFLAGS:
3871 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
3872 break;
3873 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
3874 case IFF_UP|IFF_RUNNING:
3875 /*
3876 * To avoid rescanning another access point,
3877 * do not call atw_init() here. Instead,
3878 * only reflect media settings.
3879 */
3880 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
3881 atw_filter_setup(sc);
3882 break;
3883 case IFF_UP:
3884 error = atw_init(ifp);
3885 break;
3886 case IFF_RUNNING:
3887 atw_stop(ifp, 1);
3888 break;
3889 case 0:
3890 break;
3891 }
3892 break;
3893 case SIOCADDMULTI:
3894 case SIOCDELMULTI:
3895 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
3896 if (ifp->if_flags & IFF_RUNNING)
3897 atw_filter_setup(sc); /* do not rescan */
3898 error = 0;
3899 }
3900 break;
3901 case SIOCS80211:
3902 ireq = data;
3903 if (ireq->i_type == IEEE80211_IOC_FRAGTHRESHOLD) {
3904 if ((error = kauth_authorize_network(curlwp->l_cred,
3905 KAUTH_NETWORK_INTERFACE,
3906 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, ifp,
3907 (void *)cmd, NULL) != 0))
3908 break;
3909 if (!(IEEE80211_FRAG_MIN <= ireq->i_val &&
3910 ireq->i_val <= IEEE80211_FRAG_MAX))
3911 error = EINVAL;
3912 else
3913 sc->sc_ic.ic_fragthreshold = ireq->i_val;
3914 break;
3915 }
3916 /*FALLTHROUGH*/
3917 default:
3918 error = ieee80211_ioctl(&sc->sc_ic, cmd, data);
3919 if (error == ENETRESET || error == ERESTART) {
3920 if (is_running(ifp))
3921 error = atw_init(ifp);
3922 else
3923 error = 0;
3924 }
3925 break;
3926 }
3927
3928 /* Try to get more packets going. */
3929 if (device_is_active(sc->sc_dev))
3930 atw_start(ifp);
3931
3932 splx(s);
3933 return (error);
3934 }
3935
3936 static int
3937 atw_media_change(struct ifnet *ifp)
3938 {
3939 int error;
3940
3941 error = ieee80211_media_change(ifp);
3942 if (error == ENETRESET) {
3943 if (is_running(ifp))
3944 error = atw_init(ifp);
3945 else
3946 error = 0;
3947 }
3948 return error;
3949 }
NetBSD on the FriendlyARM MINI2440