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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ic / rtw.c
bloba4251d1ebdd2f1dce8d82a0a4787cccebc0966d3
1 /* $NetBSD: rtw.c,v 1.110 2009/10/19 23:19:39 rmind Exp $ */
2 /*-
3 * Copyright (c) 2004, 2005, 2006, 2007 David Young. All rights
4 * reserved.
5 *
6 * Programmed for NetBSD by David Young.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
21 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
28 * OF SUCH DAMAGE.
29 */
30 /*
31 * Device driver for the Realtek RTL8180 802.11 MAC/BBP.
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: rtw.c,v 1.110 2009/10/19 23:19:39 rmind Exp $");
36
37 #include "bpfilter.h"
38
39 #include <sys/param.h>
40 #include <sys/sysctl.h>
41 #include <sys/systm.h>
42 #include <sys/callout.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/time.h>
47 #include <sys/types.h>
48 #include <sys/device.h>
49
50 #include <machine/endian.h>
51 #include <sys/bus.h>
52 #include <sys/intr.h> /* splnet */
53
54 #include <uvm/uvm_extern.h>
55
56 #include <net/if.h>
57 #include <net/if_media.h>
58 #include <net/if_ether.h>
59
60 #include <net80211/ieee80211_netbsd.h>
61 #include <net80211/ieee80211_var.h>
62 #include <net80211/ieee80211_radiotap.h>
63
64 #if NBPFILTER > 0
65 #include <net/bpf.h>
66 #endif
67
68 #include <dev/ic/rtwreg.h>
69 #include <dev/ic/rtwvar.h>
70 #include <dev/ic/rtwphyio.h>
71 #include <dev/ic/rtwphy.h>
72
73 #include <dev/ic/smc93cx6var.h>
74
75 static int rtw_rfprog_fallback = 0;
76 static int rtw_host_rfio = 0;
77
78 #ifdef RTW_DEBUG
79 int rtw_debug = 0;
80 static int rtw_rxbufs_limit = RTW_RXQLEN;
81 #endif /* RTW_DEBUG */
82
83 #define NEXT_ATTACH_STATE(sc, state) do { \
84 DPRINTF(sc, RTW_DEBUG_ATTACH, \
85 ("%s: attach state %s\n", __func__, #state)); \
86 sc->sc_attach_state = state; \
87 } while (0)
88
89 int rtw_dwelltime = 200; /* milliseconds */
90 static struct ieee80211_cipher rtw_cipher_wep;
91
92 static void rtw_disable_interrupts(struct rtw_regs *);
93 static void rtw_enable_interrupts(struct rtw_softc *);
94
95 static int rtw_init(struct ifnet *);
96
97 static void rtw_start(struct ifnet *);
98 static void rtw_reset_oactive(struct rtw_softc *);
99 static struct mbuf *rtw_beacon_alloc(struct rtw_softc *,
100 struct ieee80211_node *);
101 static u_int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *);
102
103 static void rtw_io_enable(struct rtw_softc *, uint8_t, int);
104 static int rtw_key_delete(struct ieee80211com *, const struct ieee80211_key *);
105 static int rtw_key_set(struct ieee80211com *, const struct ieee80211_key *,
106 const u_int8_t[IEEE80211_ADDR_LEN]);
107 static void rtw_key_update_end(struct ieee80211com *);
108 static void rtw_key_update_begin(struct ieee80211com *);
109 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int);
110 static void rtw_wep_setkeys(struct rtw_softc *, struct ieee80211_key *, int);
111
112 static void rtw_led_attach(struct rtw_led_state *, void *);
113 static void rtw_led_detach(struct rtw_led_state *);
114 static void rtw_led_init(struct rtw_regs *);
115 static void rtw_led_slowblink(void *);
116 static void rtw_led_fastblink(void *);
117 static void rtw_led_set(struct rtw_led_state *, struct rtw_regs *, int);
118
119 static int rtw_sysctl_verify_rfio(SYSCTLFN_PROTO);
120 static int rtw_sysctl_verify_rfprog(SYSCTLFN_PROTO);
121 #ifdef RTW_DEBUG
122 static void rtw_dump_rings(struct rtw_softc *sc);
123 static void rtw_print_txdesc(struct rtw_softc *, const char *,
124 struct rtw_txsoft *, struct rtw_txdesc_blk *, int);
125 static int rtw_sysctl_verify_debug(SYSCTLFN_PROTO);
126 static int rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_PROTO);
127 #endif /* RTW_DEBUG */
128 #ifdef RTW_DIAG
129 static void rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln);
130 #endif /* RTW_DIAG */
131
132 /*
133 * Setup sysctl(3) MIB, hw.rtw.*
134 *
135 * TBD condition CTLFLAG_PERMANENT on being a module or not
136 */
137 SYSCTL_SETUP(sysctl_rtw, "sysctl rtw(4) subtree setup")
138 {
139 int rc;
140 const struct sysctlnode *cnode, *rnode;
141
142 if ((rc = sysctl_createv(clog, 0, NULL, &rnode,
143 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL,
144 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0)
145 goto err;
146
147 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode,
148 CTLFLAG_PERMANENT, CTLTYPE_NODE, "rtw",
149 "Realtek RTL818x 802.11 controls",
150 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
151 goto err;
152
153 #ifdef RTW_DEBUG
154 /* control debugging printfs */
155 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
156 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
157 "debug", SYSCTL_DESCR("Enable RTL818x debugging output"),
158 rtw_sysctl_verify_debug, 0, &rtw_debug, 0,
159 CTL_CREATE, CTL_EOL)) != 0)
160 goto err;
161
162 /* Limit rx buffers, for simulating resource exhaustion. */
163 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
164 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
165 "rxbufs_limit",
166 SYSCTL_DESCR("Set rx buffers limit"),
167 rtw_sysctl_verify_rxbufs_limit, 0, &rtw_rxbufs_limit, 0,
168 CTL_CREATE, CTL_EOL)) != 0)
169 goto err;
170
171 #endif /* RTW_DEBUG */
172 /* set fallback RF programming method */
173 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
174 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
175 "rfprog_fallback",
176 SYSCTL_DESCR("Set fallback RF programming method"),
177 rtw_sysctl_verify_rfprog, 0, &rtw_rfprog_fallback, 0,
178 CTL_CREATE, CTL_EOL)) != 0)
179 goto err;
180
181 /* force host to control RF I/O bus */
182 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
183 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
184 "host_rfio", SYSCTL_DESCR("Enable host control of RF I/O"),
185 rtw_sysctl_verify_rfio, 0, &rtw_host_rfio, 0,
186 CTL_CREATE, CTL_EOL)) != 0)
187 goto err;
188
189 return;
190 err:
191 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
192 }
193
194 static int
195 rtw_sysctl_verify(SYSCTLFN_ARGS, int lower, int upper)
196 {
197 int error, t;
198 struct sysctlnode node;
199
200 node = *rnode;
201 t = *(int*)rnode->sysctl_data;
202 node.sysctl_data = &t;
203 error = sysctl_lookup(SYSCTLFN_CALL(&node));
204 if (error || newp == NULL)
205 return (error);
206
207 if (t < lower || t > upper)
208 return (EINVAL);
209
210 *(int*)rnode->sysctl_data = t;
211
212 return (0);
213 }
214
215 static int
216 rtw_sysctl_verify_rfprog(SYSCTLFN_ARGS)
217 {
218 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0,
219 __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK));
220 }
221
222 static int
223 rtw_sysctl_verify_rfio(SYSCTLFN_ARGS)
224 {
225 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)), 0, 1);
226 }
227
228 #ifdef RTW_DEBUG
229 static int
230 rtw_sysctl_verify_debug(SYSCTLFN_ARGS)
231 {
232 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)),
233 0, RTW_DEBUG_MAX);
234 }
235
236 static int
237 rtw_sysctl_verify_rxbufs_limit(SYSCTLFN_ARGS)
238 {
239 return rtw_sysctl_verify(SYSCTLFN_CALL(__UNCONST(rnode)),
240 0, RTW_RXQLEN);
241 }
242
243 static void
244 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
245 {
246 #define PRINTREG32(sc, reg) \
247 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
248 ("%s: reg[ " #reg " / %03x ] = %08x\n", \
249 dvname, reg, RTW_READ(regs, reg)))
250
251 #define PRINTREG16(sc, reg) \
252 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
253 ("%s: reg[ " #reg " / %03x ] = %04x\n", \
254 dvname, reg, RTW_READ16(regs, reg)))
255
256 #define PRINTREG8(sc, reg) \
257 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
258 ("%s: reg[ " #reg " / %03x ] = %02x\n", \
259 dvname, reg, RTW_READ8(regs, reg)))
260
261 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where));
262
263 PRINTREG32(regs, RTW_IDR0);
264 PRINTREG32(regs, RTW_IDR1);
265 PRINTREG32(regs, RTW_MAR0);
266 PRINTREG32(regs, RTW_MAR1);
267 PRINTREG32(regs, RTW_TSFTRL);
268 PRINTREG32(regs, RTW_TSFTRH);
269 PRINTREG32(regs, RTW_TLPDA);
270 PRINTREG32(regs, RTW_TNPDA);
271 PRINTREG32(regs, RTW_THPDA);
272 PRINTREG32(regs, RTW_TCR);
273 PRINTREG32(regs, RTW_RCR);
274 PRINTREG32(regs, RTW_TINT);
275 PRINTREG32(regs, RTW_TBDA);
276 PRINTREG32(regs, RTW_ANAPARM);
277 PRINTREG32(regs, RTW_BB);
278 PRINTREG32(regs, RTW_PHYCFG);
279 PRINTREG32(regs, RTW_WAKEUP0L);
280 PRINTREG32(regs, RTW_WAKEUP0H);
281 PRINTREG32(regs, RTW_WAKEUP1L);
282 PRINTREG32(regs, RTW_WAKEUP1H);
283 PRINTREG32(regs, RTW_WAKEUP2LL);
284 PRINTREG32(regs, RTW_WAKEUP2LH);
285 PRINTREG32(regs, RTW_WAKEUP2HL);
286 PRINTREG32(regs, RTW_WAKEUP2HH);
287 PRINTREG32(regs, RTW_WAKEUP3LL);
288 PRINTREG32(regs, RTW_WAKEUP3LH);
289 PRINTREG32(regs, RTW_WAKEUP3HL);
290 PRINTREG32(regs, RTW_WAKEUP3HH);
291 PRINTREG32(regs, RTW_WAKEUP4LL);
292 PRINTREG32(regs, RTW_WAKEUP4LH);
293 PRINTREG32(regs, RTW_WAKEUP4HL);
294 PRINTREG32(regs, RTW_WAKEUP4HH);
295 PRINTREG32(regs, RTW_DK0);
296 PRINTREG32(regs, RTW_DK1);
297 PRINTREG32(regs, RTW_DK2);
298 PRINTREG32(regs, RTW_DK3);
299 PRINTREG32(regs, RTW_RETRYCTR);
300 PRINTREG32(regs, RTW_RDSAR);
301 PRINTREG32(regs, RTW_FER);
302 PRINTREG32(regs, RTW_FEMR);
303 PRINTREG32(regs, RTW_FPSR);
304 PRINTREG32(regs, RTW_FFER);
305
306 /* 16-bit registers */
307 PRINTREG16(regs, RTW_BRSR);
308 PRINTREG16(regs, RTW_IMR);
309 PRINTREG16(regs, RTW_ISR);
310 PRINTREG16(regs, RTW_BCNITV);
311 PRINTREG16(regs, RTW_ATIMWND);
312 PRINTREG16(regs, RTW_BINTRITV);
313 PRINTREG16(regs, RTW_ATIMTRITV);
314 PRINTREG16(regs, RTW_CRC16ERR);
315 PRINTREG16(regs, RTW_CRC0);
316 PRINTREG16(regs, RTW_CRC1);
317 PRINTREG16(regs, RTW_CRC2);
318 PRINTREG16(regs, RTW_CRC3);
319 PRINTREG16(regs, RTW_CRC4);
320 PRINTREG16(regs, RTW_CWR);
321
322 /* 8-bit registers */
323 PRINTREG8(regs, RTW_CR);
324 PRINTREG8(regs, RTW_9346CR);
325 PRINTREG8(regs, RTW_CONFIG0);
326 PRINTREG8(regs, RTW_CONFIG1);
327 PRINTREG8(regs, RTW_CONFIG2);
328 PRINTREG8(regs, RTW_MSR);
329 PRINTREG8(regs, RTW_CONFIG3);
330 PRINTREG8(regs, RTW_CONFIG4);
331 PRINTREG8(regs, RTW_TESTR);
332 PRINTREG8(regs, RTW_PSR);
333 PRINTREG8(regs, RTW_SCR);
334 PRINTREG8(regs, RTW_PHYDELAY);
335 PRINTREG8(regs, RTW_CRCOUNT);
336 PRINTREG8(regs, RTW_PHYADDR);
337 PRINTREG8(regs, RTW_PHYDATAW);
338 PRINTREG8(regs, RTW_PHYDATAR);
339 PRINTREG8(regs, RTW_CONFIG5);
340 PRINTREG8(regs, RTW_TPPOLL);
341
342 PRINTREG16(regs, RTW_BSSID16);
343 PRINTREG32(regs, RTW_BSSID32);
344 #undef PRINTREG32
345 #undef PRINTREG16
346 #undef PRINTREG8
347 }
348 #endif /* RTW_DEBUG */
349
350 void
351 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
352 {
353 struct rtw_regs *regs = &sc->sc_regs;
354
355 uint32_t tcr;
356 tcr = RTW_READ(regs, RTW_TCR);
357 tcr &= ~RTW_TCR_LBK_MASK;
358 if (enable)
359 tcr |= RTW_TCR_LBK_CONT;
360 else
361 tcr |= RTW_TCR_LBK_NORMAL;
362 RTW_WRITE(regs, RTW_TCR, tcr);
363 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
364 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
365 rtw_txdac_enable(sc, !enable);
366 rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
367 rtw_set_access(regs, RTW_ACCESS_NONE);
368 }
369
370 #ifdef RTW_DEBUG
371 static const char *
372 rtw_access_string(enum rtw_access access)
373 {
374 switch (access) {
375 case RTW_ACCESS_NONE:
376 return "none";
377 case RTW_ACCESS_CONFIG:
378 return "config";
379 case RTW_ACCESS_ANAPARM:
380 return "anaparm";
381 default:
382 return "unknown";
383 }
384 }
385 #endif /* RTW_DEBUG */
386
387 static void
388 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
389 {
390 KASSERT(/* naccess >= RTW_ACCESS_NONE && */
391 naccess <= RTW_ACCESS_ANAPARM);
392 KASSERT(/* regs->r_access >= RTW_ACCESS_NONE && */
393 regs->r_access <= RTW_ACCESS_ANAPARM);
394
395 if (naccess == regs->r_access)
396 return;
397
398 switch (naccess) {
399 case RTW_ACCESS_NONE:
400 switch (regs->r_access) {
401 case RTW_ACCESS_ANAPARM:
402 rtw_anaparm_enable(regs, 0);
403 /*FALLTHROUGH*/
404 case RTW_ACCESS_CONFIG:
405 rtw_config0123_enable(regs, 0);
406 /*FALLTHROUGH*/
407 case RTW_ACCESS_NONE:
408 break;
409 }
410 break;
411 case RTW_ACCESS_CONFIG:
412 switch (regs->r_access) {
413 case RTW_ACCESS_NONE:
414 rtw_config0123_enable(regs, 1);
415 /*FALLTHROUGH*/
416 case RTW_ACCESS_CONFIG:
417 break;
418 case RTW_ACCESS_ANAPARM:
419 rtw_anaparm_enable(regs, 0);
420 break;
421 }
422 break;
423 case RTW_ACCESS_ANAPARM:
424 switch (regs->r_access) {
425 case RTW_ACCESS_NONE:
426 rtw_config0123_enable(regs, 1);
427 /*FALLTHROUGH*/
428 case RTW_ACCESS_CONFIG:
429 rtw_anaparm_enable(regs, 1);
430 /*FALLTHROUGH*/
431 case RTW_ACCESS_ANAPARM:
432 break;
433 }
434 break;
435 }
436 }
437
438 void
439 rtw_set_access(struct rtw_regs *regs, enum rtw_access access)
440 {
441 rtw_set_access1(regs, access);
442 RTW_DPRINTF(RTW_DEBUG_ACCESS,
443 ("%s: access %s -> %s\n", __func__,
444 rtw_access_string(regs->r_access),
445 rtw_access_string(access)));
446 regs->r_access = access;
447 }
448
449 /*
450 * Enable registers, switch register banks.
451 */
452 void
453 rtw_config0123_enable(struct rtw_regs *regs, int enable)
454 {
455 uint8_t ecr;
456 ecr = RTW_READ8(regs, RTW_9346CR);
457 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);
458 if (enable)
459 ecr |= RTW_9346CR_EEM_CONFIG;
460 else {
461 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
462 ecr |= RTW_9346CR_EEM_NORMAL;
463 }
464 RTW_WRITE8(regs, RTW_9346CR, ecr);
465 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
466 }
467
468 /* requires rtw_config0123_enable(, 1) */
469 void
470 rtw_anaparm_enable(struct rtw_regs *regs, int enable)
471 {
472 uint8_t cfg3;
473
474 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
475 cfg3 |= RTW_CONFIG3_CLKRUNEN;
476 if (enable)
477 cfg3 |= RTW_CONFIG3_PARMEN;
478 else
479 cfg3 &= ~RTW_CONFIG3_PARMEN;
480 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
481 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
482 }
483
484 /* requires rtw_anaparm_enable(, 1) */
485 void
486 rtw_txdac_enable(struct rtw_softc *sc, int enable)
487 {
488 uint32_t anaparm;
489 struct rtw_regs *regs = &sc->sc_regs;
490
491 anaparm = RTW_READ(regs, RTW_ANAPARM);
492 if (enable)
493 anaparm &= ~RTW_ANAPARM_TXDACOFF;
494 else
495 anaparm |= RTW_ANAPARM_TXDACOFF;
496 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
497 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
498 }
499
500 static inline int
501 rtw_chip_reset1(struct rtw_regs *regs, device_t dev)
502 {
503 uint8_t cr;
504 int i;
505
506 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
507
508 RTW_WBR(regs, RTW_CR, RTW_CR);
509
510 for (i = 0; i < 1000; i++) {
511 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
512 RTW_DPRINTF(RTW_DEBUG_RESET,
513 ("%s: reset in %dus\n", device_xname(dev), i));
514 return 0;
515 }
516 RTW_RBR(regs, RTW_CR, RTW_CR);
517 DELAY(10); /* 10us */
518 }
519
520 aprint_error_dev(dev, "reset failed\n");
521 return ETIMEDOUT;
522 }
523
524 static inline int
525 rtw_chip_reset(struct rtw_regs *regs, device_t dev)
526 {
527 uint32_t tcr;
528
529 /* from Linux driver */
530 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 |
531 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK);
532
533 RTW_WRITE(regs, RTW_TCR, tcr);
534
535 RTW_WBW(regs, RTW_CR, RTW_TCR);
536
537 return rtw_chip_reset1(regs, dev);
538 }
539
540 static int
541 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen)
542 {
543 struct ieee80211_key keycopy;
544
545 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__));
546
547 keycopy = *k;
548 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT;
549
550 return (*ieee80211_cipher_wep.ic_decap)(&keycopy, m, hdrlen);
551 }
552
553 static int
554 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
555 {
556 struct rtw_softc *sc = ic->ic_ifp->if_softc;
557
558 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__,
559 k->wk_keyix));
560
561 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID);
562
563 if (k->wk_keylen != 0 &&
564 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP)
565 sc->sc_flags &= ~RTW_F_DK_VALID;
566
567 return 1;
568 }
569
570 static int
571 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
572 const u_int8_t mac[IEEE80211_ADDR_LEN])
573 {
574 struct rtw_softc *sc = ic->ic_ifp->if_softc;
575
576 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix));
577
578 KASSERT(k->wk_keyix < IEEE80211_WEP_NKID);
579
580 sc->sc_flags &= ~RTW_F_DK_VALID;
581
582 return 1;
583 }
584
585 static void
586 rtw_key_update_begin(struct ieee80211com *ic)
587 {
588 #ifdef RTW_DEBUG
589 struct ifnet *ifp = ic->ic_ifp;
590 struct rtw_softc *sc = ifp->if_softc;
591 #endif
592
593 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
594 }
595
596 static void
597 rtw_tx_kick(struct rtw_regs *regs, uint8_t ringsel)
598 {
599 uint8_t tppoll;
600
601 tppoll = RTW_READ8(regs, RTW_TPPOLL);
602 tppoll &= ~RTW_TPPOLL_SALL;
603 tppoll |= ringsel & RTW_TPPOLL_ALL;
604 RTW_WRITE8(regs, RTW_TPPOLL, tppoll);
605 RTW_SYNC(regs, RTW_TPPOLL, RTW_TPPOLL);
606 }
607
608 static void
609 rtw_key_update_end(struct ieee80211com *ic)
610 {
611 struct ifnet *ifp = ic->ic_ifp;
612 struct rtw_softc *sc = ifp->if_softc;
613
614 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
615
616 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 ||
617 !device_is_active(sc->sc_dev))
618 return;
619
620 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
621 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey);
622 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE,
623 (ifp->if_flags & IFF_RUNNING) != 0);
624 }
625
626 static bool
627 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k)
628 {
629 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
630 return false;
631
632 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) ||
633 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13);
634 }
635
636 static void
637 rtw_wep_setkeys(struct rtw_softc *sc, struct ieee80211_key *wk, int txkey)
638 {
639 uint8_t psr, scr;
640 int i, keylen = 0;
641 struct rtw_regs *regs;
642 union rtw_keys *rk;
643
644 regs = &sc->sc_regs;
645 rk = &sc->sc_keys;
646
647 (void)memset(rk, 0, sizeof(rk));
648
649 /* Temporarily use software crypto for all keys. */
650 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
651 if (wk[i].wk_cipher == &rtw_cipher_wep)
652 wk[i].wk_cipher = &ieee80211_cipher_wep;
653 }
654
655 rtw_set_access(regs, RTW_ACCESS_CONFIG);
656
657 psr = RTW_READ8(regs, RTW_PSR);
658 scr = RTW_READ8(regs, RTW_SCR);
659 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON);
660
661 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
662 goto out;
663
664 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
665 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i]))
666 continue;
667 if (i == txkey) {
668 keylen = wk[i].wk_keylen;
669 break;
670 }
671 keylen = MAX(keylen, wk[i].wk_keylen);
672 }
673
674 if (keylen == 5)
675 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON;
676 else if (keylen == 13)
677 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON;
678
679 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
680 if (wk[i].wk_keylen != keylen ||
681 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
682 continue;
683 /* h/w will decrypt, s/w still strips headers */
684 wk[i].wk_cipher = &rtw_cipher_wep;
685 (void)memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen);
686 }
687
688 out:
689 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN);
690
691 bus_space_write_region_stream_4(regs->r_bt, regs->r_bh,
692 RTW_DK0, rk->rk_words, __arraycount(rk->rk_words));
693
694 bus_space_barrier(regs->r_bt, regs->r_bh, RTW_DK0, sizeof(rk->rk_words),
695 BUS_SPACE_BARRIER_SYNC);
696
697 RTW_DPRINTF(RTW_DEBUG_KEY,
698 ("%s.%d: scr %02" PRIx8 ", keylen %d\n", __func__, __LINE__, scr,
699 keylen));
700
701 RTW_WBW(regs, RTW_DK0, RTW_PSR);
702 RTW_WRITE8(regs, RTW_PSR, psr);
703 RTW_WBW(regs, RTW_PSR, RTW_SCR);
704 RTW_WRITE8(regs, RTW_SCR, scr);
705 RTW_SYNC(regs, RTW_SCR, RTW_SCR);
706 rtw_set_access(regs, RTW_ACCESS_NONE);
707 sc->sc_flags |= RTW_F_DK_VALID;
708 }
709
710 static inline int
711 rtw_recall_eeprom(struct rtw_regs *regs, device_t dev)
712 {
713 int i;
714 uint8_t ecr;
715
716 ecr = RTW_READ8(regs, RTW_9346CR);
717 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;
718 RTW_WRITE8(regs, RTW_9346CR, ecr);
719
720 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
721
722 /* wait 25ms for completion */
723 for (i = 0; i < 250; i++) {
724 ecr = RTW_READ8(regs, RTW_9346CR);
725 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {
726 RTW_DPRINTF(RTW_DEBUG_RESET,
727 ("%s: recall EEPROM in %dus\n", device_xname(dev),
728 i * 100));
729 return 0;
730 }
731 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
732 DELAY(100);
733 }
734 aprint_error_dev(dev, "recall EEPROM failed\n");
735 return ETIMEDOUT;
736 }
737
738 static inline int
739 rtw_reset(struct rtw_softc *sc)
740 {
741 int rc;
742 uint8_t config1;
743
744 sc->sc_flags &= ~RTW_F_DK_VALID;
745
746 if ((rc = rtw_chip_reset(&sc->sc_regs, sc->sc_dev)) != 0)
747 return rc;
748
749 rc = rtw_recall_eeprom(&sc->sc_regs, sc->sc_dev);
750
751 config1 = RTW_READ8(&sc->sc_regs, RTW_CONFIG1);
752 RTW_WRITE8(&sc->sc_regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN);
753 /* TBD turn off maximum power saving? */
754
755 return 0;
756 }
757
758 static inline int
759 rtw_txdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_txsoft *descs,
760 u_int ndescs)
761 {
762 int i, rc = 0;
763 for (i = 0; i < ndescs; i++) {
764 rc = bus_dmamap_create(dmat, MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES,
765 0, 0, &descs[i].ts_dmamap);
766 if (rc != 0)
767 break;
768 }
769 return rc;
770 }
771
772 static inline int
773 rtw_rxdesc_dmamaps_create(bus_dma_tag_t dmat, struct rtw_rxsoft *descs,
774 u_int ndescs)
775 {
776 int i, rc = 0;
777 for (i = 0; i < ndescs; i++) {
778 rc = bus_dmamap_create(dmat, MCLBYTES, 1, MCLBYTES, 0, 0,
779 &descs[i].rs_dmamap);
780 if (rc != 0)
781 break;
782 }
783 return rc;
784 }
785
786 static inline void
787 rtw_rxdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_rxsoft *descs,
788 u_int ndescs)
789 {
790 int i;
791 for (i = 0; i < ndescs; i++) {
792 if (descs[i].rs_dmamap != NULL)
793 bus_dmamap_destroy(dmat, descs[i].rs_dmamap);
794 }
795 }
796
797 static inline void
798 rtw_txdesc_dmamaps_destroy(bus_dma_tag_t dmat, struct rtw_txsoft *descs,
799 u_int ndescs)
800 {
801 int i;
802 for (i = 0; i < ndescs; i++) {
803 if (descs[i].ts_dmamap != NULL)
804 bus_dmamap_destroy(dmat, descs[i].ts_dmamap);
805 }
806 }
807
808 static inline void
809 rtw_srom_free(struct rtw_srom *sr)
810 {
811 sr->sr_size = 0;
812 if (sr->sr_content == NULL)
813 return;
814 free(sr->sr_content, M_DEVBUF);
815 sr->sr_content = NULL;
816 }
817
818 static void
819 rtw_srom_defaults(struct rtw_srom *sr, uint32_t *flags,
820 uint8_t *cs_threshold, enum rtw_rfchipid *rfchipid, uint32_t *rcr)
821 {
822 *flags |= (RTW_F_DIGPHY|RTW_F_ANTDIV);
823 *cs_threshold = RTW_SR_ENERGYDETTHR_DEFAULT;
824 *rcr |= RTW_RCR_ENCS1;
825 *rfchipid = RTW_RFCHIPID_PHILIPS;
826 }
827
828 static int
829 rtw_srom_parse(struct rtw_srom *sr, uint32_t *flags, uint8_t *cs_threshold,
830 enum rtw_rfchipid *rfchipid, uint32_t *rcr, enum rtw_locale *locale,
831 device_t dev)
832 {
833 int i;
834 const char *rfname, *paname;
835 char scratch[sizeof("unknown 0xXX")];
836 uint16_t srom_version;
837 uint8_t mac[IEEE80211_ADDR_LEN];
838
839 *flags &= ~(RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV);
840 *rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
841
842 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION);
843
844 if (srom_version <= 0x0101) {
845 aprint_error_dev(dev,
846 "SROM version %d.%d is not understood, "
847 "limping along with defaults\n",
848 srom_version >> 8, srom_version & 0xff);
849 rtw_srom_defaults(sr, flags, cs_threshold, rfchipid, rcr);
850 return 0;
851 } else {
852 aprint_verbose_dev(dev, "SROM version %d.%d",
853 srom_version >> 8, srom_version & 0xff);
854 }
855
856 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
857 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);
858
859 RTW_DPRINTF(RTW_DEBUG_ATTACH,
860 ("%s: EEPROM MAC %s\n", device_xname(dev), ether_sprintf(mac)));
861
862 *cs_threshold = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);
863
864 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)
865 *flags |= RTW_F_ANTDIV;
866
867 /* Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems
868 * to be reversed.
869 */
870 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)
871 *flags |= RTW_F_DIGPHY;
872 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)
873 *flags |= RTW_F_DFLANTB;
874
875 *rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
876 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);
877
878 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0)
879 *flags |= RTW_C_RXWEP_104;
880
881 *flags |= RTW_C_RXWEP_40; /* XXX */
882
883 *rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);
884 switch (*rfchipid) {
885 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */
886 rfname = "GCT GRF5101";
887 paname = "Winspring WS9901";
888 break;
889 case RTW_RFCHIPID_MAXIM:
890 rfname = "Maxim MAX2820"; /* guess */
891 paname = "Maxim MAX2422"; /* guess */
892 break;
893 case RTW_RFCHIPID_INTERSIL:
894 rfname = "Intersil HFA3873"; /* guess */
895 paname = "Intersil <unknown>";
896 break;
897 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */
898 rfname = "Philips SA2400A";
899 paname = "Philips SA2411";
900 break;
901 case RTW_RFCHIPID_RFMD:
902 /* this is the same front-end as an atw(4)! */
903 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */
904 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */
905 "SYN: Silicon Labs Si4126"; /* inferred from
906 * reference driver
907 */
908 paname = "RFMD RF2189"; /* mentioned in Realtek docs */
909 break;
910 case RTW_RFCHIPID_RESERVED:
911 rfname = paname = "reserved";
912 break;
913 default:
914 snprintf(scratch, sizeof(scratch), "unknown 0x%02x", *rfchipid);
915 rfname = paname = scratch;
916 }
917 aprint_normal_dev(dev, "RF: %s, PA: %s\n", rfname, paname);
918
919 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {
920 case RTW_CONFIG0_GL_USA:
921 case _RTW_CONFIG0_GL_USA:
922 *locale = RTW_LOCALE_USA;
923 break;
924 case RTW_CONFIG0_GL_EUROPE:
925 *locale = RTW_LOCALE_EUROPE;
926 break;
927 case RTW_CONFIG0_GL_JAPAN:
928 *locale = RTW_LOCALE_JAPAN;
929 break;
930 default:
931 *locale = RTW_LOCALE_UNKNOWN;
932 break;
933 }
934 return 0;
935 }
936
937 /* Returns -1 on failure. */
938 static int
939 rtw_srom_read(struct rtw_regs *regs, uint32_t flags, struct rtw_srom *sr,
940 device_t dev)
941 {
942 int rc;
943 struct seeprom_descriptor sd;
944 uint8_t ecr;
945
946 (void)memset(&sd, 0, sizeof(sd));
947
948 ecr = RTW_READ8(regs, RTW_9346CR);
949
950 if ((flags & RTW_F_9356SROM) != 0) {
951 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c56 SROM\n",
952 device_xname(dev)));
953 sr->sr_size = 256;
954 sd.sd_chip = C56_66;
955 } else {
956 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("%s: 93c46 SROM\n",
957 device_xname(dev)));
958 sr->sr_size = 128;
959 sd.sd_chip = C46;
960 }
961
962 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
963 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
964 ecr |= RTW_9346CR_EEM_PROGRAM;
965
966 RTW_WRITE8(regs, RTW_9346CR, ecr);
967
968 sr->sr_content = malloc(sr->sr_size, M_DEVBUF, M_NOWAIT);
969
970 if (sr->sr_content == NULL) {
971 aprint_error_dev(dev, "unable to allocate SROM buffer\n");
972 return ENOMEM;
973 }
974
975 (void)memset(sr->sr_content, 0, sr->sr_size);
976
977 /* RTL8180 has a single 8-bit register for controlling the
978 * 93cx6 SROM. There is no "ready" bit. The RTL8180
979 * input/output sense is the reverse of read_seeprom's.
980 */
981 sd.sd_tag = regs->r_bt;
982 sd.sd_bsh = regs->r_bh;
983 sd.sd_regsize = 1;
984 sd.sd_control_offset = RTW_9346CR;
985 sd.sd_status_offset = RTW_9346CR;
986 sd.sd_dataout_offset = RTW_9346CR;
987 sd.sd_CK = RTW_9346CR_EESK;
988 sd.sd_CS = RTW_9346CR_EECS;
989 sd.sd_DI = RTW_9346CR_EEDO;
990 sd.sd_DO = RTW_9346CR_EEDI;
991 /* make read_seeprom enter EEPROM read/write mode */
992 sd.sd_MS = ecr;
993 sd.sd_RDY = 0;
994
995 /* TBD bus barriers */
996 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size/2)) {
997 aprint_error_dev(dev, "could not read SROM\n");
998 free(sr->sr_content, M_DEVBUF);
999 sr->sr_content = NULL;
1000 return -1; /* XXX */
1001 }
1002
1003 /* end EEPROM read/write mode */
1004 RTW_WRITE8(regs, RTW_9346CR,
1005 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);
1006 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
1007
1008 if ((rc = rtw_recall_eeprom(regs, dev)) != 0)
1009 return rc;
1010
1011 #ifdef RTW_DEBUG
1012 {
1013 int i;
1014 RTW_DPRINTF(RTW_DEBUG_ATTACH,
1015 ("\n%s: serial ROM:\n\t", device_xname(dev)));
1016 for (i = 0; i < sr->sr_size/2; i++) {
1017 if (((i % 8) == 0) && (i != 0))
1018 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t"));
1019 RTW_DPRINTF(RTW_DEBUG_ATTACH,
1020 (" %04x", sr->sr_content[i]));
1021 }
1022 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n"));
1023 }
1024 #endif /* RTW_DEBUG */
1025 return 0;
1026 }
1027
1028 static void
1029 rtw_set_rfprog(struct rtw_regs *regs, enum rtw_rfchipid rfchipid,
1030 device_t dev)
1031 {
1032 uint8_t cfg4;
1033 const char *method;
1034
1035 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
1036
1037 switch (rfchipid) {
1038 default:
1039 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
1040 method = "fallback";
1041 break;
1042 case RTW_RFCHIPID_INTERSIL:
1043 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;
1044 method = "Intersil";
1045 break;
1046 case RTW_RFCHIPID_PHILIPS:
1047 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;
1048 method = "Philips";
1049 break;
1050 case RTW_RFCHIPID_GCT: /* XXX a guess */
1051 case RTW_RFCHIPID_RFMD:
1052 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;
1053 method = "RFMD";
1054 break;
1055 }
1056
1057 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
1058
1059 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
1060
1061 RTW_DPRINTF(RTW_DEBUG_INIT,
1062 ("%s: %s RF programming method, %#02x\n", device_xname(dev), method,
1063 RTW_READ8(regs, RTW_CONFIG4)));
1064 }
1065
1066 static inline void
1067 rtw_init_channels(enum rtw_locale locale,
1068 struct ieee80211_channel (*chans)[IEEE80211_CHAN_MAX+1], device_t dev)
1069 {
1070 int i;
1071 const char *name = NULL;
1072 #define ADD_CHANNEL(_chans, _chan) do { \
1073 (*_chans)[_chan].ic_flags = IEEE80211_CHAN_B; \
1074 (*_chans)[_chan].ic_freq = \
1075 ieee80211_ieee2mhz(_chan, (*_chans)[_chan].ic_flags);\
1076 } while (0)
1077
1078 switch (locale) {
1079 case RTW_LOCALE_USA: /* 1-11 */
1080 name = "USA";
1081 for (i = 1; i <= 11; i++)
1082 ADD_CHANNEL(chans, i);
1083 break;
1084 case RTW_LOCALE_JAPAN: /* 1-14 */
1085 name = "Japan";
1086 ADD_CHANNEL(chans, 14);
1087 for (i = 1; i <= 14; i++)
1088 ADD_CHANNEL(chans, i);
1089 break;
1090 case RTW_LOCALE_EUROPE: /* 1-13 */
1091 name = "Europe";
1092 for (i = 1; i <= 13; i++)
1093 ADD_CHANNEL(chans, i);
1094 break;
1095 default: /* 10-11 allowed by most countries */
1096 name = "<unknown>";
1097 for (i = 10; i <= 11; i++)
1098 ADD_CHANNEL(chans, i);
1099 break;
1100 }
1101 aprint_normal_dev(dev, "Geographic Location %s\n", name);
1102 #undef ADD_CHANNEL
1103 }
1104
1105
1106 static inline void
1107 rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale)
1108 {
1109 uint8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0);
1110
1111 switch (cfg0 & RTW_CONFIG0_GL_MASK) {
1112 case RTW_CONFIG0_GL_USA:
1113 case _RTW_CONFIG0_GL_USA:
1114 *locale = RTW_LOCALE_USA;
1115 break;
1116 case RTW_CONFIG0_GL_JAPAN:
1117 *locale = RTW_LOCALE_JAPAN;
1118 break;
1119 case RTW_CONFIG0_GL_EUROPE:
1120 *locale = RTW_LOCALE_EUROPE;
1121 break;
1122 default:
1123 *locale = RTW_LOCALE_UNKNOWN;
1124 break;
1125 }
1126 }
1127
1128 static inline int
1129 rtw_identify_sta(struct rtw_regs *regs, uint8_t (*addr)[IEEE80211_ADDR_LEN],
1130 device_t dev)
1131 {
1132 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
1133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1134 };
1135 uint32_t idr0 = RTW_READ(regs, RTW_IDR0),
1136 idr1 = RTW_READ(regs, RTW_IDR1);
1137
1138 (*addr)[0] = __SHIFTOUT(idr0, __BITS(0, 7));
1139 (*addr)[1] = __SHIFTOUT(idr0, __BITS(8, 15));
1140 (*addr)[2] = __SHIFTOUT(idr0, __BITS(16, 23));
1141 (*addr)[3] = __SHIFTOUT(idr0, __BITS(24 ,31));
1142
1143 (*addr)[4] = __SHIFTOUT(idr1, __BITS(0, 7));
1144 (*addr)[5] = __SHIFTOUT(idr1, __BITS(8, 15));
1145
1146 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) {
1147 aprint_error_dev(dev,
1148 "could not get mac address, attach failed\n");
1149 return ENXIO;
1150 }
1151
1152 aprint_normal_dev(dev, "802.11 address %s\n", ether_sprintf(*addr));
1153
1154 return 0;
1155 }
1156
1157 static uint8_t
1158 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,
1159 struct ieee80211_channel *chan)
1160 {
1161 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;
1162 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14);
1163 return RTW_SR_GET(sr, idx);
1164 }
1165
1166 static void
1167 rtw_txdesc_blk_init_all(struct rtw_txdesc_blk *tdb)
1168 {
1169 int pri;
1170 /* nfree: the number of free descriptors in each ring.
1171 * The beacon ring is a special case: I do not let the
1172 * driver use all of the descriptors on the beacon ring.
1173 * The reasons are two-fold:
1174 *
1175 * (1) A BEACON descriptor's OWN bit is (apparently) not
1176 * updated, so the driver cannot easily know if the descriptor
1177 * belongs to it, or if it is racing the NIC. If the NIC
1178 * does not OWN every descriptor, then the driver can safely
1179 * update the descriptors when RTW_TBDA points at tdb_next.
1180 *
1181 * (2) I hope that the NIC will process more than one BEACON
1182 * descriptor in a single beacon interval, since that will
1183 * enable multiple-BSS support. Since the NIC does not
1184 * clear the OWN bit, there is no natural place for it to
1185 * stop processing BEACON desciptors. Maybe it will *not*
1186 * stop processing them! I do not want to chance the NIC
1187 * looping around and around a saturated beacon ring, so
1188 * I will leave one descriptor unOWNed at all times.
1189 */
1190 u_int nfree[RTW_NTXPRI] =
1191 {RTW_NTXDESCLO, RTW_NTXDESCMD, RTW_NTXDESCHI,
1192 RTW_NTXDESCBCN - 1};
1193
1194 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1195 tdb[pri].tdb_nfree = nfree[pri];
1196 tdb[pri].tdb_next = 0;
1197 }
1198 }
1199
1200 static int
1201 rtw_txsoft_blk_init(struct rtw_txsoft_blk *tsb)
1202 {
1203 int i;
1204 struct rtw_txsoft *ts;
1205
1206 SIMPLEQ_INIT(&tsb->tsb_dirtyq);
1207 SIMPLEQ_INIT(&tsb->tsb_freeq);
1208 for (i = 0; i < tsb->tsb_ndesc; i++) {
1209 ts = &tsb->tsb_desc[i];
1210 ts->ts_mbuf = NULL;
1211 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1212 }
1213 tsb->tsb_tx_timer = 0;
1214 return 0;
1215 }
1216
1217 static void
1218 rtw_txsoft_blk_init_all(struct rtw_txsoft_blk *tsb)
1219 {
1220 int pri;
1221 for (pri = 0; pri < RTW_NTXPRI; pri++)
1222 rtw_txsoft_blk_init(&tsb[pri]);
1223 }
1224
1225 static inline void
1226 rtw_rxdescs_sync(struct rtw_rxdesc_blk *rdb, int desc0, int nsync, int ops)
1227 {
1228 KASSERT(nsync <= rdb->rdb_ndesc);
1229 /* sync to end of ring */
1230 if (desc0 + nsync > rdb->rdb_ndesc) {
1231 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1232 offsetof(struct rtw_descs, hd_rx[desc0]),
1233 sizeof(struct rtw_rxdesc) * (rdb->rdb_ndesc - desc0), ops);
1234 nsync -= (rdb->rdb_ndesc - desc0);
1235 desc0 = 0;
1236 }
1237
1238 KASSERT(desc0 < rdb->rdb_ndesc);
1239 KASSERT(nsync <= rdb->rdb_ndesc);
1240 KASSERT(desc0 + nsync <= rdb->rdb_ndesc);
1241
1242 /* sync what remains */
1243 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1244 offsetof(struct rtw_descs, hd_rx[desc0]),
1245 sizeof(struct rtw_rxdesc) * nsync, ops);
1246 }
1247
1248 static void
1249 rtw_txdescs_sync(struct rtw_txdesc_blk *tdb, u_int desc0, u_int nsync, int ops)
1250 {
1251 /* sync to end of ring */
1252 if (desc0 + nsync > tdb->tdb_ndesc) {
1253 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1254 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0,
1255 sizeof(struct rtw_txdesc) * (tdb->tdb_ndesc - desc0),
1256 ops);
1257 nsync -= (tdb->tdb_ndesc - desc0);
1258 desc0 = 0;
1259 }
1260
1261 /* sync what remains */
1262 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1263 tdb->tdb_ofs + sizeof(struct rtw_txdesc) * desc0,
1264 sizeof(struct rtw_txdesc) * nsync, ops);
1265 }
1266
1267 static void
1268 rtw_txdescs_sync_all(struct rtw_txdesc_blk *tdb)
1269 {
1270 int pri;
1271 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1272 rtw_txdescs_sync(&tdb[pri], 0, tdb[pri].tdb_ndesc,
1273 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1274 }
1275 }
1276
1277 static void
1278 rtw_rxbufs_release(bus_dma_tag_t dmat, struct rtw_rxsoft *desc)
1279 {
1280 int i;
1281 struct rtw_rxsoft *rs;
1282
1283 for (i = 0; i < RTW_RXQLEN; i++) {
1284 rs = &desc[i];
1285 if (rs->rs_mbuf == NULL)
1286 continue;
1287 bus_dmamap_sync(dmat, rs->rs_dmamap, 0,
1288 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1289 bus_dmamap_unload(dmat, rs->rs_dmamap);
1290 m_freem(rs->rs_mbuf);
1291 rs->rs_mbuf = NULL;
1292 }
1293 }
1294
1295 static inline int
1296 rtw_rxsoft_alloc(bus_dma_tag_t dmat, struct rtw_rxsoft *rs)
1297 {
1298 int rc;
1299 struct mbuf *m;
1300
1301 MGETHDR(m, M_DONTWAIT, MT_DATA);
1302 if (m == NULL)
1303 return ENOBUFS;
1304
1305 MCLGET(m, M_DONTWAIT);
1306 if ((m->m_flags & M_EXT) == 0) {
1307 m_freem(m);
1308 return ENOBUFS;
1309 }
1310
1311 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
1312
1313 if (rs->rs_mbuf != NULL)
1314 bus_dmamap_unload(dmat, rs->rs_dmamap);
1315
1316 rs->rs_mbuf = NULL;
1317
1318 rc = bus_dmamap_load_mbuf(dmat, rs->rs_dmamap, m, BUS_DMA_NOWAIT);
1319 if (rc != 0) {
1320 m_freem(m);
1321 return -1;
1322 }
1323
1324 rs->rs_mbuf = m;
1325
1326 return 0;
1327 }
1328
1329 static int
1330 rtw_rxsoft_init_all(bus_dma_tag_t dmat, struct rtw_rxsoft *desc,
1331 int *ndesc, device_t dev)
1332 {
1333 int i, rc = 0;
1334 struct rtw_rxsoft *rs;
1335
1336 for (i = 0; i < RTW_RXQLEN; i++) {
1337 rs = &desc[i];
1338 /* we're in rtw_init, so there should be no mbufs allocated */
1339 KASSERT(rs->rs_mbuf == NULL);
1340 #ifdef RTW_DEBUG
1341 if (i == rtw_rxbufs_limit) {
1342 aprint_error_dev(dev, "TEST hit %d-buffer limit\n", i);
1343 rc = ENOBUFS;
1344 break;
1345 }
1346 #endif /* RTW_DEBUG */
1347 if ((rc = rtw_rxsoft_alloc(dmat, rs)) != 0) {
1348 aprint_error_dev(dev,
1349 "rtw_rxsoft_alloc failed, %d buffers, rc %d\n",
1350 i, rc);
1351 break;
1352 }
1353 }
1354 *ndesc = i;
1355 return rc;
1356 }
1357
1358 static inline void
1359 rtw_rxdesc_init(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *rs,
1360 int idx, int kick)
1361 {
1362 int is_last = (idx == rdb->rdb_ndesc - 1);
1363 uint32_t ctl, octl, obuf;
1364 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx];
1365
1366 /* sync the mbuf before the descriptor */
1367 bus_dmamap_sync(rdb->rdb_dmat, rs->rs_dmamap, 0,
1368 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1369
1370 obuf = rd->rd_buf;
1371 rd->rd_buf = htole32(rs->rs_dmamap->dm_segs[0].ds_addr);
1372
1373 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
1374 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS;
1375
1376 if (is_last)
1377 ctl |= RTW_RXCTL_EOR;
1378
1379 octl = rd->rd_ctl;
1380 rd->rd_ctl = htole32(ctl);
1381
1382 RTW_DPRINTF(
1383 kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK)
1384 : RTW_DEBUG_RECV_DESC,
1385 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n", __func__, rd,
1386 le32toh(obuf), le32toh(rd->rd_buf), le32toh(octl),
1387 le32toh(rd->rd_ctl)));
1388
1389 /* sync the descriptor */
1390 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1391 RTW_DESC_OFFSET(hd_rx, idx), sizeof(struct rtw_rxdesc),
1392 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1393 }
1394
1395 static void
1396 rtw_rxdesc_init_all(struct rtw_rxdesc_blk *rdb, struct rtw_rxsoft *ctl, int kick)
1397 {
1398 int i;
1399 struct rtw_rxdesc *rd;
1400 struct rtw_rxsoft *rs;
1401
1402 for (i = 0; i < rdb->rdb_ndesc; i++) {
1403 rd = &rdb->rdb_desc[i];
1404 rs = &ctl[i];
1405 rtw_rxdesc_init(rdb, rs, i, kick);
1406 }
1407 }
1408
1409 static void
1410 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable)
1411 {
1412 struct rtw_regs *regs = &sc->sc_regs;
1413 uint8_t cr;
1414
1415 RTW_DPRINTF(RTW_DEBUG_IOSTATE, ("%s: %s 0x%02x\n", __func__,
1416 enable ? "enable" : "disable", flags));
1417
1418 cr = RTW_READ8(regs, RTW_CR);
1419
1420 /* XXX reference source does not enable MULRW */
1421 /* enable PCI Read/Write Multiple */
1422 cr |= RTW_CR_MULRW;
1423
1424 /* The receive engine will always start at RDSAR. */
1425 if (enable && (flags & ~cr & RTW_CR_RE)) {
1426 struct rtw_rxdesc_blk *rdb;
1427 rdb = &sc->sc_rxdesc_blk;
1428 rdb->rdb_next = 0;
1429 }
1430
1431 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
1432 if (enable)
1433 cr |= flags;
1434 else
1435 cr &= ~flags;
1436 RTW_WRITE8(regs, RTW_CR, cr);
1437 RTW_SYNC(regs, RTW_CR, RTW_CR);
1438
1439 #ifdef RTW_DIAG
1440 if (cr & RTW_CR_TE)
1441 rtw_txring_fixup(sc, __func__, __LINE__);
1442 #endif
1443 if (cr & RTW_CR_TE) {
1444 rtw_tx_kick(&sc->sc_regs,
1445 RTW_TPPOLL_HPQ | RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ);
1446 }
1447 }
1448
1449 static void
1450 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr)
1451 {
1452 #define IS_BEACON(__fc0) \
1453 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\
1454 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON))
1455
1456 static const int ratetbl[4] = {2, 4, 11, 22}; /* convert rates:
1457 * hardware -> net80211
1458 */
1459 u_int next, nproc = 0;
1460 int hwrate, len, rate, rssi, sq;
1461 uint32_t hrssi, hstat, htsfth, htsftl;
1462 struct rtw_rxdesc *rd;
1463 struct rtw_rxsoft *rs;
1464 struct rtw_rxdesc_blk *rdb;
1465 struct mbuf *m;
1466 struct ifnet *ifp = &sc->sc_if;
1467
1468 struct ieee80211_node *ni;
1469 struct ieee80211_frame_min *wh;
1470
1471 rdb = &sc->sc_rxdesc_blk;
1472
1473 for (next = rdb->rdb_next; ; next = rdb->rdb_next) {
1474 KASSERT(next < rdb->rdb_ndesc);
1475
1476 rtw_rxdescs_sync(rdb, next, 1,
1477 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1478 rd = &rdb->rdb_desc[next];
1479 rs = &sc->sc_rxsoft[next];
1480
1481 hstat = le32toh(rd->rd_stat);
1482 hrssi = le32toh(rd->rd_rssi);
1483 htsfth = le32toh(rd->rd_tsfth);
1484 htsftl = le32toh(rd->rd_tsftl);
1485
1486 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1487 ("%s: rxdesc[%d] hstat %08x hrssi %08x htsft %08x%08x\n",
1488 __func__, next, hstat, hrssi, htsfth, htsftl));
1489
1490 ++nproc;
1491
1492 /* still belongs to NIC */
1493 if ((hstat & RTW_RXSTAT_OWN) != 0) {
1494 rtw_rxdescs_sync(rdb, next, 1, BUS_DMASYNC_PREREAD);
1495 break;
1496 }
1497
1498 /* ieee80211_input() might reset the receive engine
1499 * (e.g. by indirectly calling rtw_tune()), so save
1500 * the next pointer here and retrieve it again on
1501 * the next round.
1502 */
1503 rdb->rdb_next = (next + 1) % rdb->rdb_ndesc;
1504
1505 #ifdef RTW_DEBUG
1506 #define PRINTSTAT(flag) do { \
1507 if ((hstat & flag) != 0) { \
1508 printf("%s" #flag, delim); \
1509 delim = ","; \
1510 } \
1511 } while (0)
1512 if ((rtw_debug & RTW_DEBUG_RECV_DESC) != 0) {
1513 const char *delim = "<";
1514 printf("%s: ", device_xname(sc->sc_dev));
1515 if ((hstat & RTW_RXSTAT_DEBUG) != 0) {
1516 printf("status %08x", hstat);
1517 PRINTSTAT(RTW_RXSTAT_SPLCP);
1518 PRINTSTAT(RTW_RXSTAT_MAR);
1519 PRINTSTAT(RTW_RXSTAT_PAR);
1520 PRINTSTAT(RTW_RXSTAT_BAR);
1521 PRINTSTAT(RTW_RXSTAT_PWRMGT);
1522 PRINTSTAT(RTW_RXSTAT_CRC32);
1523 PRINTSTAT(RTW_RXSTAT_ICV);
1524 printf(">, ");
1525 }
1526 }
1527 #endif /* RTW_DEBUG */
1528
1529 if ((hstat & RTW_RXSTAT_IOERROR) != 0) {
1530 aprint_error_dev(sc->sc_dev,
1531 "DMA error/FIFO overflow %08" PRIx32 ", "
1532 "rx descriptor %d\n", hstat, next);
1533 ifp->if_ierrors++;
1534 goto next;
1535 }
1536
1537 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);
1538 if (len < IEEE80211_MIN_LEN) {
1539 sc->sc_ic.ic_stats.is_rx_tooshort++;
1540 goto next;
1541 }
1542 if (len > rs->rs_mbuf->m_len) {
1543 aprint_error_dev(sc->sc_dev,
1544 "rx frame too long, %d > %d, %08" PRIx32
1545 ", desc %d\n",
1546 len, rs->rs_mbuf->m_len, hstat, next);
1547 ifp->if_ierrors++;
1548 goto next;
1549 }
1550
1551 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);
1552 if (hwrate >= __arraycount(ratetbl)) {
1553 aprint_error_dev(sc->sc_dev,
1554 "unknown rate #%" __PRIuBITS "\n",
1555 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));
1556 ifp->if_ierrors++;
1557 goto next;
1558 }
1559 rate = ratetbl[hwrate];
1560
1561 #ifdef RTW_DEBUG
1562 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1563 ("rate %d.%d Mb/s, time %08x%08x\n", (rate * 5) / 10,
1564 (rate * 5) % 10, htsfth, htsftl));
1565 #endif /* RTW_DEBUG */
1566
1567 /* if bad flags, skip descriptor */
1568 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) {
1569 aprint_error_dev(sc->sc_dev, "too many rx segments, "
1570 "next=%d, %08" PRIx32 "\n", next, hstat);
1571 goto next;
1572 }
1573
1574 bus_dmamap_sync(sc->sc_dmat, rs->rs_dmamap, 0,
1575 rs->rs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1576
1577 m = rs->rs_mbuf;
1578
1579 /* if temporarily out of memory, re-use mbuf */
1580 switch (rtw_rxsoft_alloc(sc->sc_dmat, rs)) {
1581 case 0:
1582 break;
1583 case ENOBUFS:
1584 aprint_error_dev(sc->sc_dev,
1585 "rtw_rxsoft_alloc(, %d) failed, dropping packet\n",
1586 next);
1587 goto next;
1588 default:
1589 /* XXX shorten rx ring, instead? */
1590 aprint_error_dev(sc->sc_dev,
1591 "could not load DMA map\n");
1592 }
1593
1594 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ);
1595
1596 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS)
1597 rssi = UINT8_MAX - sq;
1598 else {
1599 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_IMR_RSSI);
1600 /* TBD find out each front-end's LNA gain in the
1601 * front-end's units
1602 */
1603 if ((hrssi & RTW_RXRSSI_IMR_LNA) == 0)
1604 rssi |= 0x80;
1605 }
1606
1607 /* Note well: now we cannot recycle the rs_mbuf unless
1608 * we restore its original length.
1609 */
1610 m->m_pkthdr.rcvif = ifp;
1611 m->m_pkthdr.len = m->m_len = len;
1612
1613 wh = mtod(m, struct ieee80211_frame_min *);
1614
1615 if (!IS_BEACON(wh->i_fc[0]))
1616 sc->sc_led_state.ls_event |= RTW_LED_S_RX;
1617
1618 sc->sc_tsfth = htsfth;
1619
1620 #ifdef RTW_DEBUG
1621 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
1622 (IFF_DEBUG|IFF_LINK2)) {
1623 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len,
1624 rate, rssi);
1625 }
1626 #endif /* RTW_DEBUG */
1627
1628 #if NBPFILTER > 0
1629 if (sc->sc_radiobpf != NULL) {
1630 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
1631
1632 rr->rr_tsft =
1633 htole64(((uint64_t)htsfth << 32) | htsftl);
1634
1635 rr->rr_flags = IEEE80211_RADIOTAP_F_FCS;
1636
1637 if ((hstat & RTW_RXSTAT_SPLCP) != 0)
1638 rr->rr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1639 if ((hstat & RTW_RXSTAT_CRC32) != 0)
1640 rr->rr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
1641
1642 rr->rr_rate = rate;
1643
1644 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS)
1645 rr->rr_u.u_philips.p_antsignal = rssi;
1646 else {
1647 rr->rr_u.u_other.o_antsignal = rssi;
1648 rr->rr_u.u_other.o_barker_lock =
1649 htole16(UINT8_MAX - sq);
1650 }
1651
1652 bpf_mtap2(sc->sc_radiobpf, rr,
1653 sizeof(sc->sc_rxtapu), m);
1654 }
1655 #endif /* NBPFILTER > 0 */
1656
1657 if ((hstat & RTW_RXSTAT_RES) != 0) {
1658 m_freem(m);
1659 goto next;
1660 }
1661
1662 /* CRC is included with the packet; trim it off. */
1663 m_adj(m, -IEEE80211_CRC_LEN);
1664
1665 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */
1666 ni = ieee80211_find_rxnode(&sc->sc_ic, wh);
1667 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl);
1668 ieee80211_free_node(ni);
1669 next:
1670 rtw_rxdesc_init(rdb, rs, next, 0);
1671 }
1672 #undef IS_BEACON
1673 }
1674
1675 static void
1676 rtw_txsoft_release(bus_dma_tag_t dmat, struct ieee80211com *ic,
1677 struct rtw_txsoft *ts)
1678 {
1679 struct mbuf *m;
1680 struct ieee80211_node *ni;
1681
1682 m = ts->ts_mbuf;
1683 ni = ts->ts_ni;
1684 KASSERT(m != NULL);
1685 KASSERT(ni != NULL);
1686 ts->ts_mbuf = NULL;
1687 ts->ts_ni = NULL;
1688
1689 bus_dmamap_sync(dmat, ts->ts_dmamap, 0, ts->ts_dmamap->dm_mapsize,
1690 BUS_DMASYNC_POSTWRITE);
1691 bus_dmamap_unload(dmat, ts->ts_dmamap);
1692 m_freem(m);
1693 ieee80211_free_node(ni);
1694 }
1695
1696 static void
1697 rtw_txsofts_release(bus_dma_tag_t dmat, struct ieee80211com *ic,
1698 struct rtw_txsoft_blk *tsb)
1699 {
1700 struct rtw_txsoft *ts;
1701
1702 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1703 rtw_txsoft_release(dmat, ic, ts);
1704 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1705 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1706 }
1707 tsb->tsb_tx_timer = 0;
1708 }
1709
1710 static inline void
1711 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb,
1712 struct rtw_txsoft *ts, int ndesc)
1713 {
1714 uint32_t hstat;
1715 int data_retry, rts_retry;
1716 struct rtw_txdesc *tdn;
1717 const char *condstring;
1718 struct ifnet *ifp = &sc->sc_if;
1719
1720 rtw_txsoft_release(sc->sc_dmat, &sc->sc_ic, ts);
1721
1722 tdb->tdb_nfree += ndesc;
1723
1724 tdn = &tdb->tdb_desc[ts->ts_last];
1725
1726 hstat = le32toh(tdn->td_stat);
1727 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);
1728 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);
1729
1730 ifp->if_collisions += rts_retry + data_retry;
1731
1732 if ((hstat & RTW_TXSTAT_TOK) != 0)
1733 condstring = "ok";
1734 else {
1735 ifp->if_oerrors++;
1736 condstring = "error";
1737 }
1738
1739 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
1740 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n",
1741 device_xname(sc->sc_dev), ts, ts->ts_first, ts->ts_last,
1742 condstring, rts_retry, data_retry));
1743 }
1744
1745 static void
1746 rtw_reset_oactive(struct rtw_softc *sc)
1747 {
1748 short oflags;
1749 int pri;
1750 struct rtw_txsoft_blk *tsb;
1751 struct rtw_txdesc_blk *tdb;
1752 oflags = sc->sc_if.if_flags;
1753 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1754 tsb = &sc->sc_txsoft_blk[pri];
1755 tdb = &sc->sc_txdesc_blk[pri];
1756 if (!SIMPLEQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0)
1757 sc->sc_if.if_flags &= ~IFF_OACTIVE;
1758 }
1759 if (oflags != sc->sc_if.if_flags) {
1760 DPRINTF(sc, RTW_DEBUG_OACTIVE,
1761 ("%s: reset OACTIVE\n", __func__));
1762 }
1763 }
1764
1765 /* Collect transmitted packets. */
1766 static bool
1767 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb,
1768 struct rtw_txdesc_blk *tdb, int force)
1769 {
1770 bool collected = false;
1771 int ndesc;
1772 struct rtw_txsoft *ts;
1773
1774 #ifdef RTW_DEBUG
1775 rtw_dump_rings(sc);
1776 #endif
1777
1778 while ((ts = SIMPLEQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1779 /* If we're clearing a failed transmission, only clear
1780 up to the last packet the hardware has processed. */
1781 if (ts->ts_first == rtw_txring_next(&sc->sc_regs, tdb))
1782 break;
1783
1784 ndesc = 1 + ts->ts_last - ts->ts_first;
1785 if (ts->ts_last < ts->ts_first)
1786 ndesc += tdb->tdb_ndesc;
1787
1788 KASSERT(ndesc > 0);
1789
1790 rtw_txdescs_sync(tdb, ts->ts_first, ndesc,
1791 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1792
1793 if (force) {
1794 int next;
1795 #ifdef RTW_DIAG
1796 printf("%s: clearing packet, stats", __func__);
1797 #endif
1798 for (next = ts->ts_first; ;
1799 next = RTW_NEXT_IDX(tdb, next)) {
1800 #ifdef RTW_DIAG
1801 printf(" %" PRIx32 "/%" PRIx32 "/%" PRIx32 "/%" PRIu32 "/%" PRIx32, le32toh(tdb->tdb_desc[next].td_stat), le32toh(tdb->tdb_desc[next].td_ctl1), le32toh(tdb->tdb_desc[next].td_buf), le32toh(tdb->tdb_desc[next].td_len), le32toh(tdb->tdb_desc[next].td_next));
1802 #endif
1803 tdb->tdb_desc[next].td_stat &=
1804 ~htole32(RTW_TXSTAT_OWN);
1805 if (next == ts->ts_last)
1806 break;
1807 }
1808 rtw_txdescs_sync(tdb, ts->ts_first, ndesc,
1809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1810 #ifdef RTW_DIAG
1811 next = RTW_NEXT_IDX(tdb, next);
1812 printf(" -> end %u stat %" PRIx32 ", was %u\n", next,
1813 le32toh(tdb->tdb_desc[next].td_stat),
1814 rtw_txring_next(&sc->sc_regs, tdb));
1815 #endif
1816 } else if ((tdb->tdb_desc[ts->ts_last].td_stat &
1817 htole32(RTW_TXSTAT_OWN)) != 0) {
1818 rtw_txdescs_sync(tdb, ts->ts_last, 1,
1819 BUS_DMASYNC_PREREAD);
1820 break;
1821 }
1822
1823 collected = true;
1824
1825 rtw_collect_txpkt(sc, tdb, ts, ndesc);
1826 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1827 SIMPLEQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1828 }
1829
1830 /* no more pending transmissions, cancel watchdog */
1831 if (ts == NULL)
1832 tsb->tsb_tx_timer = 0;
1833 rtw_reset_oactive(sc);
1834
1835 return collected;
1836 }
1837
1838 static void
1839 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr)
1840 {
1841 int pri;
1842 struct rtw_txsoft_blk *tsb;
1843 struct rtw_txdesc_blk *tdb;
1844 struct ifnet *ifp = &sc->sc_if;
1845
1846 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1847 tsb = &sc->sc_txsoft_blk[pri];
1848 tdb = &sc->sc_txdesc_blk[pri];
1849 rtw_collect_txring(sc, tsb, tdb, 0);
1850 }
1851
1852 if ((isr & RTW_INTR_TX) != 0)
1853 rtw_start(ifp);
1854
1855 return;
1856 }
1857
1858 static void
1859 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr)
1860 {
1861 u_int next;
1862 uint32_t tsfth, tsftl;
1863 struct ieee80211com *ic;
1864 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN];
1865 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN];
1866 struct mbuf *m;
1867
1868 tsfth = RTW_READ(&sc->sc_regs, RTW_TSFTRH);
1869 tsftl = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
1870
1871 if ((isr & (RTW_INTR_TBDOK|RTW_INTR_TBDER)) != 0) {
1872 next = rtw_txring_next(&sc->sc_regs, tdb);
1873 RTW_DPRINTF(RTW_DEBUG_BEACON,
1874 ("%s: beacon ring %sprocessed, isr = %#04" PRIx16
1875 ", next %u expected %u, %" PRIu64 "\n", __func__,
1876 (next == tdb->tdb_next) ? "" : "un", isr, next,
1877 tdb->tdb_next, (uint64_t)tsfth << 32 | tsftl));
1878 if ((RTW_READ8(&sc->sc_regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0)
1879 rtw_collect_txring(sc, tsb, tdb, 1);
1880 }
1881 /* Start beacon transmission. */
1882
1883 if ((isr & RTW_INTR_BCNINT) != 0 &&
1884 sc->sc_ic.ic_state == IEEE80211_S_RUN &&
1885 SIMPLEQ_EMPTY(&tsb->tsb_dirtyq)) {
1886 RTW_DPRINTF(RTW_DEBUG_BEACON,
1887 ("%s: beacon prep. time, isr = %#04" PRIx16
1888 ", %16" PRIu64 "\n", __func__, isr,
1889 (uint64_t)tsfth << 32 | tsftl));
1890 ic = &sc->sc_ic;
1891 m = rtw_beacon_alloc(sc, ic->ic_bss);
1892
1893 if (m == NULL) {
1894 aprint_error_dev(sc->sc_dev,
1895 "could not allocate beacon\n");
1896 return;
1897 }
1898 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss);
1899 IF_ENQUEUE(&sc->sc_beaconq, m);
1900 rtw_start(&sc->sc_if);
1901 }
1902 }
1903
1904 static void
1905 rtw_intr_atim(struct rtw_softc *sc)
1906 {
1907 /* TBD */
1908 return;
1909 }
1910
1911 #ifdef RTW_DEBUG
1912 static void
1913 rtw_dump_rings(struct rtw_softc *sc)
1914 {
1915 struct rtw_txdesc_blk *tdb;
1916 struct rtw_rxdesc *rd;
1917 struct rtw_rxdesc_blk *rdb;
1918 int desc, pri;
1919
1920 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0)
1921 return;
1922
1923 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1924 tdb = &sc->sc_txdesc_blk[pri];
1925 printf("%s: txpri %d ndesc %d nfree %d\n", __func__, pri,
1926 tdb->tdb_ndesc, tdb->tdb_nfree);
1927 for (desc = 0; desc < tdb->tdb_ndesc; desc++)
1928 rtw_print_txdesc(sc, ".", NULL, tdb, desc);
1929 }
1930
1931 rdb = &sc->sc_rxdesc_blk;
1932
1933 for (desc = 0; desc < RTW_RXQLEN; desc++) {
1934 rd = &rdb->rdb_desc[desc];
1935 printf("%s: %sctl %08x rsvd0/rssi %08x buf/tsftl %08x "
1936 "rsvd1/tsfth %08x\n", __func__,
1937 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "",
1938 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi),
1939 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth));
1940 }
1941 }
1942 #endif /* RTW_DEBUG */
1943
1944 static void
1945 rtw_hwring_setup(struct rtw_softc *sc)
1946 {
1947 int pri;
1948 struct rtw_regs *regs = &sc->sc_regs;
1949 struct rtw_txdesc_blk *tdb;
1950
1951 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_basereg = RTW_TLPDA;
1952 sc->sc_txdesc_blk[RTW_TXPRILO].tdb_base = RTW_RING_BASE(sc, hd_txlo);
1953 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_basereg = RTW_TNPDA;
1954 sc->sc_txdesc_blk[RTW_TXPRIMD].tdb_base = RTW_RING_BASE(sc, hd_txmd);
1955 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_basereg = RTW_THPDA;
1956 sc->sc_txdesc_blk[RTW_TXPRIHI].tdb_base = RTW_RING_BASE(sc, hd_txhi);
1957 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_basereg = RTW_TBDA;
1958 sc->sc_txdesc_blk[RTW_TXPRIBCN].tdb_base = RTW_RING_BASE(sc, hd_bcn);
1959
1960 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1961 tdb = &sc->sc_txdesc_blk[pri];
1962 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
1963 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC,
1964 ("%s: reg[tdb->tdb_basereg] <- %" PRIxPTR "\n", __func__,
1965 (uintptr_t)tdb->tdb_base));
1966 }
1967
1968 RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx));
1969
1970 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1971 ("%s: reg[RDSAR] <- %" PRIxPTR "\n", __func__,
1972 (uintptr_t)RTW_RING_BASE(sc, hd_rx)));
1973
1974 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
1975
1976 }
1977
1978 static int
1979 rtw_swring_setup(struct rtw_softc *sc)
1980 {
1981 int rc;
1982 struct rtw_rxdesc_blk *rdb;
1983
1984 rtw_txdesc_blk_init_all(&sc->sc_txdesc_blk[0]);
1985
1986 rtw_txsoft_blk_init_all(&sc->sc_txsoft_blk[0]);
1987
1988 rdb = &sc->sc_rxdesc_blk;
1989 if ((rc = rtw_rxsoft_init_all(sc->sc_dmat, sc->sc_rxsoft, &rdb->rdb_ndesc,
1990 sc->sc_dev)) != 0 && rdb->rdb_ndesc == 0) {
1991 aprint_error_dev(sc->sc_dev, "could not allocate rx buffers\n");
1992 return rc;
1993 }
1994
1995 rdb = &sc->sc_rxdesc_blk;
1996 rtw_rxdescs_sync(rdb, 0, rdb->rdb_ndesc,
1997 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1998 rtw_rxdesc_init_all(rdb, sc->sc_rxsoft, 1);
1999 rdb->rdb_next = 0;
2000
2001 rtw_txdescs_sync_all(&sc->sc_txdesc_blk[0]);
2002 return 0;
2003 }
2004
2005 static void
2006 rtw_txdesc_blk_init(struct rtw_txdesc_blk *tdb)
2007 {
2008 int i;
2009
2010 (void)memset(tdb->tdb_desc, 0,
2011 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc);
2012 for (i = 0; i < tdb->tdb_ndesc; i++)
2013 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i));
2014 }
2015
2016 static u_int
2017 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
2018 {
2019 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
2020 sizeof(struct rtw_txdesc);
2021 }
2022
2023 #ifdef RTW_DIAG
2024 static void
2025 rtw_txring_fixup(struct rtw_softc *sc, const char *fn, int ln)
2026 {
2027 int pri;
2028 u_int next;
2029 struct rtw_txdesc_blk *tdb;
2030 struct rtw_regs *regs = &sc->sc_regs;
2031
2032 for (pri = 0; pri < RTW_NTXPRI; pri++) {
2033 int i;
2034 tdb = &sc->sc_txdesc_blk[pri];
2035 next = rtw_txring_next(regs, tdb);
2036 if (tdb->tdb_next == next)
2037 continue;
2038 for (i = 0; next != tdb->tdb_next;
2039 next = RTW_NEXT_IDX(tdb, next), i++) {
2040 if ((tdb->tdb_desc[next].td_stat & htole32(RTW_TXSTAT_OWN)) == 0)
2041 break;
2042 }
2043 printf("%s:%d: tx-ring %d expected next %u, read %u+%d -> %s\n", fn,
2044 ln, pri, tdb->tdb_next, next, i, tdb->tdb_next == next ? "okay" : "BAD");
2045 if (tdb->tdb_next == next)
2046 continue;
2047 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1);
2048 }
2049 }
2050 #endif
2051
2052 static void
2053 rtw_txdescs_reset(struct rtw_softc *sc)
2054 {
2055 int pri;
2056 struct rtw_txsoft_blk *tsb;
2057 struct rtw_txdesc_blk *tdb;
2058
2059 for (pri = 0; pri < RTW_NTXPRI; pri++) {
2060 tsb = &sc->sc_txsoft_blk[pri];
2061 tdb = &sc->sc_txdesc_blk[pri];
2062 rtw_collect_txring(sc, tsb, tdb, 1);
2063 #ifdef RTW_DIAG
2064 if (!SIMPLEQ_EMPTY(&tsb->tsb_dirtyq))
2065 printf("%s: packets left in ring %d\n", __func__, pri);
2066 #endif
2067 }
2068 }
2069
2070 static void
2071 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr)
2072 {
2073 aprint_error_dev(sc->sc_dev, "tx fifo underflow\n");
2074
2075 RTW_DPRINTF(RTW_DEBUG_BUGS, ("%s: cleaning up xmit, isr %" PRIx16
2076 "\n", device_xname(sc->sc_dev), isr));
2077
2078 #ifdef RTW_DEBUG
2079 rtw_dump_rings(sc);
2080 #endif /* RTW_DEBUG */
2081
2082 /* Collect tx'd packets. XXX let's hope this stops the transmit
2083 * timeouts.
2084 */
2085 rtw_txdescs_reset(sc);
2086
2087 #ifdef RTW_DEBUG
2088 rtw_dump_rings(sc);
2089 #endif /* RTW_DEBUG */
2090 }
2091
2092 static inline void
2093 rtw_suspend_ticks(struct rtw_softc *sc)
2094 {
2095 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
2096 ("%s: suspending ticks\n", device_xname(sc->sc_dev)));
2097 sc->sc_do_tick = 0;
2098 }
2099
2100 static inline void
2101 rtw_resume_ticks(struct rtw_softc *sc)
2102 {
2103 uint32_t tsftrl0, tsftrl1, next_tick;
2104
2105 tsftrl0 = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
2106
2107 tsftrl1 = RTW_READ(&sc->sc_regs, RTW_TSFTRL);
2108 next_tick = tsftrl1 + 1000000;
2109 RTW_WRITE(&sc->sc_regs, RTW_TINT, next_tick);
2110
2111 sc->sc_do_tick = 1;
2112
2113 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
2114 ("%s: resume ticks delta %#08x now %#08x next %#08x\n",
2115 device_xname(sc->sc_dev), tsftrl1 - tsftrl0, tsftrl1, next_tick));
2116 }
2117
2118 static void
2119 rtw_intr_timeout(struct rtw_softc *sc)
2120 {
2121 RTW_DPRINTF(RTW_DEBUG_TIMEOUT, ("%s: timeout\n", device_xname(sc->sc_dev)));
2122 if (sc->sc_do_tick)
2123 rtw_resume_ticks(sc);
2124 return;
2125 }
2126
2127 int
2128 rtw_intr(void *arg)
2129 {
2130 int i;
2131 struct rtw_softc *sc = arg;
2132 struct rtw_regs *regs = &sc->sc_regs;
2133 uint16_t isr;
2134 struct ifnet *ifp = &sc->sc_if;
2135
2136 /*
2137 * If the interface isn't running, the interrupt couldn't
2138 * possibly have come from us.
2139 */
2140 if ((ifp->if_flags & IFF_RUNNING) == 0 ||
2141 !device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) {
2142 RTW_DPRINTF(RTW_DEBUG_INTR, ("%s: stray interrupt\n",
2143 device_xname(sc->sc_dev)));
2144 return (0);
2145 }
2146
2147 for (i = 0; i < 10; i++) {
2148 isr = RTW_READ16(regs, RTW_ISR);
2149
2150 RTW_WRITE16(regs, RTW_ISR, isr);
2151 RTW_WBR(regs, RTW_ISR, RTW_ISR);
2152
2153 if (sc->sc_intr_ack != NULL)
2154 (*sc->sc_intr_ack)(regs);
2155
2156 if (isr == 0)
2157 break;
2158
2159 #ifdef RTW_DEBUG
2160 #define PRINTINTR(flag) do { \
2161 if ((isr & flag) != 0) { \
2162 printf("%s" #flag, delim); \
2163 delim = ","; \
2164 } \
2165 } while (0)
2166
2167 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) {
2168 const char *delim = "<";
2169
2170 printf("%s: reg[ISR] = %x", device_xname(sc->sc_dev),
2171 isr);
2172
2173 PRINTINTR(RTW_INTR_TXFOVW);
2174 PRINTINTR(RTW_INTR_TIMEOUT);
2175 PRINTINTR(RTW_INTR_BCNINT);
2176 PRINTINTR(RTW_INTR_ATIMINT);
2177 PRINTINTR(RTW_INTR_TBDER);
2178 PRINTINTR(RTW_INTR_TBDOK);
2179 PRINTINTR(RTW_INTR_THPDER);
2180 PRINTINTR(RTW_INTR_THPDOK);
2181 PRINTINTR(RTW_INTR_TNPDER);
2182 PRINTINTR(RTW_INTR_TNPDOK);
2183 PRINTINTR(RTW_INTR_RXFOVW);
2184 PRINTINTR(RTW_INTR_RDU);
2185 PRINTINTR(RTW_INTR_TLPDER);
2186 PRINTINTR(RTW_INTR_TLPDOK);
2187 PRINTINTR(RTW_INTR_RER);
2188 PRINTINTR(RTW_INTR_ROK);
2189
2190 printf(">\n");
2191 }
2192 #undef PRINTINTR
2193 #endif /* RTW_DEBUG */
2194
2195 if ((isr & RTW_INTR_RX) != 0)
2196 rtw_intr_rx(sc, isr);
2197 if ((isr & RTW_INTR_TX) != 0)
2198 rtw_intr_tx(sc, isr);
2199 if ((isr & RTW_INTR_BEACON) != 0)
2200 rtw_intr_beacon(sc, isr);
2201 if ((isr & RTW_INTR_ATIMINT) != 0)
2202 rtw_intr_atim(sc);
2203 if ((isr & RTW_INTR_IOERROR) != 0)
2204 rtw_intr_ioerror(sc, isr);
2205 if ((isr & RTW_INTR_TIMEOUT) != 0)
2206 rtw_intr_timeout(sc);
2207 }
2208
2209 return 1;
2210 }
2211
2212 /* Must be called at splnet. */
2213 static void
2214 rtw_stop(struct ifnet *ifp, int disable)
2215 {
2216 int pri;
2217 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
2218 struct ieee80211com *ic = &sc->sc_ic;
2219 struct rtw_regs *regs = &sc->sc_regs;
2220
2221 rtw_suspend_ticks(sc);
2222
2223 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2224
2225 if (device_has_power(sc->sc_dev)) {
2226 /* Disable interrupts. */
2227 RTW_WRITE16(regs, RTW_IMR, 0);
2228
2229 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
2230
2231 /* Stop the transmit and receive processes. First stop DMA,
2232 * then disable receiver and transmitter.
2233 */
2234 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2235
2236 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
2237
2238 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2239 }
2240
2241 for (pri = 0; pri < RTW_NTXPRI; pri++) {
2242 rtw_txsofts_release(sc->sc_dmat, &sc->sc_ic,
2243 &sc->sc_txsoft_blk[pri]);
2244 }
2245
2246 rtw_rxbufs_release(sc->sc_dmat, &sc->sc_rxsoft[0]);
2247
2248 /* Mark the interface as not running. Cancel the watchdog timer. */
2249 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2250 ifp->if_timer = 0;
2251
2252 if (disable)
2253 pmf_device_suspend(sc->sc_dev, &sc->sc_qual);
2254
2255 return;
2256 }
2257
2258 const char *
2259 rtw_pwrstate_string(enum rtw_pwrstate power)
2260 {
2261 switch (power) {
2262 case RTW_ON:
2263 return "on";
2264 case RTW_SLEEP:
2265 return "sleep";
2266 case RTW_OFF:
2267 return "off";
2268 default:
2269 return "unknown";
2270 }
2271 }
2272
2273 /* XXX For Maxim, I am using the RFMD settings gleaned from the
2274 * reference driver, plus a magic Maxim "ON" value that comes from
2275 * the Realtek document "Windows PG for Rtl8180."
2276 */
2277 static void
2278 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2279 int before_rf, int digphy)
2280 {
2281 uint32_t anaparm;
2282
2283 anaparm = RTW_READ(regs, RTW_ANAPARM);
2284 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2285
2286 switch (power) {
2287 case RTW_OFF:
2288 if (before_rf)
2289 return;
2290 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF;
2291 anaparm |= RTW_ANAPARM_TXDACOFF;
2292 break;
2293 case RTW_SLEEP:
2294 if (!before_rf)
2295 return;
2296 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP;
2297 anaparm |= RTW_ANAPARM_TXDACOFF;
2298 break;
2299 case RTW_ON:
2300 if (!before_rf)
2301 return;
2302 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON;
2303 break;
2304 }
2305 RTW_DPRINTF(RTW_DEBUG_PWR,
2306 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2307 __func__, rtw_pwrstate_string(power),
2308 (before_rf) ? "before" : "after", anaparm));
2309
2310 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2311 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2312 }
2313
2314 /* XXX I am using the RFMD settings gleaned from the reference
2315 * driver. They agree
2316 */
2317 static void
2318 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2319 int before_rf, int digphy)
2320 {
2321 uint32_t anaparm;
2322
2323 anaparm = RTW_READ(regs, RTW_ANAPARM);
2324 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2325
2326 switch (power) {
2327 case RTW_OFF:
2328 if (before_rf)
2329 return;
2330 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF;
2331 anaparm |= RTW_ANAPARM_TXDACOFF;
2332 break;
2333 case RTW_SLEEP:
2334 if (!before_rf)
2335 return;
2336 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP;
2337 anaparm |= RTW_ANAPARM_TXDACOFF;
2338 break;
2339 case RTW_ON:
2340 if (!before_rf)
2341 return;
2342 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON;
2343 break;
2344 }
2345 RTW_DPRINTF(RTW_DEBUG_PWR,
2346 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2347 __func__, rtw_pwrstate_string(power),
2348 (before_rf) ? "before" : "after", anaparm));
2349
2350 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2351 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2352 }
2353
2354 static void
2355 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2356 int before_rf, int digphy)
2357 {
2358 uint32_t anaparm;
2359
2360 anaparm = RTW_READ(regs, RTW_ANAPARM);
2361 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2362
2363 switch (power) {
2364 case RTW_OFF:
2365 if (before_rf)
2366 return;
2367 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF;
2368 anaparm |= RTW_ANAPARM_TXDACOFF;
2369 break;
2370 case RTW_SLEEP:
2371 if (!before_rf)
2372 return;
2373 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP;
2374 anaparm |= RTW_ANAPARM_TXDACOFF;
2375 break;
2376 case RTW_ON:
2377 if (!before_rf)
2378 return;
2379 if (digphy) {
2380 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON;
2381 /* XXX guess */
2382 anaparm |= RTW_ANAPARM_TXDACOFF;
2383 } else
2384 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON;
2385 break;
2386 }
2387 RTW_DPRINTF(RTW_DEBUG_PWR,
2388 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2389 __func__, rtw_pwrstate_string(power),
2390 (before_rf) ? "before" : "after", anaparm));
2391
2392 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2393 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2394 }
2395
2396 static void
2397 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf,
2398 int digphy)
2399 {
2400 struct rtw_regs *regs = &sc->sc_regs;
2401
2402 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
2403
2404 (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy);
2405
2406 rtw_set_access(regs, RTW_ACCESS_NONE);
2407
2408 return;
2409 }
2410
2411 static int
2412 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power)
2413 {
2414 int rc;
2415
2416 RTW_DPRINTF(RTW_DEBUG_PWR,
2417 ("%s: %s->%s\n", __func__,
2418 rtw_pwrstate_string(sc->sc_pwrstate), rtw_pwrstate_string(power)));
2419
2420 if (sc->sc_pwrstate == power)
2421 return 0;
2422
2423 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY);
2424 rc = rtw_rf_pwrstate(sc->sc_rf, power);
2425 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY);
2426
2427 switch (power) {
2428 case RTW_ON:
2429 /* TBD set LEDs */
2430 break;
2431 case RTW_SLEEP:
2432 /* TBD */
2433 break;
2434 case RTW_OFF:
2435 /* TBD */
2436 break;
2437 }
2438 if (rc == 0)
2439 sc->sc_pwrstate = power;
2440 else
2441 sc->sc_pwrstate = RTW_OFF;
2442 return rc;
2443 }
2444
2445 static int
2446 rtw_tune(struct rtw_softc *sc)
2447 {
2448 struct ieee80211com *ic = &sc->sc_ic;
2449 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
2450 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
2451 u_int chan;
2452 int rc;
2453 int antdiv = sc->sc_flags & RTW_F_ANTDIV,
2454 dflantb = sc->sc_flags & RTW_F_DFLANTB;
2455
2456 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2457 KASSERT(chan != IEEE80211_CHAN_ANY);
2458
2459 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2460 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2461
2462 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2463 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2464
2465 if (chan == sc->sc_cur_chan) {
2466 RTW_DPRINTF(RTW_DEBUG_TUNE,
2467 ("%s: already tuned chan #%d\n", __func__, chan));
2468 return 0;
2469 }
2470
2471 rtw_suspend_ticks(sc);
2472
2473 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2474
2475 /* TBD wait for Tx to complete */
2476
2477 KASSERT(device_has_power(sc->sc_dev));
2478
2479 if ((rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf,
2480 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan), sc->sc_csthr,
2481 ic->ic_curchan->ic_freq, antdiv, dflantb, RTW_ON)) != 0) {
2482 /* XXX condition on powersaving */
2483 aprint_error_dev(sc->sc_dev, "phy init failed\n");
2484 }
2485
2486 sc->sc_cur_chan = chan;
2487
2488 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2489
2490 rtw_resume_ticks(sc);
2491
2492 return rc;
2493 }
2494
2495 bool
2496 rtw_suspend(device_t self, pmf_qual_t qual)
2497 {
2498 int rc;
2499 struct rtw_softc *sc = device_private(self);
2500
2501 sc->sc_flags &= ~RTW_F_DK_VALID;
2502
2503 if (!device_has_power(self))
2504 return false;
2505
2506 /* turn off PHY */
2507 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0) {
2508 aprint_error_dev(self, "failed to turn off PHY (%d)\n", rc);
2509 return false;
2510 }
2511
2512 rtw_disable_interrupts(&sc->sc_regs);
2513
2514 return true;
2515 }
2516
2517 bool
2518 rtw_resume(device_t self, pmf_qual_t qual)
2519 {
2520 struct rtw_softc *sc = device_private(self);
2521
2522 /* Power may have been removed, resetting WEP keys.
2523 */
2524 sc->sc_flags &= ~RTW_F_DK_VALID;
2525 rtw_enable_interrupts(sc);
2526
2527 return true;
2528 }
2529
2530 static void
2531 rtw_transmit_config(struct rtw_regs *regs)
2532 {
2533 uint32_t tcr;
2534
2535 tcr = RTW_READ(regs, RTW_TCR);
2536
2537 tcr |= RTW_TCR_CWMIN;
2538 tcr &= ~RTW_TCR_MXDMA_MASK;
2539 tcr |= RTW_TCR_MXDMA_256;
2540 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */
2541 tcr &= ~RTW_TCR_LBK_MASK;
2542 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */
2543
2544 /* set short/long retry limits */
2545 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK);
2546 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK);
2547
2548 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */
2549
2550 RTW_WRITE(regs, RTW_TCR, tcr);
2551 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
2552 }
2553
2554 static void
2555 rtw_disable_interrupts(struct rtw_regs *regs)
2556 {
2557 RTW_WRITE16(regs, RTW_IMR, 0);
2558 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2559 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2560 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2561 }
2562
2563 static void
2564 rtw_enable_interrupts(struct rtw_softc *sc)
2565 {
2566 struct rtw_regs *regs = &sc->sc_regs;
2567
2568 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT;
2569 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT;
2570
2571 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
2572 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2573 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2574 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2575
2576 /* XXX necessary? */
2577 if (sc->sc_intr_ack != NULL)
2578 (*sc->sc_intr_ack)(regs);
2579 }
2580
2581 static void
2582 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode)
2583 {
2584 uint8_t msr;
2585
2586 /* I'm guessing that MSR is protected as CONFIG[0123] are. */
2587 rtw_set_access(&sc->sc_regs, RTW_ACCESS_CONFIG);
2588
2589 msr = RTW_READ8(&sc->sc_regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK;
2590
2591 switch (opmode) {
2592 case IEEE80211_M_AHDEMO:
2593 case IEEE80211_M_IBSS:
2594 msr |= RTW_MSR_NETYPE_ADHOC_OK;
2595 break;
2596 case IEEE80211_M_HOSTAP:
2597 msr |= RTW_MSR_NETYPE_AP_OK;
2598 break;
2599 case IEEE80211_M_MONITOR:
2600 /* XXX */
2601 msr |= RTW_MSR_NETYPE_NOLINK;
2602 break;
2603 case IEEE80211_M_STA:
2604 msr |= RTW_MSR_NETYPE_INFRA_OK;
2605 break;
2606 }
2607 RTW_WRITE8(&sc->sc_regs, RTW_MSR, msr);
2608
2609 rtw_set_access(&sc->sc_regs, RTW_ACCESS_NONE);
2610 }
2611
2612 #define rtw_calchash(addr) \
2613 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26)
2614
2615 static void
2616 rtw_pktfilt_load(struct rtw_softc *sc)
2617 {
2618 struct rtw_regs *regs = &sc->sc_regs;
2619 struct ieee80211com *ic = &sc->sc_ic;
2620 struct ethercom *ec = &sc->sc_ec;
2621 struct ifnet *ifp = &sc->sc_if;
2622 int hash;
2623 uint32_t hashes[2] = { 0, 0 };
2624 struct ether_multi *enm;
2625 struct ether_multistep step;
2626
2627 /* XXX might be necessary to stop Rx/Tx engines while setting filters */
2628
2629 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK;
2630 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK);
2631
2632 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT;
2633 /* MAC auto-reset PHY (huh?) */
2634 sc->sc_rcr |= RTW_RCR_ENMARP;
2635 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */
2636 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE;
2637
2638 switch (ic->ic_opmode) {
2639 case IEEE80211_M_MONITOR:
2640 sc->sc_rcr |= RTW_RCR_MONITOR;
2641 break;
2642 case IEEE80211_M_AHDEMO:
2643 case IEEE80211_M_IBSS:
2644 /* receive broadcasts in our BSS */
2645 sc->sc_rcr |= RTW_RCR_ADD3;
2646 break;
2647 default:
2648 break;
2649 }
2650
2651 ifp->if_flags &= ~IFF_ALLMULTI;
2652
2653 /*
2654 * Program the 64-bit multicast hash filter.
2655 */
2656 ETHER_FIRST_MULTI(step, ec, enm);
2657 while (enm != NULL) {
2658 /* XXX */
2659 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
2660 ETHER_ADDR_LEN) != 0) {
2661 ifp->if_flags |= IFF_ALLMULTI;
2662 break;
2663 }
2664
2665 hash = rtw_calchash(enm->enm_addrlo);
2666 hashes[hash >> 5] |= (1 << (hash & 0x1f));
2667 ETHER_NEXT_MULTI(step, enm);
2668 }
2669
2670 /* XXX accept all broadcast if scanning */
2671 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2672 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2673
2674 if (ifp->if_flags & IFF_PROMISC) {
2675 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2676 sc->sc_rcr |= RTW_RCR_ACRC32; /* accept frames failing CRC */
2677 sc->sc_rcr |= RTW_RCR_AICV; /* accept frames failing ICV */
2678 ifp->if_flags |= IFF_ALLMULTI;
2679 }
2680
2681 if (ifp->if_flags & IFF_ALLMULTI)
2682 hashes[0] = hashes[1] = 0xffffffff;
2683
2684 if ((hashes[0] | hashes[1]) != 0)
2685 sc->sc_rcr |= RTW_RCR_AM; /* accept multicast */
2686
2687 RTW_WRITE(regs, RTW_MAR0, hashes[0]);
2688 RTW_WRITE(regs, RTW_MAR1, hashes[1]);
2689 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
2690 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
2691
2692 DPRINTF(sc, RTW_DEBUG_PKTFILT,
2693 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n",
2694 device_xname(sc->sc_dev), RTW_READ(regs, RTW_MAR0),
2695 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
2696 }
2697
2698 static struct mbuf *
2699 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni)
2700 {
2701 struct ieee80211com *ic = &sc->sc_ic;
2702 struct mbuf *m;
2703 struct ieee80211_beacon_offsets boff;
2704
2705 if ((m = ieee80211_beacon_alloc(ic, ni, &boff)) != NULL) {
2706 RTW_DPRINTF(RTW_DEBUG_BEACON,
2707 ("%s: m %p len %u\n", __func__, m, m->m_len));
2708 }
2709 return m;
2710 }
2711
2712 /* Must be called at splnet. */
2713 static int
2714 rtw_init(struct ifnet *ifp)
2715 {
2716 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
2717 struct ieee80211com *ic = &sc->sc_ic;
2718 struct rtw_regs *regs = &sc->sc_regs;
2719 int rc;
2720
2721 if (device_is_active(sc->sc_dev)) {
2722 /* Cancel pending I/O and reset. */
2723 rtw_stop(ifp, 0);
2724 } else if (!pmf_device_resume(sc->sc_dev, &sc->sc_qual) ||
2725 !device_is_active(sc->sc_dev))
2726 return 0;
2727
2728 DPRINTF(sc, RTW_DEBUG_TUNE, ("%s: channel %d freq %d flags 0x%04x\n",
2729 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan),
2730 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
2731
2732 if ((rc = rtw_pwrstate(sc, RTW_OFF)) != 0)
2733 goto out;
2734
2735 if ((rc = rtw_swring_setup(sc)) != 0)
2736 goto out;
2737
2738 rtw_transmit_config(regs);
2739
2740 rtw_set_access(regs, RTW_ACCESS_CONFIG);
2741
2742 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
2743 RTW_WBW(regs, RTW_MSR, RTW_BRSR);
2744
2745 /* long PLCP header, 1Mb/2Mb basic rate */
2746 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS);
2747 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
2748
2749 rtw_set_access(regs, RTW_ACCESS_ANAPARM);
2750 rtw_set_access(regs, RTW_ACCESS_NONE);
2751
2752 /* XXX from reference sources */
2753 RTW_WRITE(regs, RTW_FEMR, 0xffff);
2754 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
2755
2756 rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev);
2757
2758 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
2759 /* from Linux driver */
2760 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
2761
2762 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
2763
2764 rtw_enable_interrupts(sc);
2765
2766 rtw_pktfilt_load(sc);
2767
2768 rtw_hwring_setup(sc);
2769
2770 rtw_wep_setkeys(sc, ic->ic_nw_keys, ic->ic_def_txkey);
2771
2772 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2773
2774 ifp->if_flags |= IFF_RUNNING;
2775 ic->ic_state = IEEE80211_S_INIT;
2776
2777 RTW_WRITE16(regs, RTW_BSSID16, 0x0);
2778 RTW_WRITE(regs, RTW_BSSID32, 0x0);
2779
2780 rtw_resume_ticks(sc);
2781
2782 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
2783
2784 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2785 return ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2786 else
2787 return ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2788
2789 out:
2790 aprint_error_dev(sc->sc_dev, "interface not running\n");
2791 return rc;
2792 }
2793
2794 static inline void
2795 rtw_led_init(struct rtw_regs *regs)
2796 {
2797 uint8_t cfg0, cfg1;
2798
2799 rtw_set_access(regs, RTW_ACCESS_CONFIG);
2800
2801 cfg0 = RTW_READ8(regs, RTW_CONFIG0);
2802 cfg0 |= RTW_CONFIG0_LEDGPOEN;
2803 RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
2804
2805 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2806 RTW_DPRINTF(RTW_DEBUG_LED,
2807 ("%s: read %" PRIx8 " from reg[CONFIG1]\n", __func__, cfg1));
2808
2809 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2810 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2811 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
2812
2813 rtw_set_access(regs, RTW_ACCESS_NONE);
2814 }
2815
2816 /*
2817 * IEEE80211_S_INIT: LED1 off
2818 *
2819 * IEEE80211_S_AUTH,
2820 * IEEE80211_S_ASSOC,
2821 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx
2822 *
2823 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx
2824 */
2825 static void
2826 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate)
2827 {
2828 struct rtw_led_state *ls;
2829
2830 ls = &sc->sc_led_state;
2831
2832 switch (nstate) {
2833 case IEEE80211_S_INIT:
2834 rtw_led_init(&sc->sc_regs);
2835 aprint_debug_dev(sc->sc_dev, "stopping blink\n");
2836 callout_stop(&ls->ls_slow_ch);
2837 callout_stop(&ls->ls_fast_ch);
2838 ls->ls_slowblink = 0;
2839 ls->ls_actblink = 0;
2840 ls->ls_default = 0;
2841 break;
2842 case IEEE80211_S_SCAN:
2843 aprint_debug_dev(sc->sc_dev, "scheduling blink\n");
2844 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS);
2845 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS);
2846 /*FALLTHROUGH*/
2847 case IEEE80211_S_AUTH:
2848 case IEEE80211_S_ASSOC:
2849 ls->ls_default = RTW_LED1;
2850 ls->ls_actblink = RTW_LED1;
2851 ls->ls_slowblink = RTW_LED1;
2852 break;
2853 case IEEE80211_S_RUN:
2854 ls->ls_slowblink = 0;
2855 break;
2856 }
2857 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid);
2858 }
2859
2860 static void
2861 rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, int hwverid)
2862 {
2863 uint8_t led_condition;
2864 bus_size_t ofs;
2865 uint8_t mask, newval, val;
2866
2867 led_condition = ls->ls_default;
2868
2869 if (ls->ls_state & RTW_LED_S_SLOW)
2870 led_condition ^= ls->ls_slowblink;
2871 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX))
2872 led_condition ^= ls->ls_actblink;
2873
2874 RTW_DPRINTF(RTW_DEBUG_LED,
2875 ("%s: LED condition %" PRIx8 "\n", __func__, led_condition));
2876
2877 switch (hwverid) {
2878 default:
2879 case 'F':
2880 ofs = RTW_PSR;
2881 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;
2882 if (led_condition & RTW_LED0)
2883 newval &= ~RTW_PSR_LEDGPO0;
2884 if (led_condition & RTW_LED1)
2885 newval &= ~RTW_PSR_LEDGPO1;
2886 break;
2887 case 'D':
2888 ofs = RTW_9346CR;
2889 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;
2890 newval = RTW_9346CR_EEM_PROGRAM;
2891 if (led_condition & RTW_LED0)
2892 newval |= RTW_9346CR_EEDI;
2893 if (led_condition & RTW_LED1)
2894 newval |= RTW_9346CR_EECS;
2895 break;
2896 }
2897 val = RTW_READ8(regs, ofs);
2898 RTW_DPRINTF(RTW_DEBUG_LED,
2899 ("%s: read %" PRIx8 " from reg[%#02" PRIxPTR "]\n", __func__, val,
2900 (uintptr_t)ofs));
2901 val &= ~mask;
2902 val |= newval;
2903 RTW_WRITE8(regs, ofs, val);
2904 RTW_DPRINTF(RTW_DEBUG_LED,
2905 ("%s: wrote %" PRIx8 " to reg[%#02" PRIxPTR "]\n", __func__, val,
2906 (uintptr_t)ofs));
2907 RTW_SYNC(regs, ofs, ofs);
2908 }
2909
2910 static void
2911 rtw_led_fastblink(void *arg)
2912 {
2913 int ostate, s;
2914 struct rtw_softc *sc = (struct rtw_softc *)arg;
2915 struct rtw_led_state *ls = &sc->sc_led_state;
2916
2917 s = splnet();
2918 ostate = ls->ls_state;
2919 ls->ls_state ^= ls->ls_event;
2920
2921 if ((ls->ls_event & RTW_LED_S_TX) == 0)
2922 ls->ls_state &= ~RTW_LED_S_TX;
2923
2924 if ((ls->ls_event & RTW_LED_S_RX) == 0)
2925 ls->ls_state &= ~RTW_LED_S_RX;
2926
2927 ls->ls_event = 0;
2928
2929 if (ostate != ls->ls_state)
2930 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid);
2931 splx(s);
2932
2933 aprint_debug_dev(sc->sc_dev, "scheduling fast blink\n");
2934 callout_schedule(&ls->ls_fast_ch, RTW_LED_FAST_TICKS);
2935 }
2936
2937 static void
2938 rtw_led_slowblink(void *arg)
2939 {
2940 int s;
2941 struct rtw_softc *sc = (struct rtw_softc *)arg;
2942 struct rtw_led_state *ls = &sc->sc_led_state;
2943
2944 s = splnet();
2945 ls->ls_state ^= RTW_LED_S_SLOW;
2946 rtw_led_set(ls, &sc->sc_regs, sc->sc_hwverid);
2947 splx(s);
2948 aprint_debug_dev(sc->sc_dev, "scheduling slow blink\n");
2949 callout_schedule(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS);
2950 }
2951
2952 static void
2953 rtw_led_detach(struct rtw_led_state *ls)
2954 {
2955 callout_destroy(&ls->ls_fast_ch);
2956 callout_destroy(&ls->ls_slow_ch);
2957 }
2958
2959 static void
2960 rtw_led_attach(struct rtw_led_state *ls, void *arg)
2961 {
2962 callout_init(&ls->ls_fast_ch, 0);
2963 callout_init(&ls->ls_slow_ch, 0);
2964 callout_setfunc(&ls->ls_fast_ch, rtw_led_fastblink, arg);
2965 callout_setfunc(&ls->ls_slow_ch, rtw_led_slowblink, arg);
2966 }
2967
2968 static int
2969 rtw_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2970 {
2971 int rc = 0, s;
2972 struct rtw_softc *sc = ifp->if_softc;
2973
2974 s = splnet();
2975 if (cmd == SIOCSIFFLAGS) {
2976 if ((rc = ifioctl_common(ifp, cmd, data)) != 0)
2977 ;
2978 else switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
2979 case IFF_UP:
2980 rc = rtw_init(ifp);
2981 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2982 break;
2983 case IFF_UP|IFF_RUNNING:
2984 if (device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER))
2985 rtw_pktfilt_load(sc);
2986 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2987 break;
2988 case IFF_RUNNING:
2989 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2990 rtw_stop(ifp, 1);
2991 break;
2992 default:
2993 break;
2994 }
2995 } else if ((rc = ieee80211_ioctl(&sc->sc_ic, cmd, data)) != ENETRESET)
2996 ; /* nothing to do */
2997 else if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) {
2998 /* reload packet filter if running */
2999 if (ifp->if_flags & IFF_RUNNING)
3000 rtw_pktfilt_load(sc);
3001 rc = 0;
3002 } else if ((ifp->if_flags & IFF_UP) != 0)
3003 rc = rtw_init(ifp);
3004 else
3005 rc = 0;
3006 splx(s);
3007 return rc;
3008 }
3009
3010 /* Select a transmit ring with at least one h/w and s/w descriptor free.
3011 * Return 0 on success, -1 on failure.
3012 */
3013 static inline int
3014 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp,
3015 struct rtw_txdesc_blk **tdbp, int pri)
3016 {
3017 struct rtw_txsoft_blk *tsb;
3018 struct rtw_txdesc_blk *tdb;
3019
3020 KASSERT(pri >= 0 && pri < RTW_NTXPRI);
3021
3022 tsb = &sc->sc_txsoft_blk[pri];
3023 tdb = &sc->sc_txdesc_blk[pri];
3024
3025 if (SIMPLEQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) {
3026 if (tsb->tsb_tx_timer == 0)
3027 tsb->tsb_tx_timer = 5;
3028 *tsbp = NULL;
3029 *tdbp = NULL;
3030 return -1;
3031 }
3032 *tsbp = tsb;
3033 *tdbp = tdb;
3034 return 0;
3035 }
3036
3037 static inline struct mbuf *
3038 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri,
3039 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp,
3040 struct ieee80211_node **nip, short *if_flagsp)
3041 {
3042 struct mbuf *m;
3043
3044 if (IF_IS_EMPTY(ifq))
3045 return NULL;
3046 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
3047 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n",
3048 __func__, pri));
3049 *if_flagsp |= IFF_OACTIVE;
3050 sc->sc_if.if_timer = 1;
3051 return NULL;
3052 }
3053 IF_DEQUEUE(ifq, m);
3054 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3055 m->m_pkthdr.rcvif = NULL;
3056 KASSERT(*nip != NULL);
3057 return m;
3058 }
3059
3060 /* Point *mp at the next 802.11 frame to transmit. Point *tsbp
3061 * at the driver's selection of transmit control block for the packet.
3062 */
3063 static inline int
3064 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp,
3065 struct rtw_txdesc_blk **tdbp, struct mbuf **mp,
3066 struct ieee80211_node **nip)
3067 {
3068 int pri;
3069 struct ether_header *eh;
3070 struct mbuf *m0;
3071 struct rtw_softc *sc;
3072 short *if_flagsp;
3073
3074 *mp = NULL;
3075
3076 sc = (struct rtw_softc *)ifp->if_softc;
3077
3078 DPRINTF(sc, RTW_DEBUG_XMIT,
3079 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__));
3080
3081 if_flagsp = &ifp->if_flags;
3082
3083 if (sc->sc_ic.ic_state == IEEE80211_S_RUN &&
3084 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp,
3085 tdbp, nip, if_flagsp)) != NULL) {
3086 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue beacon frame\n",
3087 __func__));
3088 return 0;
3089 }
3090
3091 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp,
3092 tdbp, nip, if_flagsp)) != NULL) {
3093 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue mgt frame\n",
3094 __func__));
3095 return 0;
3096 }
3097
3098 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) {
3099 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: not running\n", __func__));
3100 return 0;
3101 }
3102
3103 IFQ_POLL(&ifp->if_snd, m0);
3104 if (m0 == NULL) {
3105 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n",
3106 __func__));
3107 return 0;
3108 }
3109
3110 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD;
3111
3112 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
3113 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC, ("%s: no ring %d descriptor\n",
3114 __func__, pri));
3115 *if_flagsp |= IFF_OACTIVE;
3116 sc->sc_if.if_timer = 1;
3117 return 0;
3118 }
3119
3120 IFQ_DEQUEUE(&ifp->if_snd, m0);
3121 if (m0 == NULL) {
3122 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: no frame ready\n",
3123 __func__));
3124 return 0;
3125 }
3126 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: dequeue data frame\n", __func__));
3127 ifp->if_opackets++;
3128 #if NBPFILTER > 0
3129 if (ifp->if_bpf)
3130 bpf_mtap(ifp->if_bpf, m0);
3131 #endif
3132 eh = mtod(m0, struct ether_header *);
3133 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost);
3134 if (*nip == NULL) {
3135 /* NB: ieee80211_find_txnode does stat+msg */
3136 m_freem(m0);
3137 return -1;
3138 }
3139 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) {
3140 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: encap error\n", __func__));
3141 ifp->if_oerrors++;
3142 return -1;
3143 }
3144 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__));
3145 *mp = m0;
3146 return 0;
3147 }
3148
3149 static int
3150 rtw_seg_too_short(bus_dmamap_t dmamap)
3151 {
3152 int i;
3153 for (i = 0; i < dmamap->dm_nsegs; i++) {
3154 if (dmamap->dm_segs[i].ds_len < 4)
3155 return 1;
3156 }
3157 return 0;
3158 }
3159
3160 /* TBD factor with atw_start */
3161 static struct mbuf *
3162 rtw_dmamap_load_txbuf(bus_dma_tag_t dmat, bus_dmamap_t dmam, struct mbuf *chain,
3163 u_int ndescfree, device_t dev)
3164 {
3165 int first, rc;
3166 struct mbuf *m, *m0;
3167
3168 m0 = chain;
3169
3170 /*
3171 * Load the DMA map. Copy and try (once) again if the packet
3172 * didn't fit in the alloted number of segments.
3173 */
3174 for (first = 1;
3175 ((rc = bus_dmamap_load_mbuf(dmat, dmam, m0,
3176 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 ||
3177 dmam->dm_nsegs > ndescfree || rtw_seg_too_short(dmam)) && first;
3178 first = 0) {
3179 if (rc == 0) {
3180 #ifdef RTW_DIAGxxx
3181 if (rtw_seg_too_short(dmam)) {
3182 printf("%s: short segment, mbuf lengths:", __func__);
3183 for (m = m0; m; m = m->m_next)
3184 printf(" %d", m->m_len);
3185 printf("\n");
3186 }
3187 #endif
3188 bus_dmamap_unload(dmat, dmam);
3189 }
3190 MGETHDR(m, M_DONTWAIT, MT_DATA);
3191 if (m == NULL) {
3192 aprint_error_dev(dev, "unable to allocate Tx mbuf\n");
3193 break;
3194 }
3195 if (m0->m_pkthdr.len > MHLEN) {
3196 MCLGET(m, M_DONTWAIT);
3197 if ((m->m_flags & M_EXT) == 0) {
3198 aprint_error_dev(dev,
3199 "cannot allocate Tx cluster\n");
3200 m_freem(m);
3201 break;
3202 }
3203 }
3204 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
3205 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
3206 m_freem(m0);
3207 m0 = m;
3208 m = NULL;
3209 }
3210 if (rc != 0) {
3211 aprint_error_dev(dev, "cannot load Tx buffer, rc = %d\n", rc);
3212 m_freem(m0);
3213 return NULL;
3214 } else if (rtw_seg_too_short(dmam)) {
3215 aprint_error_dev(dev,
3216 "cannot load Tx buffer, segment too short\n");
3217 bus_dmamap_unload(dmat, dmam);
3218 m_freem(m0);
3219 return NULL;
3220 } else if (dmam->dm_nsegs > ndescfree) {
3221 aprint_error_dev(dev, "too many tx segments\n");
3222 bus_dmamap_unload(dmat, dmam);
3223 m_freem(m0);
3224 return NULL;
3225 }
3226 return m0;
3227 }
3228
3229 #ifdef RTW_DEBUG
3230 static void
3231 rtw_print_txdesc(struct rtw_softc *sc, const char *action,
3232 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc)
3233 {
3234 struct rtw_txdesc *td = &tdb->tdb_desc[desc];
3235 DPRINTF(sc, RTW_DEBUG_XMIT_DESC, ("%s: %p %s txdesc[%d] next %#08x "
3236 "buf %#08x ctl0 %#08x ctl1 %#08x len %#08x\n",
3237 device_xname(sc->sc_dev), ts, action, desc,
3238 le32toh(td->td_buf), le32toh(td->td_next),
3239 le32toh(td->td_ctl0), le32toh(td->td_ctl1),
3240 le32toh(td->td_len)));
3241 }
3242 #endif /* RTW_DEBUG */
3243
3244 static void
3245 rtw_start(struct ifnet *ifp)
3246 {
3247 int desc, i, lastdesc, npkt, rate;
3248 uint32_t proto_ctl0, ctl0, ctl1;
3249 bus_dmamap_t dmamap;
3250 struct ieee80211com *ic;
3251 struct ieee80211_duration *d0;
3252 struct ieee80211_frame_min *wh;
3253 struct ieee80211_node *ni = NULL; /* XXX: GCC */
3254 struct mbuf *m0;
3255 struct rtw_softc *sc;
3256 struct rtw_txsoft_blk *tsb = NULL; /* XXX: GCC */
3257 struct rtw_txdesc_blk *tdb = NULL; /* XXX: GCC */
3258 struct rtw_txsoft *ts;
3259 struct rtw_txdesc *td;
3260 struct ieee80211_key *k;
3261
3262 sc = (struct rtw_softc *)ifp->if_softc;
3263 ic = &sc->sc_ic;
3264
3265 DPRINTF(sc, RTW_DEBUG_XMIT,
3266 ("%s: enter %s\n", device_xname(sc->sc_dev), __func__));
3267
3268 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3269 goto out;
3270
3271 /* XXX do real rate control */
3272 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS;
3273
3274 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0)
3275 proto_ctl0 |= RTW_TXCTL0_SPLCP;
3276
3277 for (;;) {
3278 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1)
3279 continue;
3280 if (m0 == NULL)
3281 break;
3282
3283 wh = mtod(m0, struct ieee80211_frame_min *);
3284
3285 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 &&
3286 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3287 m_freem(m0);
3288 break;
3289 } else
3290 k = NULL;
3291
3292 ts = SIMPLEQ_FIRST(&tsb->tsb_freeq);
3293
3294 dmamap = ts->ts_dmamap;
3295
3296 m0 = rtw_dmamap_load_txbuf(sc->sc_dmat, dmamap, m0,
3297 tdb->tdb_nfree, sc->sc_dev);
3298
3299 if (m0 == NULL || dmamap->dm_nsegs == 0) {
3300 DPRINTF(sc, RTW_DEBUG_XMIT,
3301 ("%s: fail dmamap load\n", __func__));
3302 goto post_dequeue_err;
3303 }
3304
3305 /* Note well: rtw_dmamap_load_txbuf may have created
3306 * a new chain, so we must find the header once
3307 * more.
3308 */
3309 wh = mtod(m0, struct ieee80211_frame_min *);
3310
3311 /* XXX do real rate control */
3312 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3313 IEEE80211_FC0_TYPE_MGT)
3314 rate = 2;
3315 else
3316 rate = MAX(2, ieee80211_get_rate(ni));
3317
3318 #ifdef RTW_DEBUG
3319 if ((ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3320 (IFF_DEBUG|IFF_LINK2)) {
3321 ieee80211_dump_pkt(mtod(m0, uint8_t *),
3322 (dmamap->dm_nsegs == 1) ? m0->m_pkthdr.len
3323 : sizeof(wh),
3324 rate, 0);
3325 }
3326 #endif /* RTW_DEBUG */
3327 ctl0 = proto_ctl0 |
3328 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
3329
3330 switch (rate) {
3331 default:
3332 case 2:
3333 ctl0 |= RTW_TXCTL0_RATE_1MBPS;
3334 break;
3335 case 4:
3336 ctl0 |= RTW_TXCTL0_RATE_2MBPS;
3337 break;
3338 case 11:
3339 ctl0 |= RTW_TXCTL0_RATE_5MBPS;
3340 break;
3341 case 22:
3342 ctl0 |= RTW_TXCTL0_RATE_11MBPS;
3343 break;
3344 }
3345 /* XXX >= ? Compare after fragmentation? */
3346 if (m0->m_pkthdr.len > ic->ic_rtsthreshold)
3347 ctl0 |= RTW_TXCTL0_RTSEN;
3348
3349 /* XXX Sometimes writes a bogus keyid; h/w doesn't
3350 * seem to care, since we don't activate h/w Tx
3351 * encryption.
3352 */
3353 if (k != NULL &&
3354 k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) {
3355 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &
3356 RTW_TXCTL0_KEYID_MASK;
3357 }
3358
3359 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3360 IEEE80211_FC0_TYPE_MGT) {
3361 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
3362 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3363 IEEE80211_FC0_SUBTYPE_BEACON)
3364 ctl0 |= RTW_TXCTL0_BEACON;
3365 }
3366
3367 if (ieee80211_compute_duration(wh, k, m0->m_pkthdr.len,
3368 ic->ic_flags, ic->ic_fragthreshold,
3369 rate, &ts->ts_d0, &ts->ts_dn, &npkt,
3370 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3371 (IFF_DEBUG|IFF_LINK2)) == -1) {
3372 DPRINTF(sc, RTW_DEBUG_XMIT,
3373 ("%s: fail compute duration\n", __func__));
3374 goto post_load_err;
3375 }
3376
3377 d0 = &ts->ts_d0;
3378
3379 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur);
3380
3381 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
3382 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
3383
3384 if (d0->d_residue)
3385 ctl1 |= RTW_TXCTL1_LENGEXT;
3386
3387 /* TBD fragmentation */
3388
3389 ts->ts_first = tdb->tdb_next;
3390
3391 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs,
3392 BUS_DMASYNC_PREWRITE);
3393
3394 KASSERT(ts->ts_first < tdb->tdb_ndesc);
3395
3396 #if NBPFILTER > 0
3397 if (ic->ic_rawbpf != NULL)
3398 bpf_mtap((void *)ic->ic_rawbpf, m0);
3399
3400 if (sc->sc_radiobpf != NULL) {
3401 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
3402
3403 rt->rt_rate = rate;
3404
3405 bpf_mtap2(sc->sc_radiobpf, (void *)rt,
3406 sizeof(sc->sc_txtapu), m0);
3407 }
3408 #endif /* NBPFILTER > 0 */
3409
3410 for (i = 0, lastdesc = desc = ts->ts_first;
3411 i < dmamap->dm_nsegs;
3412 i++, desc = RTW_NEXT_IDX(tdb, desc)) {
3413 if (dmamap->dm_segs[i].ds_len > RTW_TXLEN_LENGTH_MASK) {
3414 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
3415 ("%s: seg too long\n", __func__));
3416 goto post_load_err;
3417 }
3418 td = &tdb->tdb_desc[desc];
3419 td->td_ctl0 = htole32(ctl0);
3420 td->td_ctl1 = htole32(ctl1);
3421 td->td_buf = htole32(dmamap->dm_segs[i].ds_addr);
3422 td->td_len = htole32(dmamap->dm_segs[i].ds_len);
3423 td->td_next = htole32(RTW_NEXT_DESC(tdb, desc));
3424 if (i != 0)
3425 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3426 lastdesc = desc;
3427 #ifdef RTW_DEBUG
3428 rtw_print_txdesc(sc, "load", ts, tdb, desc);
3429 #endif /* RTW_DEBUG */
3430 }
3431
3432 KASSERT(desc < tdb->tdb_ndesc);
3433
3434 ts->ts_ni = ni;
3435 KASSERT(ni != NULL);
3436 ts->ts_mbuf = m0;
3437 ts->ts_last = lastdesc;
3438 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS);
3439 tdb->tdb_desc[ts->ts_first].td_ctl0 |=
3440 htole32(RTW_TXCTL0_FS);
3441
3442 #ifdef RTW_DEBUG
3443 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first);
3444 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last);
3445 #endif /* RTW_DEBUG */
3446
3447 tdb->tdb_nfree -= dmamap->dm_nsegs;
3448 tdb->tdb_next = desc;
3449
3450 rtw_txdescs_sync(tdb, ts->ts_first, dmamap->dm_nsegs,
3451 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3452
3453 tdb->tdb_desc[ts->ts_first].td_ctl0 |=
3454 htole32(RTW_TXCTL0_OWN);
3455
3456 #ifdef RTW_DEBUG
3457 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first);
3458 #endif /* RTW_DEBUG */
3459
3460 rtw_txdescs_sync(tdb, ts->ts_first, 1,
3461 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3462
3463 SIMPLEQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q);
3464 SIMPLEQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q);
3465
3466 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN])
3467 sc->sc_led_state.ls_event |= RTW_LED_S_TX;
3468 tsb->tsb_tx_timer = 5;
3469 ifp->if_timer = 1;
3470 rtw_tx_kick(&sc->sc_regs, tsb->tsb_poll);
3471 }
3472 out:
3473 DPRINTF(sc, RTW_DEBUG_XMIT, ("%s: leave\n", __func__));
3474 return;
3475 post_load_err:
3476 bus_dmamap_unload(sc->sc_dmat, dmamap);
3477 m_freem(m0);
3478 post_dequeue_err:
3479 ieee80211_free_node(ni);
3480 return;
3481 }
3482
3483 static void
3484 rtw_idle(struct rtw_regs *regs)
3485 {
3486 int active;
3487 uint8_t tppoll;
3488
3489 /* request stop DMA; wait for packets to stop transmitting. */
3490
3491 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
3492 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
3493
3494 for (active = 0; active < 300 &&
3495 (tppoll = RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0;
3496 active++)
3497 DELAY(10);
3498 printf("%s: transmit DMA idle in %dus, tppoll %02" PRIx8 "\n", __func__,
3499 active * 10, tppoll);
3500 }
3501
3502 static void
3503 rtw_watchdog(struct ifnet *ifp)
3504 {
3505 int pri, tx_timeouts = 0;
3506 struct rtw_softc *sc;
3507 struct rtw_txsoft_blk *tsb;
3508
3509 sc = ifp->if_softc;
3510
3511 ifp->if_timer = 0;
3512
3513 if (!device_is_active(sc->sc_dev))
3514 return;
3515
3516 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3517 tsb = &sc->sc_txsoft_blk[pri];
3518
3519 if (tsb->tsb_tx_timer == 0)
3520 continue;
3521 else if (--tsb->tsb_tx_timer == 0) {
3522 if (SIMPLEQ_EMPTY(&tsb->tsb_dirtyq))
3523 continue;
3524 else if (rtw_collect_txring(sc, tsb,
3525 &sc->sc_txdesc_blk[pri], 0))
3526 continue;
3527 printf("%s: transmit timeout, priority %d\n",
3528 ifp->if_xname, pri);
3529 ifp->if_oerrors++;
3530 if (pri != RTW_TXPRIBCN)
3531 tx_timeouts++;
3532 } else
3533 ifp->if_timer = 1;
3534 }
3535
3536 if (tx_timeouts > 0) {
3537 /* Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr,
3538 * reset s/w tx-ring pointers, and start transmission.
3539 *
3540 * TBD Stop/restart just the broken rings?
3541 */
3542 rtw_idle(&sc->sc_regs);
3543 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
3544 rtw_txdescs_reset(sc);
3545 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3546 rtw_start(ifp);
3547 }
3548 ieee80211_watchdog(&sc->sc_ic);
3549 return;
3550 }
3551
3552 static void
3553 rtw_next_scan(void *arg)
3554 {
3555 struct ieee80211com *ic = arg;
3556 int s;
3557
3558 /* don't call rtw_start w/o network interrupts blocked */
3559 s = splnet();
3560 if (ic->ic_state == IEEE80211_S_SCAN)
3561 ieee80211_next_scan(ic);
3562 splx(s);
3563 }
3564
3565 static void
3566 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0)
3567 {
3568 uint16_t bcnitv, bintritv, intval;
3569 int i;
3570 struct rtw_regs *regs = &sc->sc_regs;
3571
3572 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3573 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
3574
3575 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
3576
3577 rtw_set_access(regs, RTW_ACCESS_CONFIG);
3578
3579 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK));
3580
3581 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
3582 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);
3583 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
3584 /* interrupt host 1ms before the TBTT */
3585 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
3586 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV);
3587 RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
3588 /* magic from Linux */
3589 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND));
3590 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));
3591 rtw_set_access(regs, RTW_ACCESS_NONE);
3592
3593 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3594 }
3595
3596 /* Synchronize the hardware state with the software state. */
3597 static int
3598 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3599 {
3600 struct ifnet *ifp = ic->ic_ifp;
3601 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3602 enum ieee80211_state ostate;
3603 int error;
3604
3605 ostate = ic->ic_state;
3606
3607 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__);
3608 rtw_led_newstate(sc, nstate);
3609
3610 aprint_debug_dev(sc->sc_dev, "%s: l.%d\n", __func__, __LINE__);
3611 if (nstate == IEEE80211_S_INIT) {
3612 callout_stop(&sc->sc_scan_ch);
3613 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
3614 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg);
3615 }
3616
3617 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT)
3618 rtw_pwrstate(sc, RTW_ON);
3619
3620 if ((error = rtw_tune(sc)) != 0)
3621 return error;
3622
3623 switch (nstate) {
3624 case IEEE80211_S_INIT:
3625 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__);
3626 break;
3627 case IEEE80211_S_SCAN:
3628 if (ostate != IEEE80211_S_SCAN) {
3629 (void)memset(ic->ic_bss->ni_bssid, 0,
3630 IEEE80211_ADDR_LEN);
3631 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3632 }
3633
3634 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000,
3635 rtw_next_scan, ic);
3636
3637 break;
3638 case IEEE80211_S_RUN:
3639 switch (ic->ic_opmode) {
3640 case IEEE80211_M_HOSTAP:
3641 case IEEE80211_M_IBSS:
3642 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3643 /*FALLTHROUGH*/
3644 case IEEE80211_M_AHDEMO:
3645 case IEEE80211_M_STA:
3646 rtw_join_bss(sc, ic->ic_bss->ni_bssid,
3647 ic->ic_bss->ni_intval);
3648 break;
3649 case IEEE80211_M_MONITOR:
3650 break;
3651 }
3652 rtw_set_nettype(sc, ic->ic_opmode);
3653 break;
3654 case IEEE80211_S_ASSOC:
3655 case IEEE80211_S_AUTH:
3656 break;
3657 }
3658
3659 if (nstate != IEEE80211_S_SCAN)
3660 callout_stop(&sc->sc_scan_ch);
3661
3662 return (*sc->sc_mtbl.mt_newstate)(ic, nstate, arg);
3663 }
3664
3665 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */
3666 static uint64_t
3667 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp)
3668 {
3669 uint32_t tsftl, tsfth;
3670
3671 tsfth = RTW_READ(regs, RTW_TSFTRH);
3672 tsftl = RTW_READ(regs, RTW_TSFTRL);
3673 if (tsftl < rstamp) /* Compensate for rollover. */
3674 tsfth--;
3675 return ((uint64_t)tsfth << 32) | rstamp;
3676 }
3677
3678 static void
3679 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
3680 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
3681 {
3682 struct ifnet *ifp = ic->ic_ifp;
3683 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3684
3685 (*sc->sc_mtbl.mt_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp);
3686
3687 switch (subtype) {
3688 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3689 case IEEE80211_FC0_SUBTYPE_BEACON:
3690 if (ic->ic_opmode == IEEE80211_M_IBSS &&
3691 ic->ic_state == IEEE80211_S_RUN &&
3692 device_is_active(sc->sc_dev)) {
3693 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp);
3694 if (le64toh(ni->ni_tstamp.tsf) >= tsf)
3695 (void)ieee80211_ibss_merge(ni);
3696 }
3697 break;
3698 default:
3699 break;
3700 }
3701 return;
3702 }
3703
3704 static struct ieee80211_node *
3705 rtw_node_alloc(struct ieee80211_node_table *nt)
3706 {
3707 struct ifnet *ifp = nt->nt_ic->ic_ifp;
3708 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3709 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt);
3710
3711 DPRINTF(sc, RTW_DEBUG_NODE,
3712 ("%s: alloc node %p\n", device_xname(sc->sc_dev), ni));
3713 return ni;
3714 }
3715
3716 static void
3717 rtw_node_free(struct ieee80211_node *ni)
3718 {
3719 struct ieee80211com *ic = ni->ni_ic;
3720 struct ifnet *ifp = ic->ic_ifp;
3721 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3722
3723 DPRINTF(sc, RTW_DEBUG_NODE,
3724 ("%s: freeing node %p %s\n", device_xname(sc->sc_dev), ni,
3725 ether_sprintf(ni->ni_bssid)));
3726 (*sc->sc_mtbl.mt_node_free)(ni);
3727 }
3728
3729 static int
3730 rtw_media_change(struct ifnet *ifp)
3731 {
3732 int error;
3733
3734 error = ieee80211_media_change(ifp);
3735 if (error == ENETRESET) {
3736 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
3737 (IFF_RUNNING|IFF_UP))
3738 rtw_init(ifp); /* XXX lose error */
3739 error = 0;
3740 }
3741 return error;
3742 }
3743
3744 static void
3745 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
3746 {
3747 struct rtw_softc *sc = ifp->if_softc;
3748
3749 if (!device_is_active(sc->sc_dev)) {
3750 imr->ifm_active = IFM_IEEE80211 | IFM_NONE;
3751 imr->ifm_status = 0;
3752 return;
3753 }
3754 ieee80211_media_status(ifp, imr);
3755 }
3756
3757 static inline void
3758 rtw_setifprops(struct ifnet *ifp, const char *dvname, void *softc)
3759 {
3760 (void)strlcpy(ifp->if_xname, dvname, IFNAMSIZ);
3761 ifp->if_softc = softc;
3762 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST |
3763 IFF_NOTRAILERS;
3764 ifp->if_ioctl = rtw_ioctl;
3765 ifp->if_start = rtw_start;
3766 ifp->if_watchdog = rtw_watchdog;
3767 ifp->if_init = rtw_init;
3768 ifp->if_stop = rtw_stop;
3769 }
3770
3771 static inline void
3772 rtw_set80211props(struct ieee80211com *ic)
3773 {
3774 int nrate;
3775 ic->ic_phytype = IEEE80211_T_DS;
3776 ic->ic_opmode = IEEE80211_M_STA;
3777 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS |
3778 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR | IEEE80211_C_WEP;
3779
3780 nrate = 0;
3781 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] =
3782 IEEE80211_RATE_BASIC | 2;
3783 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] =
3784 IEEE80211_RATE_BASIC | 4;
3785 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11;
3786 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22;
3787 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate;
3788 }
3789
3790 static inline void
3791 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic)
3792 {
3793 mtbl->mt_newstate = ic->ic_newstate;
3794 ic->ic_newstate = rtw_newstate;
3795
3796 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt;
3797 ic->ic_recv_mgmt = rtw_recv_mgmt;
3798
3799 mtbl->mt_node_free = ic->ic_node_free;
3800 ic->ic_node_free = rtw_node_free;
3801
3802 mtbl->mt_node_alloc = ic->ic_node_alloc;
3803 ic->ic_node_alloc = rtw_node_alloc;
3804
3805 ic->ic_crypto.cs_key_delete = rtw_key_delete;
3806 ic->ic_crypto.cs_key_set = rtw_key_set;
3807 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin;
3808 ic->ic_crypto.cs_key_update_end = rtw_key_update_end;
3809 }
3810
3811 static inline void
3812 rtw_init_radiotap(struct rtw_softc *sc)
3813 {
3814 uint32_t present;
3815
3816 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu));
3817 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
3818
3819 if (sc->sc_rfchipid == RTW_RFCHIPID_PHILIPS)
3820 present = htole32(RTW_PHILIPS_RX_RADIOTAP_PRESENT);
3821 else
3822 present = htole32(RTW_RX_RADIOTAP_PRESENT);
3823 sc->sc_rxtap.rr_ihdr.it_present = present;
3824
3825 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu));
3826 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
3827 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT);
3828 }
3829
3830 static int
3831 rtw_txsoft_blk_setup(struct rtw_txsoft_blk *tsb, u_int qlen)
3832 {
3833 SIMPLEQ_INIT(&tsb->tsb_dirtyq);
3834 SIMPLEQ_INIT(&tsb->tsb_freeq);
3835 tsb->tsb_ndesc = qlen;
3836 tsb->tsb_desc = malloc(qlen * sizeof(*tsb->tsb_desc), M_DEVBUF,
3837 M_NOWAIT);
3838 if (tsb->tsb_desc == NULL)
3839 return ENOMEM;
3840 return 0;
3841 }
3842
3843 static void
3844 rtw_txsoft_blk_cleanup_all(struct rtw_softc *sc)
3845 {
3846 int pri;
3847 struct rtw_txsoft_blk *tsb;
3848
3849 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3850 tsb = &sc->sc_txsoft_blk[pri];
3851 free(tsb->tsb_desc, M_DEVBUF);
3852 tsb->tsb_desc = NULL;
3853 }
3854 }
3855
3856 static int
3857 rtw_txsoft_blk_setup_all(struct rtw_softc *sc)
3858 {
3859 int pri, rc = 0;
3860 int qlen[RTW_NTXPRI] =
3861 {RTW_TXQLENLO, RTW_TXQLENMD, RTW_TXQLENHI, RTW_TXQLENBCN};
3862 struct rtw_txsoft_blk *tsbs;
3863
3864 tsbs = sc->sc_txsoft_blk;
3865
3866 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3867 rc = rtw_txsoft_blk_setup(&tsbs[pri], qlen[pri]);
3868 if (rc != 0)
3869 break;
3870 }
3871 tsbs[RTW_TXPRILO].tsb_poll = RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ;
3872 tsbs[RTW_TXPRIMD].tsb_poll = RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ;
3873 tsbs[RTW_TXPRIHI].tsb_poll = RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ;
3874 tsbs[RTW_TXPRIBCN].tsb_poll = RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ;
3875 return rc;
3876 }
3877
3878 static void
3879 rtw_txdesc_blk_setup(struct rtw_txdesc_blk *tdb, struct rtw_txdesc *desc,
3880 u_int ndesc, bus_addr_t ofs, bus_addr_t physbase)
3881 {
3882 tdb->tdb_ndesc = ndesc;
3883 tdb->tdb_desc = desc;
3884 tdb->tdb_physbase = physbase;
3885 tdb->tdb_ofs = ofs;
3886
3887 (void)memset(tdb->tdb_desc, 0,
3888 sizeof(tdb->tdb_desc[0]) * tdb->tdb_ndesc);
3889
3890 rtw_txdesc_blk_init(tdb);
3891 tdb->tdb_next = 0;
3892 }
3893
3894 static void
3895 rtw_txdesc_blk_setup_all(struct rtw_softc *sc)
3896 {
3897 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRILO],
3898 &sc->sc_descs->hd_txlo[0], RTW_NTXDESCLO,
3899 RTW_RING_OFFSET(hd_txlo), RTW_RING_BASE(sc, hd_txlo));
3900
3901 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIMD],
3902 &sc->sc_descs->hd_txmd[0], RTW_NTXDESCMD,
3903 RTW_RING_OFFSET(hd_txmd), RTW_RING_BASE(sc, hd_txmd));
3904
3905 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIHI],
3906 &sc->sc_descs->hd_txhi[0], RTW_NTXDESCHI,
3907 RTW_RING_OFFSET(hd_txhi), RTW_RING_BASE(sc, hd_txhi));
3908
3909 rtw_txdesc_blk_setup(&sc->sc_txdesc_blk[RTW_TXPRIBCN],
3910 &sc->sc_descs->hd_bcn[0], RTW_NTXDESCBCN,
3911 RTW_RING_OFFSET(hd_bcn), RTW_RING_BASE(sc, hd_bcn));
3912 }
3913
3914 static struct rtw_rf *
3915 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy)
3916 {
3917 rtw_rf_write_t rf_write;
3918 struct rtw_rf *rf;
3919
3920 switch (rfchipid) {
3921 default:
3922 rf_write = rtw_rf_hostwrite;
3923 break;
3924 case RTW_RFCHIPID_INTERSIL:
3925 case RTW_RFCHIPID_PHILIPS:
3926 case RTW_RFCHIPID_GCT: /* XXX a guess */
3927 case RTW_RFCHIPID_RFMD:
3928 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite;
3929 break;
3930 }
3931
3932 switch (rfchipid) {
3933 case RTW_RFCHIPID_GCT:
3934 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0);
3935 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3936 break;
3937 case RTW_RFCHIPID_MAXIM:
3938 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0);
3939 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3940 break;
3941 case RTW_RFCHIPID_PHILIPS:
3942 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy);
3943 sc->sc_pwrstate_cb = rtw_philips_pwrstate;
3944 break;
3945 case RTW_RFCHIPID_RFMD:
3946 /* XXX RFMD has no RF constructor */
3947 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate;
3948 /*FALLTHROUGH*/
3949 default:
3950 return NULL;
3951 }
3952 rf->rf_continuous_tx_cb =
3953 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable;
3954 rf->rf_continuous_tx_arg = (void *)sc;
3955 return rf;
3956 }
3957
3958 /* Revision C and later use a different PHY delay setting than
3959 * revisions A and B.
3960 */
3961 static uint8_t
3962 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr)
3963 {
3964 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV)
3965 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE)
3966
3967 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);
3968
3969 RTW_WRITE(regs, RTW_RCR, REVAB);
3970 RTW_WBW(regs, RTW_RCR, RTW_RCR);
3971 RTW_WRITE(regs, RTW_RCR, REVC);
3972
3973 RTW_WBR(regs, RTW_RCR, RTW_RCR);
3974 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
3975 phydelay |= RTW_PHYDELAY_REVC_MAGIC;
3976
3977 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
3978 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
3979
3980 return phydelay;
3981 #undef REVC
3982 }
3983
3984 void
3985 rtw_attach(struct rtw_softc *sc)
3986 {
3987 struct ifnet *ifp = &sc->sc_if;
3988 struct ieee80211com *ic = &sc->sc_ic;
3989 struct rtw_txsoft_blk *tsb;
3990 int pri, rc;
3991
3992 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual);
3993
3994 rtw_cipher_wep = ieee80211_cipher_wep;
3995 rtw_cipher_wep.ic_decap = rtw_wep_decap;
3996
3997 NEXT_ATTACH_STATE(sc, DETACHED);
3998
3999 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
4000 case RTW_TCR_HWVERID_F:
4001 sc->sc_hwverid = 'F';
4002 break;
4003 case RTW_TCR_HWVERID_D:
4004 sc->sc_hwverid = 'D';
4005 break;
4006 default:
4007 sc->sc_hwverid = '?';
4008 break;
4009 }
4010 aprint_verbose_dev(sc->sc_dev, "hardware version %c\n",
4011 sc->sc_hwverid);
4012
4013 rc = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct rtw_descs),
4014 RTW_DESC_ALIGNMENT, 0, &sc->sc_desc_segs, 1, &sc->sc_desc_nsegs,
4015 0);
4016
4017 if (rc != 0) {
4018 aprint_error_dev(sc->sc_dev,
4019 "could not allocate hw descriptors, error %d\n", rc);
4020 goto err;
4021 }
4022
4023 NEXT_ATTACH_STATE(sc, FINISH_DESC_ALLOC);
4024
4025 rc = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_segs,
4026 sc->sc_desc_nsegs, sizeof(struct rtw_descs),
4027 (void **)&sc->sc_descs, BUS_DMA_COHERENT);
4028
4029 if (rc != 0) {
4030 aprint_error_dev(sc->sc_dev,
4031 "could not map hw descriptors, error %d\n", rc);
4032 goto err;
4033 }
4034 NEXT_ATTACH_STATE(sc, FINISH_DESC_MAP);
4035
4036 rc = bus_dmamap_create(sc->sc_dmat, sizeof(struct rtw_descs), 1,
4037 sizeof(struct rtw_descs), 0, 0, &sc->sc_desc_dmamap);
4038
4039 if (rc != 0) {
4040 aprint_error_dev(sc->sc_dev,
4041 "could not create DMA map for hw descriptors, error %d\n",
4042 rc);
4043 goto err;
4044 }
4045 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_CREATE);
4046
4047 sc->sc_rxdesc_blk.rdb_dmat = sc->sc_dmat;
4048 sc->sc_rxdesc_blk.rdb_dmamap = sc->sc_desc_dmamap;
4049
4050 for (pri = 0; pri < RTW_NTXPRI; pri++) {
4051 sc->sc_txdesc_blk[pri].tdb_dmat = sc->sc_dmat;
4052 sc->sc_txdesc_blk[pri].tdb_dmamap = sc->sc_desc_dmamap;
4053 }
4054
4055 rc = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_dmamap, sc->sc_descs,
4056 sizeof(struct rtw_descs), NULL, 0);
4057
4058 if (rc != 0) {
4059 aprint_error_dev(sc->sc_dev,
4060 "could not load DMA map for hw descriptors, error %d\n",
4061 rc);
4062 goto err;
4063 }
4064 NEXT_ATTACH_STATE(sc, FINISH_DESCMAP_LOAD);
4065
4066 if (rtw_txsoft_blk_setup_all(sc) != 0)
4067 goto err;
4068 NEXT_ATTACH_STATE(sc, FINISH_TXCTLBLK_SETUP);
4069
4070 rtw_txdesc_blk_setup_all(sc);
4071
4072 NEXT_ATTACH_STATE(sc, FINISH_TXDESCBLK_SETUP);
4073
4074 sc->sc_rxdesc_blk.rdb_desc = &sc->sc_descs->hd_rx[0];
4075
4076 for (pri = 0; pri < RTW_NTXPRI; pri++) {
4077 tsb = &sc->sc_txsoft_blk[pri];
4078
4079 if ((rc = rtw_txdesc_dmamaps_create(sc->sc_dmat,
4080 &tsb->tsb_desc[0], tsb->tsb_ndesc)) != 0) {
4081 aprint_error_dev(sc->sc_dev,
4082 "could not load DMA map for hw tx descriptors, "
4083 "error %d\n", rc);
4084 goto err;
4085 }
4086 }
4087
4088 NEXT_ATTACH_STATE(sc, FINISH_TXMAPS_CREATE);
4089 if ((rc = rtw_rxdesc_dmamaps_create(sc->sc_dmat, &sc->sc_rxsoft[0],
4090 RTW_RXQLEN)) != 0) {
4091 aprint_error_dev(sc->sc_dev,
4092 "could not load DMA map for hw rx descriptors, error %d\n",
4093 rc);
4094 goto err;
4095 }
4096 NEXT_ATTACH_STATE(sc, FINISH_RXMAPS_CREATE);
4097
4098 /* Reset the chip to a known state. */
4099 if (rtw_reset(sc) != 0)
4100 goto err;
4101 NEXT_ATTACH_STATE(sc, FINISH_RESET);
4102
4103 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
4104
4105 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0)
4106 sc->sc_flags |= RTW_F_9356SROM;
4107
4108 if (rtw_srom_read(&sc->sc_regs, sc->sc_flags, &sc->sc_srom,
4109 sc->sc_dev) != 0)
4110 goto err;
4111
4112 NEXT_ATTACH_STATE(sc, FINISH_READ_SROM);
4113
4114 if (rtw_srom_parse(&sc->sc_srom, &sc->sc_flags, &sc->sc_csthr,
4115 &sc->sc_rfchipid, &sc->sc_rcr, &sc->sc_locale,
4116 sc->sc_dev) != 0) {
4117 aprint_error_dev(sc->sc_dev,
4118 "attach failed, malformed serial ROM\n");
4119 goto err;
4120 }
4121
4122 aprint_verbose_dev(sc->sc_dev, "%s PHY\n",
4123 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital" : "analog");
4124
4125 aprint_verbose_dev(sc->sc_dev, "carrier-sense threshold %u\n",
4126 sc->sc_csthr);
4127
4128 NEXT_ATTACH_STATE(sc, FINISH_PARSE_SROM);
4129
4130 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid,
4131 sc->sc_flags & RTW_F_DIGPHY);
4132
4133 if (sc->sc_rf == NULL) {
4134 aprint_verbose_dev(sc->sc_dev,
4135 "attach failed, could not attach RF\n");
4136 goto err;
4137 }
4138
4139 NEXT_ATTACH_STATE(sc, FINISH_RF_ATTACH);
4140
4141 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr);
4142
4143 RTW_DPRINTF(RTW_DEBUG_ATTACH,
4144 ("%s: PHY delay %d\n", device_xname(sc->sc_dev), sc->sc_phydelay));
4145
4146 if (sc->sc_locale == RTW_LOCALE_UNKNOWN)
4147 rtw_identify_country(&sc->sc_regs, &sc->sc_locale);
4148
4149 rtw_init_channels(sc->sc_locale, &sc->sc_ic.ic_channels, sc->sc_dev);
4150
4151 if (rtw_identify_sta(&sc->sc_regs, &sc->sc_ic.ic_myaddr,
4152 sc->sc_dev) != 0)
4153 goto err;
4154 NEXT_ATTACH_STATE(sc, FINISH_ID_STA);
4155
4156 rtw_setifprops(ifp, device_xname(sc->sc_dev), (void*)sc);
4157
4158 IFQ_SET_READY(&ifp->if_snd);
4159
4160 sc->sc_ic.ic_ifp = ifp;
4161 rtw_set80211props(&sc->sc_ic);
4162
4163 rtw_led_attach(&sc->sc_led_state, (void *)sc);
4164
4165 /*
4166 * Call MI attach routines.
4167 */
4168 if_attach(ifp);
4169 ieee80211_ifattach(&sc->sc_ic);
4170
4171 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic);
4172
4173 /* possibly we should fill in our own sc_send_prresp, since
4174 * the RTL8180 is probably sending probe responses in ad hoc
4175 * mode.
4176 */
4177
4178 /* complete initialization */
4179 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status);
4180 callout_init(&sc->sc_scan_ch, 0);
4181
4182 rtw_init_radiotap(sc);
4183
4184 #if NBPFILTER > 0
4185 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
4186 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
4187 #endif
4188
4189 NEXT_ATTACH_STATE(sc, FINISHED);
4190
4191 ieee80211_announce(ic);
4192 return;
4193 err:
4194 rtw_detach(sc);
4195 return;
4196 }
4197
4198 int
4199 rtw_detach(struct rtw_softc *sc)
4200 {
4201 struct ifnet *ifp = &sc->sc_if;
4202 int pri, s;
4203
4204 s = splnet();
4205
4206 switch (sc->sc_attach_state) {
4207 case FINISHED:
4208 rtw_stop(ifp, 1);
4209
4210 pmf_device_deregister(sc->sc_dev);
4211 callout_stop(&sc->sc_scan_ch);
4212 ieee80211_ifdetach(&sc->sc_ic);
4213 if_detach(ifp);
4214 rtw_led_detach(&sc->sc_led_state);
4215 /*FALLTHROUGH*/
4216 case FINISH_ID_STA:
4217 case FINISH_RF_ATTACH:
4218 rtw_rf_destroy(sc->sc_rf);
4219 sc->sc_rf = NULL;
4220 /*FALLTHROUGH*/
4221 case FINISH_PARSE_SROM:
4222 case FINISH_READ_SROM:
4223 rtw_srom_free(&sc->sc_srom);
4224 /*FALLTHROUGH*/
4225 case FINISH_RESET:
4226 case FINISH_RXMAPS_CREATE:
4227 rtw_rxdesc_dmamaps_destroy(sc->sc_dmat, &sc->sc_rxsoft[0],
4228 RTW_RXQLEN);
4229 /*FALLTHROUGH*/
4230 case FINISH_TXMAPS_CREATE:
4231 for (pri = 0; pri < RTW_NTXPRI; pri++) {
4232 rtw_txdesc_dmamaps_destroy(sc->sc_dmat,
4233 sc->sc_txsoft_blk[pri].tsb_desc,
4234 sc->sc_txsoft_blk[pri].tsb_ndesc);
4235 }
4236 /*FALLTHROUGH*/
4237 case FINISH_TXDESCBLK_SETUP:
4238 case FINISH_TXCTLBLK_SETUP:
4239 rtw_txsoft_blk_cleanup_all(sc);
4240 /*FALLTHROUGH*/
4241 case FINISH_DESCMAP_LOAD:
4242 bus_dmamap_unload(sc->sc_dmat, sc->sc_desc_dmamap);
4243 /*FALLTHROUGH*/
4244 case FINISH_DESCMAP_CREATE:
4245 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_dmamap);
4246 /*FALLTHROUGH*/
4247 case FINISH_DESC_MAP:
4248 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_descs,
4249 sizeof(struct rtw_descs));
4250 /*FALLTHROUGH*/
4251 case FINISH_DESC_ALLOC:
4252 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_segs,
4253 sc->sc_desc_nsegs);
4254 /*FALLTHROUGH*/
4255 case DETACHED:
4256 NEXT_ATTACH_STATE(sc, DETACHED);
4257 break;
4258 }
4259 splx(s);
4260 return 0;
4261 }
NetBSD on the FriendlyARM MINI2440