sys/dev/pci/agpreg.h

   1 /*      $NetBSD: agpreg.h,v 1.19 2008/03/11 13:36:14 joerg Exp $        */
   2
   3 /*-
   4  * Copyright (c) 2000 Doug Rabson
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  *      $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $
  29  */
  30
  31 #ifndef _PCI_AGPREG_H_
  32 #define _PCI_AGPREG_H_
  33
  34 /*
  35  * Offsets for various AGP configuration registers.
  36  */
  37 #define AGP_APBASE              0x10
  38
  39 #define AGP_STATUS              0x4
  40 #define AGP_COMMAND             0x8
  41
  42 /*
  43  * Config registers for Intel AGP chipsets.
  44  */
  45 /* i845/855PM */
  46 #define AGP_I845_AGPMISC        0x51
  47 # define AGPMISC_AAGN           (1U << 1)  /* Aperture AccessEN */
  48
  49 /* i840/850/850E */
  50 #define AGP_I840_MCHCFG         0x50
  51 # define MCHCFG_AAGN            (1U << 9)  /* Aperture AccessEN */
  52
  53 /* i82443LX/BX/GX */
  54 #define AGP_INTEL_NBXCFG        0x50
  55 # define NBXCFG_APAE            (1U << 10) /* AGPtoPCI AccessDIS */
  56 # define NBXCFG_AAGN            (1U << 9)  /* Aperture AccessEN */
  57
  58 /* Error Status for i8XX Chipset */
  59 #define AGP_INTEL_I8XX_ERRSTS   0xc8
  60
  61 /* Common register */
  62 #define AGP_INTEL_ERRSTS        0x90 /* bytes at 0x91 and 0x92, not i8XX */
  63 #define AGP_INTEL_AGPCMD        0xa8
  64 # define AGPCMD_SBA             (1U << 9)
  65 # define AGPCMD_AGPEN           (1U << 8)
  66 # define AGPCMD_FWEN            (1U << 4)
  67 # define AGPCMD_RATE_1X         (1U << 1)
  68 # define AGPCMD_RATE_2X         (1U << 2)
  69 # define AGPCMD_RATE_4X         (1U << 3)
  70
  71 #define AGP_INTEL_AGPCTRL       0xb0
  72 # define AGPCTRL_AGPRSE         (1U << 13) /* AGPRSE (82443 only)*/
  73 # define AGPCTRL_GTLB           (1U << 7)  /* GTLB EN */
  74
  75 #define AGP_INTEL_APSIZE        0xb4
  76 # define APSIZE_MASK            0x3f
  77
  78 #define AGP_INTEL_ATTBASE       0xb8
  79
  80 /*
  81  * Config offsets for VIA AGP 2.x chipsets.
  82  */
  83 #define AGP_VIA_GARTCTRL        0x80
  84 #define AGP_VIA_APSIZE          0x84
  85 #define AGP_VIA_ATTBASE         0x88
  86
  87 /*
  88  * Config offsets for VIA AGP 3.0 chipsets.
  89  */
  90 #define AGP3_VIA_GARTCTRL       0x90
  91 #define AGP3_VIA_APSIZE         0x94
  92 #define AGP3_VIA_ATTBASE        0x98
  93 #define AGP_VIA_AGPSEL          0xfc
  94
  95 /*
  96  * Config offsets for SiS AGP chipsets.
  97  */
  98 #define AGP_SIS_ATTBASE         0x90
  99 #define AGP_SIS_WINCTRL         0x94
 100 #define AGP_SIS_TLBCTRL         0x97
 101 #define AGP_SIS_TLBFLUSH        0x98
 102
 103 /*
 104  * Config offsets for Ali AGP chipsets.
 105  */
 106 #define AGP_ALI_AGPCTRL         0xb8
 107 #define AGP_ALI_ATTBASE         0xbc
 108 #define AGP_ALI_TLBCTRL         0xc0
 109
 110 /*
 111  * Config offsets for the AMD 751 chipset.
 112  */
 113 #define AGP_AMD751_REGISTERS    0x14
 114 #define AGP_AMD751_APCTRL       0xac
 115 #define AGP_AMD751_MODECTRL     0xb0
 116 #define AGP_AMD751_MODECTRL_SYNEN       0x80
 117 #define AGP_AMD751_MODECTRL2    0xb2
 118 #define AGP_AMD751_MODECTRL2_G1LM       0x01
 119 #define AGP_AMD751_MODECTRL2_GPDCE      0x02
 120 #define AGP_AMD751_MODECTRL2_NGSE       0x08
 121
 122 /*
 123  * Memory mapped register offsets for AMD 751 chipset.
 124  */
 125 #define AGP_AMD751_CAPS         0x00
 126 #define AGP_AMD751_CAPS_EHI             0x0800
 127 #define AGP_AMD751_CAPS_P2P             0x0400
 128 #define AGP_AMD751_CAPS_MPC             0x0200
 129 #define AGP_AMD751_CAPS_VBE             0x0100
 130 #define AGP_AMD751_CAPS_REV             0x00ff
 131 #define AGP_AMD751_STATUS       0x02
 132 #define AGP_AMD751_STATUS_P2PS          0x0800
 133 #define AGP_AMD751_STATUS_GCS           0x0400
 134 #define AGP_AMD751_STATUS_MPS           0x0200
 135 #define AGP_AMD751_STATUS_VBES          0x0100
 136 #define AGP_AMD751_STATUS_P2PE          0x0008
 137 #define AGP_AMD751_STATUS_GCE           0x0004
 138 #define AGP_AMD751_STATUS_VBEE          0x0001
 139 #define AGP_AMD751_ATTBASE      0x04
 140 #define AGP_AMD751_TLBCTRL      0x0c
 141
 142 /*
 143  * Config registers for i810 device 0
 144  */
 145 #define AGP_I810_SMRAM          0x70
 146 #define AGP_I810_SMRAM_GMS              0xc0
 147 #define AGP_I810_SMRAM_GMS_DISABLED     0x00
 148 #define AGP_I810_SMRAM_GMS_ENABLED_0    0x40
 149 #define AGP_I810_SMRAM_GMS_ENABLED_512  0x80
 150 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
 151 #define AGP_I810_MISCC          0x72
 152 #define AGP_I810_MISCC_WINSIZE          0x0001
 153 #define AGP_I810_MISCC_WINSIZE_64       0x0000
 154 #define AGP_I810_MISCC_WINSIZE_32       0x0001
 155 #define AGP_I810_MISCC_PLCK             0x0008
 156 #define AGP_I810_MISCC_PLCK_UNLOCKED    0x0000
 157 #define AGP_I810_MISCC_PLCK_LOCKED      0x0008
 158 #define AGP_I810_MISCC_WPTC             0x0030
 159 #define AGP_I810_MISCC_WPTC_NOLIMIT     0x0000
 160 #define AGP_I810_MISCC_WPTC_62          0x0010
 161 #define AGP_I810_MISCC_WPTC_50          0x0020
 162 #define AGP_I810_MISCC_WPTC_37          0x0030
 163 #define AGP_I810_MISCC_RPTC             0x00c0
 164 #define AGP_I810_MISCC_RPTC_NOLIMIT     0x0000
 165 #define AGP_I810_MISCC_RPTC_62          0x0040
 166 #define AGP_I810_MISCC_RPTC_50          0x0080
 167 #define AGP_I810_MISCC_RPTC_37          0x00c0
 168
 169 /*
 170  * Config registers for i810 device 1
 171  */
 172 #define AGP_I810_GMADR          0x10
 173 #define AGP_I810_MMADR          0x14
 174
 175 /*
 176  * Memory mapped register offsets for i810 chipset.
 177  */
 178 #define AGP_I810_PGTBL_CTL      0x2020
 179
 180 /**
 181  * This field determines the actual size of the global GTT on the 965
 182  * and G33
 183  */
 184 #define AGP_I810_PGTBL_SIZE_MASK        0x0000000e
 185 #define AGP_I810_PGTBL_SIZE_512KB       (0 << 1)
 186 #define AGP_I810_PGTBL_SIZE_256KB       (1 << 1)
 187 #define AGP_I810_PGTBL_SIZE_128KB       (2 << 1)
 188 #define AGP_I810_DRT                    0x3000
 189 #define AGP_I810_DRT_UNPOPULATED        0x00
 190 #define AGP_I810_DRT_POPULATED          0x01
 191 #define AGP_I810_GTT                    0x10000
 192
 193 /*
 194  * Config registers for i830MG device 0
 195  */
 196 #define AGP_I830_GCC0                   0x50
 197 #define AGP_I830_GCC1                   0x52
 198 #define AGP_I830_GCC1_DEV2              0x08
 199 #define AGP_I830_GCC1_DEV2_ENABLED      0x00
 200 #define AGP_I830_GCC1_DEV2_DISABLED     0x08
 201 #define AGP_I830_GCC1_GMS               0x70
 202 #define AGP_I830_GCC1_GMS_STOLEN_512    0x20
 203 #define AGP_I830_GCC1_GMS_STOLEN_1024   0x30
 204 #define AGP_I830_GCC1_GMS_STOLEN_8192   0x40
 205 #define AGP_I830_GCC1_GMASIZE           0x01
 206 #define AGP_I830_GCC1_GMASIZE_64        0x01
 207 #define AGP_I830_GCC1_GMASIZE_128       0x00
 208
 209
 210 /*
 211  * Config registers for 852GM/855GM/865G device 0
 212  */
 213 #define AGP_I855_GCC1                   0x50 /* upper word */
 214 #define AGP_I855_GCC1_DEV2              0x08
 215 #define AGP_I855_GCC1_DEV2_ENABLED      0x00
 216 #define AGP_I855_GCC1_DEV2_DISABLED     0x08
 217 #define AGP_I855_GCC1_GMS               0xf0    /* Top bit reserved pre-G33 */
 218 #define AGP_I855_GCC1_GMS_STOLEN_0M     0x00
 219 #define AGP_I855_GCC1_GMS_STOLEN_1M     0x10
 220 #define AGP_I855_GCC1_GMS_STOLEN_4M     0x20
 221 #define AGP_I855_GCC1_GMS_STOLEN_8M     0x30
 222 #define AGP_I855_GCC1_GMS_STOLEN_16M    0x40
 223 #define AGP_I855_GCC1_GMS_STOLEN_32M    0x50
 224
 225 /*
 226  * Config registers for 915G/915GM
 227  */
 228 #define AGP_I915_MMADR                  0x10
 229 #define AGP_I915_GMADR                  0x18
 230 #define AGP_I915_GTTADR                 0x1c
 231 #define AGP_I915_GCC1                   0x52
 232 #define AGP_I915_GCC1_GMS               0x70
 233 #define AGP_I915_GCC1_GMS_STOLEN_0M     0x00
 234 #define AGP_I915_GCC1_GMS_STOLEN_1M     0x10
 235 #define AGP_I915_GCC1_GMS_STOLEN_8M     0x30
 236 #define AGP_I915_GCC1_GMS_STOLEN_16M    0x40
 237 #define AGP_I915_GCC1_GMS_STOLEN_32M    0x50
 238 #define AGP_I915_GCC1_GMS_STOLEN_48M    0x60
 239 #define AGP_I915_GCC1_GMS_STOLEN_64M    0x70
 240 #define AGP_I915_MSAC                   0x60 /* upper word */
 241 #define AGP_I915_MSAC_APER_128M         0x02
 242
 243 /*
 244  * Config registers for 965G/965Q
 245  */
 246 #define AGP_I965_MMADR                  0x10
 247 #define AGP_I965_GMADR                  0x18
 248
 249 #define AGP_I965_GTT                    (512*1024)
 250
 251 #define AGP_I965_PGTBL_SIZE_1MB         (3 << 1)
 252 #define AGP_I965_PGTBL_SIZE_2MB         (4 << 1)
 253 #define AGP_I965_PGTBL_SIZE_1_5MB       (5 << 1)
 254
 255
 256 /*
 257  * Config registers for G33
 258  */
 259 #define AGP_G33_PGTBL_SIZE_MASK         (3U << 8)
 260 #define AGP_G33_PGTBL_SIZE_1M           (1U << 8)
 261 #define AGP_G33_PGTBL_SIZE_2M           (2U << 8)
 262
 263 #define AGP_G33_GCC1_GMS_STOLEN_128M    0x80
 264 #define AGP_G33_GCC1_GMS_STOLEN_256M    0x90
 265
 266 /*
 267  * Config registers for G4X
 268  */
 269 #define AGP_G4X_MSAC                    0x64 /* upper word */
 270 #define AGP_G4X_MSAC_MASK               0xff
 271 #define AGP_G4X_MSAC_APER_256M          0x02
 272 #define AGP_G4X_MSAC_APER_512M          0x04
 273
 274 #define AGP_G4X_GTT                     (2*1024*1024)
 275
 276 #define AGP_G4X_GCC1_GMS_STOLEN_96M     0xa0
 277 #define AGP_G4X_GCC1_GMS_STOLEN_160M    0xb0
 278 #define AGP_G4X_GCC1_GMS_STOLEN_224M    0xc0
 279 #define AGP_G4X_GCC1_GMS_STOLEN_352M    0xd0
 280
 281 /*
 282  * AMD64 GART registers
 283  */
 284 #define AGP_AMD64_APCTRL                0x90
 285 #define AGP_AMD64_APBASE                0x94
 286 #define AGP_AMD64_ATTBASE               0x98
 287 #define AGP_AMD64_CACHECTRL             0x9c
 288 #define AGP_AMD64_APCTRL_GARTEN         0x00000001
 289 #define AGP_AMD64_APCTRL_SIZE_MASK      0x0000000e
 290 #define AGP_AMD64_APCTRL_DISGARTCPU     0x00000010
 291 #define AGP_AMD64_APCTRL_DISGARTIO      0x00000020
 292 #define AGP_AMD64_APCTRL_DISWLKPRB      0x00000040
 293 #define AGP_AMD64_APBASE_MASK           0x00007fff
 294 #define AGP_AMD64_ATTBASE_MASK          0xfffffff0
 295 #define AGP_AMD64_CACHECTRL_INVGART     0x00000001
 296 #define AGP_AMD64_CACHECTRL_PTEERR      0x00000002
 297
 298 /*
 299  * NVIDIA nForce3 registers
 300  */
 301 #define AGP_AMD64_NVIDIA_0_APBASE       0x10
 302 #define AGP_AMD64_NVIDIA_1_APBASE1      0x50
 303 #define AGP_AMD64_NVIDIA_1_APLIMIT1     0x54
 304 #define AGP_AMD64_NVIDIA_1_APSIZE       0xa8
 305 #define AGP_AMD64_NVIDIA_1_APBASE2      0xd8
 306 #define AGP_AMD64_NVIDIA_1_APLIMIT2     0xdc
 307
 308 /*
 309  * ULi M1689 registers
 310  */
 311 #define AGP_AMD64_ULI_APBASE            0x10
 312 #define AGP_AMD64_ULI_HTT_FEATURE       0x50
 313 #define AGP_AMD64_ULI_ENU_SCR           0x54
 314
 315 #endif /* !_PCI_AGPREG_H_ */