2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: ahc_pci.c,v 1.68 2009/11/26 15:17:08 njoly Exp $
44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $
46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $
49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.67 2009/09/02 11:10:37 tsutsui Exp $");
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/malloc.h>
58 #include <sys/kernel.h>
59 #include <sys/queue.h>
60 #include <sys/device.h>
61 #include <sys/reboot.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
70 /* XXXX some i386 on-board chips act weird when memory-mapped */
72 #define AHC_ALLOW_MEMIO
75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */
76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */
78 #include <dev/ic/aic7xxx_osm.h>
79 #include <dev/ic/aic7xxx_inline.h>
81 #include <dev/ic/smc93cx6var.h>
84 static inline uint64_t
85 ahc_compose_id(u_int device
, u_int vendor
, u_int subdevice
, u_int subvendor
)
91 | ((uint64_t)vendor
<< 32)
92 | ((uint64_t)device
<< 48);
97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
101 #define ID_9005_SISL_ID 0x0005900500000000ull
102 #define ID_AIC7850 0x5078900400000000ull
103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull
104 #define ID_AIC7855 0x5578900400000000ull
105 #define ID_AIC7859 0x3860900400000000ull
106 #define ID_AHA_2930CU 0x3860900438699004ull
107 #define ID_AIC7860 0x6078900400000000ull
108 #define ID_AIC7860C 0x6078900478609004ull
109 #define ID_AHA_1480A 0x6075900400000000ull
110 #define ID_AHA_2940AU_0 0x6178900400000000ull
111 #define ID_AHA_2940AU_1 0x6178900478619004ull
112 #define ID_AHA_2940AU_CN 0x2178900478219004ull
113 #define ID_AHA_2930C_VAR 0x6038900438689004ull
115 #define ID_AIC7870 0x7078900400000000ull
116 #define ID_AHA_2940 0x7178900400000000ull
117 #define ID_AHA_3940 0x7278900400000000ull
118 #define ID_AHA_398X 0x7378900400000000ull
119 #define ID_AHA_2944 0x7478900400000000ull
120 #define ID_AHA_3944 0x7578900400000000ull
121 #define ID_AHA_4944 0x7678900400000000ull
123 #define ID_AIC7880 0x8078900400000000ull
124 #define ID_AIC7880_B 0x8078900478809004ull
125 #define ID_AHA_2940U 0x8178900400000000ull
126 #define ID_AHA_3940U 0x8278900400000000ull
127 #define ID_AHA_2944U 0x8478900400000000ull
128 #define ID_AHA_3944U 0x8578900400000000ull
129 #define ID_AHA_398XU 0x8378900400000000ull
130 #define ID_AHA_4944U 0x8678900400000000ull
131 #define ID_AHA_2940UB 0x8178900478819004ull
132 #define ID_AHA_2930U 0x8878900478889004ull
133 #define ID_AHA_2940U_PRO 0x8778900478879004ull
134 #define ID_AHA_2940U_CN 0x0078900478009004ull
136 #define ID_AIC7895 0x7895900478959004ull
137 #define ID_AIC7895_ARO 0x7890900478939004ull
138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
140 #define ID_AHA_3940AU 0x7895900478929004ull
141 #define ID_AHA_3944AU 0x7895900478949004ull
143 #define ID_AIC7890 0x001F9005000F9005ull
144 #define ID_AIC7890_ARO 0x00139005000F9005ull
145 #define ID_AAA_131U2 0x0013900500039005ull
146 #define ID_AHA_2930U2 0x0011900501819005ull
147 #define ID_AHA_2940U2B 0x00109005A1009005ull
148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
149 #define ID_AHA_2940U2 0x00109005A1809005ull
150 #define ID_AHA_2950U2B 0x00109005E1009005ull
152 #define ID_AIC7892 0x008F9005FFFF9005ull
153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
154 #define ID_AHA_2915LP 0x0082900502109005ull
155 #define ID_AHA_29160 0x00809005E2A09005ull
156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
157 #define ID_AHA_29160N 0x0080900562A09005ull
158 #define ID_AHA_29160C 0x0080900562209005ull
159 #define ID_AHA_29160B 0x00809005E2209005ull
160 #define ID_AHA_19160B 0x0081900562A19005ull
162 #define ID_AIC7896 0x005F9005FFFF9005ull
163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
169 #define ID_AIC7899 0x00CF9005FFFF9005ull
170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
171 #define ID_AHA_3960D 0x00C09005F6209005ull
172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
174 #define ID_AIC7810 0x1078900400000000ull
175 #define ID_AIC7815 0x7815900400000000ull
177 #define DEVID_9005_TYPE(id) ((id) & 0xF)
178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
184 #define DEVID_9005_MAXRATE_U160 0x0
185 #define DEVID_9005_MAXRATE_ULTRA2 0x1
186 #define DEVID_9005_MAXRATE_ULTRA 0x2
187 #define DEVID_9005_MAXRATE_FAST 0x3
189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
194 #define SUBID_9005_TYPE(id) ((id) & 0xF)
195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
200 #define SUBID_9005_TYPE_KNOWN(id) \
201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
207 #define SUBID_9005_MAXRATE_ULTRA2 0x0
208 #define SUBID_9005_MAXRATE_ULTRA 0x1
209 #define SUBID_9005_MAXRATE_U160 0x2
210 #define SUBID_9005_MAXRATE_RESERVED 0x3
212 #define SUBID_9005_SEEPTYPE(id) \
213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
214 ? ((id) & 0xC0) >> 6 \
215 : ((id) & 0x300) >> 8)
216 #define SUBID_9005_SEEPTYPE_NONE 0x0
217 #define SUBID_9005_SEEPTYPE_1K 0x1
218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
220 #define SUBID_9005_AUTOTERM(id) \
221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
222 ? (((id) & 0x400) >> 10) == 0 \
223 : (((id) & 0x40) >> 6) == 0)
225 #define SUBID_9005_NUMCHAN(id) \
226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
227 ? ((id) & 0x300) >> 8 \
228 : ((id) & 0xC00) >> 10)
230 #define SUBID_9005_LEGACYCONN(id) \
231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
233 : ((id) & 0x80) >> 7)
235 #define SUBID_9005_MFUNCENB(id) \
236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
237 ? ((id) & 0x800) >> 11 \
238 : ((id) & 0x1000) >> 12)
240 * Informational only. Should use chip register to be
241 * certain, but may be use in identification strings.
243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
247 static ahc_device_setup_t ahc_aic785X_setup
;
248 static ahc_device_setup_t ahc_aic7860_setup
;
249 static ahc_device_setup_t ahc_apa1480_setup
;
250 static ahc_device_setup_t ahc_aic7870_setup
;
251 static ahc_device_setup_t ahc_aha394X_setup
;
252 static ahc_device_setup_t ahc_aha494X_setup
;
253 static ahc_device_setup_t ahc_aha398X_setup
;
254 static ahc_device_setup_t ahc_aic7880_setup
;
255 static ahc_device_setup_t ahc_aha2940Pro_setup
;
256 static ahc_device_setup_t ahc_aha394XU_setup
;
257 static ahc_device_setup_t ahc_aha398XU_setup
;
258 static ahc_device_setup_t ahc_aic7890_setup
;
259 static ahc_device_setup_t ahc_aic7892_setup
;
260 static ahc_device_setup_t ahc_aic7895_setup
;
261 static ahc_device_setup_t ahc_aic7896_setup
;
262 static ahc_device_setup_t ahc_aic7899_setup
;
263 static ahc_device_setup_t ahc_aha29160C_setup
;
264 static ahc_device_setup_t ahc_raid_setup
;
265 static ahc_device_setup_t ahc_aha394XX_setup
;
266 static ahc_device_setup_t ahc_aha494XX_setup
;
267 static ahc_device_setup_t ahc_aha398XX_setup
;
269 static struct ahc_pci_identity ahc_pci_ident_table
[] =
271 /* aic7850 based controllers */
273 ID_AHA_2902_04_10_15_20_30C
,
275 "Adaptec 2902/04/10/15/20/30C SCSI adapter",
278 /* aic7860 based controllers */
282 "Adaptec 2930CU SCSI adapter",
286 ID_AHA_1480A
& ID_DEV_VENDOR_MASK
,
288 "Adaptec 1480A Ultra SCSI adapter",
292 ID_AHA_2940AU_0
& ID_DEV_VENDOR_MASK
,
294 "Adaptec 2940A Ultra SCSI adapter",
298 ID_AHA_2940AU_CN
& ID_DEV_VENDOR_MASK
,
300 "Adaptec 2940A/CN Ultra SCSI adapter",
304 ID_AHA_2930C_VAR
& ID_DEV_VENDOR_MASK
,
306 "Adaptec 2930C Ultra SCSI adapter (VAR)",
309 /* aic7870 based controllers */
313 "Adaptec 2940 SCSI adapter",
319 "Adaptec 3940 SCSI adapter",
325 "Adaptec 398X SCSI RAID adapter",
331 "Adaptec 2944 SCSI adapter",
337 "Adaptec 3944 SCSI adapter",
343 "Adaptec 4944 SCSI adapter",
346 /* aic7880 based controllers */
348 ID_AHA_2940U
& ID_DEV_VENDOR_MASK
,
350 "Adaptec 2940 Ultra SCSI adapter",
354 ID_AHA_3940U
& ID_DEV_VENDOR_MASK
,
356 "Adaptec 3940 Ultra SCSI adapter",
360 ID_AHA_2944U
& ID_DEV_VENDOR_MASK
,
362 "Adaptec 2944 Ultra SCSI adapter",
366 ID_AHA_3944U
& ID_DEV_VENDOR_MASK
,
368 "Adaptec 3944 Ultra SCSI adapter",
372 ID_AHA_398XU
& ID_DEV_VENDOR_MASK
,
374 "Adaptec 398X Ultra SCSI RAID adapter",
379 * XXX Don't know the slot numbers
380 * so we can't identify channels
382 ID_AHA_4944U
& ID_DEV_VENDOR_MASK
,
384 "Adaptec 4944 Ultra SCSI adapter",
388 ID_AHA_2930U
& ID_DEV_VENDOR_MASK
,
390 "Adaptec 2930 Ultra SCSI adapter",
394 ID_AHA_2940U_PRO
& ID_DEV_VENDOR_MASK
,
396 "Adaptec 2940 Pro Ultra SCSI adapter",
400 ID_AHA_2940U_CN
& ID_DEV_VENDOR_MASK
,
402 "Adaptec 2940/CN Ultra SCSI adapter",
405 /* Ignore all SISL (AAC on MB) based controllers. */
412 /* aic7890 based controllers */
416 "Adaptec 2930 Ultra2 SCSI adapter",
422 "Adaptec 2940B Ultra2 SCSI adapter",
428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
434 "Adaptec 2940 Ultra2 SCSI adapter",
440 "Adaptec 2950 Ultra2 SCSI adapter",
446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
452 "Adaptec AAA-131 Ultra2 RAID adapter",
455 /* aic7892 based controllers */
459 "Adaptec 29160 Ultra160 SCSI adapter",
465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
471 "Adaptec 29160N Ultra160 SCSI adapter",
477 "Adaptec 29160C Ultra160 SCSI adapter",
483 "Adaptec 29160B Ultra160 SCSI adapter",
489 "Adaptec 19160B Ultra160 SCSI adapter",
495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
501 "Adaptec 2915LP Ultra160 SCSI adapter",
504 /* aic7895 based controllers */
508 "Adaptec 2940/DUAL Ultra SCSI adapter",
514 "Adaptec 3940A Ultra SCSI adapter",
520 "Adaptec 3944A Ultra SCSI adapter",
526 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
529 /* aic7896/97 based controllers */
533 "Adaptec 3950B Ultra2 SCSI adapter",
539 "Adaptec 3950B Ultra2 SCSI adapter",
545 "Adaptec 3950D Ultra2 SCSI adapter",
551 "Adaptec 3950D Ultra2 SCSI adapter",
557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
560 /* aic7899 based controllers */
564 "Adaptec 3960D Ultra160 SCSI adapter",
570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
579 /* Generic chip probes for devices we don't know 'exactly' */
581 ID_AIC7850
& ID_DEV_VENDOR_MASK
,
583 "Adaptec aic7850 SCSI adapter",
587 ID_AIC7855
& ID_DEV_VENDOR_MASK
,
589 "Adaptec aic7855 SCSI adapter",
593 ID_AIC7859
& ID_DEV_VENDOR_MASK
,
595 "Adaptec aic7859 SCSI adapter",
599 ID_AIC7860
& ID_DEV_VENDOR_MASK
,
601 "Adaptec aic7860 Ultra SCSI adapter",
605 ID_AIC7870
& ID_DEV_VENDOR_MASK
,
607 "Adaptec aic7870 SCSI adapter",
611 ID_AIC7880
& ID_DEV_VENDOR_MASK
,
613 "Adaptec aic7880 Ultra SCSI adapter",
617 ID_AIC7890
& ID_9005_GENERIC_MASK
,
618 ID_9005_GENERIC_MASK
,
619 "Adaptec aic7890/91 Ultra2 SCSI adapter",
623 ID_AIC7892
& ID_9005_GENERIC_MASK
,
624 ID_9005_GENERIC_MASK
,
625 "Adaptec aic7892 Ultra160 SCSI adapter",
629 ID_AIC7895
& ID_DEV_VENDOR_MASK
,
631 "Adaptec aic7895 Ultra SCSI adapter",
635 ID_AIC7896
& ID_9005_GENERIC_MASK
,
636 ID_9005_GENERIC_MASK
,
637 "Adaptec aic7896/97 Ultra2 SCSI adapter",
641 ID_AIC7899
& ID_9005_GENERIC_MASK
,
642 ID_9005_GENERIC_MASK
,
643 "Adaptec aic7899 Ultra160 SCSI adapter",
647 ID_AIC7810
& ID_DEV_VENDOR_MASK
,
649 "Adaptec aic7810 RAID memory controller",
653 ID_AIC7815
& ID_DEV_VENDOR_MASK
,
655 "Adaptec aic7815 RAID memory controller",
660 static const u_int ahc_num_pci_devs
= NUM_ELEMENTS(ahc_pci_ident_table
);
662 #define AHC_394X_SLOT_CHANNEL_A 4
663 #define AHC_394X_SLOT_CHANNEL_B 5
665 #define AHC_398X_SLOT_CHANNEL_A 4
666 #define AHC_398X_SLOT_CHANNEL_B 8
667 #define AHC_398X_SLOT_CHANNEL_C 12
669 #define AHC_494X_SLOT_CHANNEL_A 4
670 #define AHC_494X_SLOT_CHANNEL_B 5
671 #define AHC_494X_SLOT_CHANNEL_C 6
672 #define AHC_494X_SLOT_CHANNEL_D 7
674 #define DEVCONFIG 0x40
675 #define PCIERRGENDIS 0x80000000ul
676 #define SCBSIZE32 0x00010000ul /* aic789X only */
677 #define REXTVALID 0x00001000ul /* ultra cards only */
678 #define MPORTMODE 0x00000400ul /* aic7870+ only */
679 #define RAMPSM 0x00000200ul /* aic7870+ only */
680 #define VOLSENSE 0x00000100ul
681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
682 #define SCBRAMSEL 0x00000080ul
683 #define MRDCEN 0x00000040ul
684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
686 #define BERREN 0x00000008ul
687 #define DACEN 0x00000004ul
688 #define STPWLEVEL 0x00000002ul
689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
691 #define CSIZE_LATTIME 0x0c
692 #define CACHESIZE 0x0000003ful /* only 5 bits */
693 #define LATTIME 0x0000ff00ul
695 /* PCI STATUS definitions */
703 static int ahc_9005_subdevinfo_valid(uint16_t vendor
, uint16_t device
,
704 uint16_t subvendor
, uint16_t subdevice
);
705 static int ahc_ext_scbram_present(struct ahc_softc
*ahc
);
706 static void ahc_scbram_config(struct ahc_softc
*ahc
, int enable
,
707 int pcheck
, int fast
, int large
);
708 static void ahc_probe_ext_scbram(struct ahc_softc
*ahc
);
710 static void ahc_pci_intr(struct ahc_softc
*);
712 static const struct ahc_pci_identity
*
713 ahc_find_pci_device(pcireg_t id
, pcireg_t subid
, u_int func
)
716 const struct ahc_pci_identity
*entry
;
719 full_id
= ahc_compose_id(PCI_PRODUCT(id
), PCI_VENDOR(id
),
720 PCI_PRODUCT(subid
), PCI_VENDOR(subid
));
723 * If the second function is not hooked up, ignore it.
724 * Unfortunately, not all MB vendors implement the
725 * subdevice ID as per the Adaptec spec, so do our best
726 * to sanity check it prior to accepting the subdevice
730 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id
), PCI_PRODUCT(id
),
731 PCI_VENDOR(subid
), PCI_PRODUCT(subid
))
732 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid
)) == 0)
735 for (i
= 0; i
< ahc_num_pci_devs
; i
++) {
736 entry
= &ahc_pci_ident_table
[i
];
737 if (entry
->full_id
== (full_id
& entry
->id_mask
))
744 ahc_pci_probe(device_t parent
, cfdata_t match
, void *aux
)
746 struct pci_attach_args
*pa
= aux
;
747 const struct ahc_pci_identity
*entry
;
750 subid
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, PCI_SUBSYS_ID_REG
);
751 entry
= ahc_find_pci_device(pa
->pa_id
, subid
, pa
->pa_function
);
752 return (entry
!= NULL
&& entry
->setup
!= NULL
) ? 1 : 0;
756 ahc_pci_attach(device_t parent
, device_t self
, void *aux
)
758 struct pci_attach_args
*pa
= aux
;
759 const struct ahc_pci_identity
*entry
;
760 struct ahc_softc
*ahc
= device_private(self
);
771 bus_space_tag_t st
, iot
;
772 bus_space_handle_t sh
, ioh
;
773 #ifdef AHC_ALLOW_MEMIO
775 bus_space_tag_t memt
;
776 bus_space_handle_t memh
;
779 pci_intr_handle_t ih
;
781 struct ahc_pci_busdata
*bd
;
785 ahc_set_name(ahc
, device_xname(ahc
->sc_dev
));
786 ahc
->parent_dmat
= pa
->pa_dmat
;
788 command
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, PCI_COMMAND_STATUS_REG
);
789 subid
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, PCI_SUBSYS_ID_REG
);
790 entry
= ahc_find_pci_device(pa
->pa_id
, subid
, pa
->pa_function
);
793 printf(": %s\n", entry
->name
);
795 /* Keep information about the PCI bus */
796 bd
= malloc(sizeof (struct ahc_pci_busdata
), M_DEVBUF
, M_NOWAIT
);
798 printf("%s: unable to allocate bus-specific data\n",
802 memset(bd
, 0, sizeof(struct ahc_pci_busdata
));
805 bd
->tag
= pa
->pa_tag
;
806 bd
->func
= pa
->pa_function
;
807 bd
->dev
= pa
->pa_device
;
808 bd
->class = pa
->pa_class
;
812 ahc
->description
= entry
->name
;
814 error
= entry
->setup(ahc
);
820 #ifdef AHC_ALLOW_MEMIO
822 memtype
= pci_mapreg_type(pa
->pa_pc
, pa
->pa_tag
, AHC_PCI_MEMADDR
);
824 case PCI_MAPREG_TYPE_MEM
| PCI_MAPREG_MEM_TYPE_32BIT
:
825 case PCI_MAPREG_TYPE_MEM
| PCI_MAPREG_MEM_TYPE_64BIT
:
826 memh_valid
= (pci_mapreg_map(pa
, AHC_PCI_MEMADDR
,
827 memtype
, 0, &memt
, &memh
, NULL
, NULL
) == 0);
833 ioh_valid
= (pci_mapreg_map(pa
, AHC_PCI_IOADDR
,
834 PCI_MAPREG_TYPE_IO
, 0, &iot
,
835 &ioh
, NULL
, NULL
) == 0);
837 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n",
838 ahc_name(ahc
), (u_long
)memt
, (u_long
)memh
, (u_long
)iot
,
845 #ifdef AHC_ALLOW_MEMIO
846 } else if (memh_valid
) {
851 printf(": unable to map registers\n");
857 ahc
->chip
|= AHC_PCI
;
859 * Before we continue probing the card, ensure that
860 * its interrupts are *disabled*. We don't want
861 * a misstep to hang the machine in an interrupt
864 ahc_intr_enable(ahc
, FALSE
);
867 * XXX somehow reading this once fails on some sparc64 systems.
868 * This may be a problem in the sparc64 PCI code. Doing it
869 * twice works around it.
871 devconfig
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, DEVCONFIG
);
872 devconfig
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, DEVCONFIG
);
875 * If we need to support high memory, enable dual
876 * address cycles. This bit must be set to enable
877 * high address bit generation even if we are on a
878 * 64bit bus (PCI64BIT set in devconfig).
880 if ((ahc
->flags
& AHC_39BIT_ADDRESSING
) != 0) {
882 if (1/*bootverbose*/)
883 printf("%s: Enabling 39Bit Addressing\n",
888 /* Ensure that pci error generation, a test feature, is disabled. */
889 devconfig
|= PCIERRGENDIS
;
891 pci_conf_write(pa
->pa_pc
, pa
->pa_tag
, DEVCONFIG
, devconfig
);
893 /* Ensure busmastering is enabled */
894 command
|= PCI_COMMAND_MASTER_ENABLE
;
895 pci_conf_write(pa
->pa_pc
, pa
->pa_tag
, PCI_COMMAND_STATUS_REG
, command
);
898 * Disable PCI parity error reporting. Users typically
899 * do this to work around broken PCI chipsets that get
900 * the parity timing wrong and thus generate lots of spurious
903 if ((ahc
->flags
& AHC_DISABLE_PCI_PERR
) != 0)
904 command
&= ~PCI_COMMAND_PARITY_ENABLE
;
905 pci_conf_write(pa
->pa_pc
, pa
->pa_tag
, PCI_COMMAND_STATUS_REG
, command
);
907 /* On all PCI adapters, we allow SCB paging */
908 ahc
->flags
|= AHC_PAGESCBS
;
909 error
= ahc_softc_init(ahc
);
913 ahc
->bus_intr
= ahc_pci_intr
;
915 /* Remember how the card was setup in case there is no SEEPROM */
916 if ((ahc_inb(ahc
, HCNTRL
) & POWRDN
) == 0) {
918 if ((ahc
->features
& AHC_ULTRA2
) != 0)
919 our_id
= ahc_inb(ahc
, SCSIID_ULTRA2
) & OID
;
921 our_id
= ahc_inb(ahc
, SCSIID
) & OID
;
922 sxfrctl1
= ahc_inb(ahc
, SXFRCTL1
) & STPWEN
;
923 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
930 error
= ahc_reset(ahc
);
934 if ((ahc
->features
& AHC_DT
) != 0) {
937 /* Perform ALT-Mode Setup */
938 sfunct
= ahc_inb(ahc
, SFUNCT
) & ~ALT_MODE
;
939 ahc_outb(ahc
, SFUNCT
, sfunct
| ALT_MODE
);
940 ahc_outb(ahc
, OPTIONMODE
,
941 OPTIONMODE_DEFAULTS
|AUTOACKEN
|BUSFREEREV
|EXPPHASEDIS
);
942 ahc_outb(ahc
, SFUNCT
, sfunct
);
944 /* Normal mode setup */
945 ahc_outb(ahc
, CRCCONTROL1
, CRCVALCHKEN
|CRCENDCHKEN
|CRCREQCHKEN
949 if (pci_intr_map(pa
, &ih
)) {
950 printf("%s: couldn't map interrupt\n", ahc_name(ahc
));
954 intrstr
= pci_intr_string(pa
->pa_pc
, ih
);
955 ahc
->ih
= pci_intr_establish(pa
->pa_pc
, ih
, IPL_BIO
, ahc_intr
, ahc
);
956 if (ahc
->ih
== NULL
) {
957 aprint_error_dev(ahc
->sc_dev
,
958 "couldn't establish interrupt\n");
960 aprint_error(" at %s", intrstr
);
966 printf("%s: interrupting at %s\n", ahc_name(ahc
), intrstr
);
968 dscommand0
= ahc_inb(ahc
, DSCOMMAND0
);
969 dscommand0
|= MPARCKEN
|CACHETHEN
;
970 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
973 * DPARCKEN doesn't work correctly on
974 * some MBs so don't use it.
976 dscommand0
&= ~DPARCKEN
;
980 * Handle chips that must have cache line
981 * streaming (dis/en)abled.
983 if ((ahc
->bugs
& AHC_CACHETHEN_DIS_BUG
) != 0)
984 dscommand0
|= CACHETHEN
;
986 if ((ahc
->bugs
& AHC_CACHETHEN_BUG
) != 0)
987 dscommand0
&= ~CACHETHEN
;
989 ahc_outb(ahc
, DSCOMMAND0
, dscommand0
);
992 pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, CSIZE_LATTIME
) & CACHESIZE
;
993 ahc
->pci_cachesize
*= 4;
995 if ((ahc
->bugs
& AHC_PCI_2_1_RETRY_BUG
) != 0
996 && ahc
->pci_cachesize
== 4) {
997 pci_conf_write(pa
->pa_pc
, pa
->pa_tag
, CSIZE_LATTIME
, 0);
998 ahc
->pci_cachesize
= 0;
1002 * We cannot perform ULTRA speeds without the presence
1003 * of the external precision resistor.
1004 * Allow override for the SGI O2 though, which has two onboard ahc
1005 * that fail here but are perfectly capable of ultra speeds.
1007 override_ultra
= FALSE
;
1008 prop_dictionary_get_bool(device_properties(self
),
1009 "aic7xxx-override-ultra", &override_ultra
);
1011 if (((ahc
->features
& AHC_ULTRA
) != 0) && (!override_ultra
)) {
1014 dvconfig
= pci_conf_read(pa
->pa_pc
, pa
->pa_tag
, DEVCONFIG
);
1015 if ((dvconfig
& REXTVALID
) == 0)
1016 ahc
->features
&= ~AHC_ULTRA
;
1019 ahc
->seep_config
= malloc(sizeof(*ahc
->seep_config
),
1020 M_DEVBUF
, M_NOWAIT
);
1021 if (ahc
->seep_config
== NULL
)
1024 memset(ahc
->seep_config
, 0, sizeof(*ahc
->seep_config
));
1026 /* See if we have a SEEPROM and perform auto-term */
1027 ahc_check_extport(ahc
, &sxfrctl1
);
1030 * Take the LED out of diagnostic mode
1032 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
1033 ahc_outb(ahc
, SBLKCTL
, (sblkctl
& ~(DIAGLEDEN
|DIAGLEDON
)));
1035 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1036 ahc_outb(ahc
, DFF_THRSH
, RD_DFTHRSH_MAX
|WR_DFTHRSH_MAX
);
1038 ahc_outb(ahc
, DSPCISTATUS
, DFTHRSH_100
);
1041 if (ahc
->flags
& AHC_USEDEFAULTS
) {
1043 * PCI Adapter default setup
1044 * Should only be used if the adapter does not have
1047 /* See if someone else set us up already */
1048 if ((ahc
->flags
& AHC_NO_BIOS_INIT
) == 0
1052 printf("%s: Using left over BIOS settings\n",
1054 ahc
->flags
&= ~AHC_USEDEFAULTS
;
1056 * Ignore target device settings and use default
1057 * if BIOS initializes chip's SRAM with some
1058 * conservative settings (async, no tagged
1059 * queuing etc.) and machine dependent device
1062 usetd
= prop_dictionary_get(
1063 device_properties(ahc
->sc_dev
),
1064 "aic7xxx-use-target-defaults");
1065 if (usetd
!= NULL
) {
1066 KASSERT(prop_object_type(usetd
) ==
1068 if (prop_bool_true(usetd
))
1069 ahc
->flags
|= AHC_USETARGETDEFAULTS
;
1071 ahc
->flags
|= AHC_BIOS_ENABLED
;
1074 * Assume only one connector and always turn
1080 ahc_outb(ahc
, SCSICONF
, our_id
|ENSPCHK
|RESET_SCSI
);
1082 ahc
->our_id
= our_id
;
1086 * Take a look to see if we have external SRAM.
1087 * We currently do not attempt to use SRAM that is
1088 * shared among multiple controllers.
1090 ahc_probe_ext_scbram(ahc
);
1093 * Record our termination setting for the
1094 * generic initialization routine.
1096 if ((sxfrctl1
& STPWEN
) != 0)
1097 ahc
->flags
|= AHC_TERM_ENB_A
;
1111 CFATTACH_DECL_NEW(ahc_pci
, sizeof(struct ahc_softc
),
1112 ahc_pci_probe
, ahc_pci_attach
, NULL
, NULL
);
1115 ahc_9005_subdevinfo_valid(uint16_t device
, uint16_t vendor
,
1116 uint16_t subdevice
, uint16_t subvendor
)
1120 /* Default to invalid. */
1122 if (vendor
== 0x9005
1123 && subvendor
== 0x9005
1124 && subdevice
!= device
1125 && SUBID_9005_TYPE_KNOWN(subdevice
) != 0) {
1127 switch (SUBID_9005_TYPE(subdevice
)) {
1128 case SUBID_9005_TYPE_MB
:
1130 case SUBID_9005_TYPE_CARD
:
1131 case SUBID_9005_TYPE_LCCARD
:
1133 * Currently only trust Adaptec cards to
1134 * get the sub device info correct.
1136 if (DEVID_9005_TYPE(device
) == DEVID_9005_TYPE_HBA
)
1139 case SUBID_9005_TYPE_RAID
:
1150 * Test for the presense of external sram in an
1151 * "unshared" configuration.
1154 ahc_ext_scbram_present(struct ahc_softc
*ahc
)
1161 chip
= ahc
->chip
& AHC_CHIPID_MASK
;
1162 devconfig
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
, DEVCONFIG
);
1163 single_user
= (devconfig
& MPORTMODE
) != 0;
1165 if ((ahc
->features
& AHC_ULTRA2
) != 0)
1166 ramps
= (ahc_inb(ahc
, DSCOMMAND0
) & RAMPS
) != 0;
1167 else if (chip
== AHC_AIC7895
|| chip
== AHC_AIC7895C
)
1169 * External SCBRAM arbitration is flakey
1170 * on these chips. Unfortunately this means
1171 * we don't use the extra SCB ram space on the
1175 else if (chip
>= AHC_AIC7870
)
1176 ramps
= (devconfig
& RAMPSM
) != 0;
1180 if (ramps
&& single_user
)
1186 * Enable external scbram.
1189 ahc_scbram_config(struct ahc_softc
*ahc
, int enable
, int pcheck
,
1190 int fast
, int large
)
1194 if (ahc
->features
& AHC_MULTI_FUNC
) {
1196 * Set the SCB Base addr (highest address bit)
1197 * depending on which channel we are.
1199 ahc_outb(ahc
, SCBBADDR
, ahc
->bd
->func
);
1202 ahc
->flags
&= ~AHC_LSCBS_ENABLED
;
1204 ahc
->flags
|= AHC_LSCBS_ENABLED
;
1205 devconfig
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
, DEVCONFIG
);
1206 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1209 dscommand0
= ahc_inb(ahc
, DSCOMMAND0
);
1211 dscommand0
&= ~INTSCBRAMSEL
;
1213 dscommand0
|= INTSCBRAMSEL
;
1215 dscommand0
&= ~USCBSIZE32
;
1217 dscommand0
|= USCBSIZE32
;
1218 ahc_outb(ahc
, DSCOMMAND0
, dscommand0
);
1221 devconfig
&= ~EXTSCBTIME
;
1223 devconfig
|= EXTSCBTIME
;
1225 devconfig
&= ~SCBRAMSEL
;
1227 devconfig
|= SCBRAMSEL
;
1229 devconfig
&= ~SCBSIZE32
;
1231 devconfig
|= SCBSIZE32
;
1234 devconfig
|= EXTSCBPEN
;
1236 devconfig
&= ~EXTSCBPEN
;
1238 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
, DEVCONFIG
, devconfig
);
1242 * Take a look to see if we have external SRAM.
1243 * We currently do not attempt to use SRAM that is
1244 * shared among multiple controllers.
1247 ahc_probe_ext_scbram(struct ahc_softc
*ahc
)
1262 if (ahc_ext_scbram_present(ahc
) == 0)
1266 * Probe for the best parameters to use.
1268 ahc_scbram_config(ahc
, /*enable*/TRUE
, pcheck
, fast
, large
);
1269 num_scbs
= ahc_probe_scbs(ahc
);
1270 if (num_scbs
== 0) {
1271 /* The SRAM wasn't really present. */
1277 * Clear any outstanding parity error
1278 * and ensure that parity error reporting
1281 ahc_outb(ahc
, SEQCTL
, 0);
1282 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
1283 ahc_outb(ahc
, CLRINT
, CLRBRKADRINT
);
1285 /* Now see if we can do parity */
1286 ahc_scbram_config(ahc
, enable
, /*pcheck*/TRUE
, fast
, large
);
1287 num_scbs
= ahc_probe_scbs(ahc
);
1288 if ((ahc_inb(ahc
, INTSTAT
) & BRKADRINT
) == 0
1289 || (ahc_inb(ahc
, ERROR
) & MPARERR
) == 0)
1292 /* Clear any resulting parity error */
1293 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
1294 ahc_outb(ahc
, CLRINT
, CLRBRKADRINT
);
1296 /* Now see if we can do fast timing */
1297 ahc_scbram_config(ahc
, enable
, pcheck
, /*fast*/TRUE
, large
);
1298 test_num_scbs
= ahc_probe_scbs(ahc
);
1299 if (test_num_scbs
== num_scbs
1300 && ((ahc_inb(ahc
, INTSTAT
) & BRKADRINT
) == 0
1301 || (ahc_inb(ahc
, ERROR
) & MPARERR
) == 0))
1305 * See if we can use large SCBs and still maintain
1306 * the same overall count of SCBs.
1308 if ((ahc
->features
& AHC_LARGE_SCBS
) != 0) {
1309 ahc_scbram_config(ahc
, enable
, pcheck
, fast
, /*large*/TRUE
);
1310 test_num_scbs
= ahc_probe_scbs(ahc
);
1311 if (test_num_scbs
>= num_scbs
) {
1313 num_scbs
= test_num_scbs
;
1314 if (num_scbs
>= 64) {
1316 * We have enough space to move the
1317 * "busy targets table" into SCB space
1318 * and make it qualify all the way to the
1321 ahc
->flags
|= AHC_SCB_BTT
;
1327 * Disable parity error reporting until we
1328 * can load instruction ram.
1330 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
);
1331 /* Clear any latched parity error */
1332 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
1333 ahc_outb(ahc
, CLRINT
, CLRBRKADRINT
);
1334 if (1/*bootverbose*/ && enable
) {
1335 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1336 ahc_name(ahc
), fast
? "fast" : "slow",
1337 pcheck
? ", parity checking enabled" : "",
1340 ahc_scbram_config(ahc
, enable
, pcheck
, fast
, large
);
1345 * Perform some simple tests that should catch situations where
1346 * our registers are invalidly mapped.
1349 ahc_pci_test_register_access(struct ahc_softc
*ahc
)
1359 * Enable PCI error interrupt status, but suppress NMIs
1360 * generated by SERR raised due to target aborts.
1362 cmd
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
, PCIR_COMMAND
);
1363 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
, PCIR_COMMAND
,
1364 cmd
& ~PCIM_CMD_SERRESPEN
);
1367 * First a simple test to see if any
1368 * registers can be read. Reading
1369 * HCNTRL has no side effects and has
1370 * at least one bit that is guaranteed to
1371 * be zero so it is a good register to
1372 * use for this test.
1374 hcntrl
= ahc_inb(ahc
, HCNTRL
);
1379 * Next create a situation where write combining
1380 * or read prefetching could be initiated by the
1381 * CPU or host bridge. Our device does not support
1382 * either, so look for data corruption and/or flagged
1385 ahc_outb(ahc
, HCNTRL
, hcntrl
|PAUSE
);
1386 while (ahc_is_paused(ahc
) == 0)
1388 ahc_outb(ahc
, SEQCTL
, PERRORDIS
);
1389 ahc_outb(ahc
, SCBPTR
, 0);
1390 ahc_outl(ahc
, SCB_BASE
, 0x5aa555aa);
1391 if (ahc_inl(ahc
, SCB_BASE
) != 0x5aa555aa)
1394 status1
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
,
1395 PCI_COMMAND_STATUS_REG
+ 1);
1396 if ((status1
& STA
) != 0)
1402 /* Silently clear any latched errors. */
1403 status1
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
,
1404 PCI_COMMAND_STATUS_REG
+ 1);
1405 ahc_pci_write_config(ahc
->dev_softc
, PCIR_STATUS
+ 1,
1406 status1
, /*bytes*/1);
1407 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
1408 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
);
1409 ahc_pci_write_config(ahc
->dev_softc
, PCIR_COMMAND
, cmd
, /*bytes*/2);
1415 ahc_pci_intr(struct ahc_softc
*ahc
)
1420 error
= ahc_inb(ahc
, ERROR
);
1421 if ((error
& PCIERRSTAT
) == 0)
1424 status1
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
,
1425 PCI_COMMAND_STATUS_REG
);
1427 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1429 ahc_inb(ahc
, SEQADDR0
) | (ahc_inb(ahc
, SEQADDR1
) << 8));
1431 if (status1
& DPE
) {
1432 printf("%s: Data Parity Error Detected during address "
1433 "or write data phase\n", ahc_name(ahc
));
1435 if (status1
& SSE
) {
1436 printf("%s: Signal System Error Detected\n", ahc_name(ahc
));
1438 if (status1
& RMA
) {
1439 printf("%s: Received a Master Abort\n", ahc_name(ahc
));
1441 if (status1
& RTA
) {
1442 printf("%s: Received a Target Abort\n", ahc_name(ahc
));
1444 if (status1
& STA
) {
1445 printf("%s: Signaled a Target Abort\n", ahc_name(ahc
));
1447 if (status1
& DPR
) {
1448 printf("%s: Data Parity Error has been reported via PERR#\n",
1452 /* Clear latched errors. */
1453 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
, PCI_COMMAND_STATUS_REG
,
1456 if ((status1
& (DPE
|SSE
|RMA
|RTA
|STA
|DPR
)) == 0) {
1457 printf("%s: Latched PCIERR interrupt with "
1458 "no status bits set\n", ahc_name(ahc
));
1460 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
1467 ahc_aic785X_setup(struct ahc_softc
*ahc
)
1472 ahc
->chip
= AHC_AIC7850
;
1473 ahc
->features
= AHC_AIC7850_FE
;
1474 ahc
->bugs
|= AHC_TMODE_WIDEODD_BUG
|AHC_CACHETHEN_BUG
|AHC_PCI_MWI_BUG
;
1475 rev
= PCI_REVISION(ahc
->bd
->class);
1477 ahc
->bugs
|= AHC_PCI_2_1_RETRY_BUG
;
1482 ahc_aic7860_setup(struct ahc_softc
*ahc
)
1487 ahc
->chip
= AHC_AIC7860
;
1488 ahc
->features
= AHC_AIC7860_FE
;
1489 ahc
->bugs
|= AHC_TMODE_WIDEODD_BUG
|AHC_CACHETHEN_BUG
|AHC_PCI_MWI_BUG
;
1490 rev
= PCI_REVISION(ahc
->bd
->class);
1492 ahc
->bugs
|= AHC_PCI_2_1_RETRY_BUG
;
1497 ahc_apa1480_setup(struct ahc_softc
*ahc
)
1501 error
= ahc_aic7860_setup(ahc
);
1504 ahc
->features
|= AHC_REMOVABLE
;
1509 ahc_aic7870_setup(struct ahc_softc
*ahc
)
1513 ahc
->chip
= AHC_AIC7870
;
1514 ahc
->features
= AHC_AIC7870_FE
;
1515 ahc
->bugs
|= AHC_TMODE_WIDEODD_BUG
|AHC_CACHETHEN_BUG
|AHC_PCI_MWI_BUG
;
1520 ahc_aha394X_setup(struct ahc_softc
*ahc
)
1524 error
= ahc_aic7870_setup(ahc
);
1526 error
= ahc_aha394XX_setup(ahc
);
1531 ahc_aha398X_setup(struct ahc_softc
*ahc
)
1535 error
= ahc_aic7870_setup(ahc
);
1537 error
= ahc_aha398XX_setup(ahc
);
1542 ahc_aha494X_setup(struct ahc_softc
*ahc
)
1546 error
= ahc_aic7870_setup(ahc
);
1548 error
= ahc_aha494XX_setup(ahc
);
1553 ahc_aic7880_setup(struct ahc_softc
*ahc
)
1558 ahc
->chip
= AHC_AIC7880
;
1559 ahc
->features
= AHC_AIC7880_FE
;
1560 ahc
->bugs
|= AHC_TMODE_WIDEODD_BUG
;
1561 rev
= PCI_REVISION(ahc
->bd
->class);
1563 ahc
->bugs
|= AHC_PCI_2_1_RETRY_BUG
;
1565 ahc
->bugs
|= AHC_CACHETHEN_BUG
|AHC_PCI_MWI_BUG
;
1571 ahc_aha2940Pro_setup(struct ahc_softc
*ahc
)
1574 ahc
->flags
|= AHC_INT50_SPEEDFLEX
;
1575 return (ahc_aic7880_setup(ahc
));
1579 ahc_aha394XU_setup(struct ahc_softc
*ahc
)
1583 error
= ahc_aic7880_setup(ahc
);
1585 error
= ahc_aha394XX_setup(ahc
);
1590 ahc_aha398XU_setup(struct ahc_softc
*ahc
)
1594 error
= ahc_aic7880_setup(ahc
);
1596 error
= ahc_aha398XX_setup(ahc
);
1601 ahc_aic7890_setup(struct ahc_softc
*ahc
)
1606 ahc
->chip
= AHC_AIC7890
;
1607 ahc
->features
= AHC_AIC7890_FE
;
1608 ahc
->flags
|= AHC_NEWEEPROM_FMT
;
1609 rev
= PCI_REVISION(ahc
->bd
->class);
1611 ahc
->bugs
|= AHC_AUTOFLUSH_BUG
|AHC_CACHETHEN_BUG
;
1616 ahc_aic7892_setup(struct ahc_softc
*ahc
)
1620 ahc
->chip
= AHC_AIC7892
;
1621 ahc
->features
= AHC_AIC7892_FE
;
1622 ahc
->flags
|= AHC_NEWEEPROM_FMT
;
1623 ahc
->bugs
|= AHC_SCBCHAN_UPLOAD_BUG
;
1628 ahc_aic7895_setup(struct ahc_softc
*ahc
)
1632 ahc
->channel
= (ahc
->bd
->func
== 1) ? 'B' : 'A';
1634 * The 'C' revision of the aic7895 has a few additional features.
1636 rev
= PCI_REVISION(ahc
->bd
->class);
1638 ahc
->chip
= AHC_AIC7895C
;
1639 ahc
->features
= AHC_AIC7895C_FE
;
1643 ahc
->chip
= AHC_AIC7895
;
1644 ahc
->features
= AHC_AIC7895_FE
;
1647 * The BIOS disables the use of MWI transactions
1648 * since it does not have the MWI bug work around
1649 * we have. Disabling MWI reduces performance, so
1652 command
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
,
1653 PCI_COMMAND_STATUS_REG
);
1654 command
|= PCI_COMMAND_INVALIDATE_ENABLE
;
1655 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
,
1656 PCI_COMMAND_STATUS_REG
, command
);
1657 ahc
->bugs
|= AHC_PCI_MWI_BUG
;
1660 * XXX Does CACHETHEN really not work??? What about PCI retry?
1661 * on C level chips. Need to test, but for now, play it safe.
1663 ahc
->bugs
|= AHC_TMODE_WIDEODD_BUG
|AHC_PCI_2_1_RETRY_BUG
1664 | AHC_CACHETHEN_BUG
;
1670 * Cachesize must also be zero due to stray DAC
1671 * problem when sitting behind some bridges.
1673 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
, CSIZE_LATTIME
, 0);
1674 devconfig
= pci_conf_read(ahc
->bd
->pc
, ahc
->bd
->tag
, DEVCONFIG
);
1675 devconfig
|= MRDCEN
;
1676 pci_conf_write(ahc
->bd
->pc
, ahc
->bd
->tag
, DEVCONFIG
, devconfig
);
1678 ahc
->flags
|= AHC_NEWEEPROM_FMT
;
1683 ahc_aic7896_setup(struct ahc_softc
*ahc
)
1685 ahc
->channel
= (ahc
->bd
->func
== 1) ? 'B' : 'A';
1686 ahc
->chip
= AHC_AIC7896
;
1687 ahc
->features
= AHC_AIC7896_FE
;
1688 ahc
->flags
|= AHC_NEWEEPROM_FMT
;
1689 ahc
->bugs
|= AHC_CACHETHEN_DIS_BUG
;
1694 ahc_aic7899_setup(struct ahc_softc
*ahc
)
1696 ahc
->channel
= (ahc
->bd
->func
== 1) ? 'B' : 'A';
1697 ahc
->chip
= AHC_AIC7899
;
1698 ahc
->features
= AHC_AIC7899_FE
;
1699 ahc
->flags
|= AHC_NEWEEPROM_FMT
;
1700 ahc
->bugs
|= AHC_SCBCHAN_UPLOAD_BUG
;
1705 ahc_aha29160C_setup(struct ahc_softc
*ahc
)
1709 error
= ahc_aic7899_setup(ahc
);
1712 ahc
->features
|= AHC_REMOVABLE
;
1717 ahc_raid_setup(struct ahc_softc
*ahc
)
1719 aprint_normal_dev(ahc
->sc_dev
, "RAID functionality unsupported\n");
1724 ahc_aha394XX_setup(struct ahc_softc
*ahc
)
1727 switch (ahc
->bd
->dev
) {
1728 case AHC_394X_SLOT_CHANNEL_A
:
1731 case AHC_394X_SLOT_CHANNEL_B
:
1735 printf("adapter at unexpected slot %d\n"
1736 "unable to map to a channel\n",
1744 ahc_aha398XX_setup(struct ahc_softc
*ahc
)
1747 switch (ahc
->bd
->dev
) {
1748 case AHC_398X_SLOT_CHANNEL_A
:
1751 case AHC_398X_SLOT_CHANNEL_B
:
1754 case AHC_398X_SLOT_CHANNEL_C
:
1758 printf("adapter at unexpected slot %d\n"
1759 "unable to map to a channel\n",
1764 ahc
->flags
|= AHC_LARGE_SEEPROM
;
1769 ahc_aha494XX_setup(struct ahc_softc
*ahc
)
1772 switch (ahc
->bd
->dev
) {
1773 case AHC_494X_SLOT_CHANNEL_A
:
1776 case AHC_494X_SLOT_CHANNEL_B
:
1779 case AHC_494X_SLOT_CHANNEL_C
:
1782 case AHC_494X_SLOT_CHANNEL_D
:
1786 printf("adapter at unexpected slot %d\n"
1787 "unable to map to a channel\n",
1791 ahc
->flags
|= AHC_LARGE_SEEPROM
;