sys/dev/pci/artsata.c

   1 /*      $NetBSD: artsata.c,v 1.18 2008/04/28 20:23:54 martin Exp $      */
   2
   3 /*-
   4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of Wasabi Systems, Inc.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.18 2008/04/28 20:23:54 martin Exp $");
  34
  35 #include "opt_pciide.h"
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/malloc.h>
  40
  41 #include <dev/pci/pcivar.h>
  42 #include <dev/pci/pcidevs.h>
  43 #include <dev/pci/pciidereg.h>
  44 #include <dev/pci/pciidevar.h>
  45 #include <dev/pci/pciide_i31244_reg.h>
  46
  47 #include <dev/ata/satareg.h>
  48 #include <dev/ata/satavar.h>
  49 #include <dev/ata/atareg.h>
  50 #include <dev/ata/atavar.h>
  51
  52 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *);
  53
  54 static int  artsata_match(device_t, cfdata_t, void *);
  55 static void artsata_attach(device_t, device_t, void *);
  56
  57 static const struct pciide_product_desc pciide_artsata_products[] =  {
  58         { PCI_PRODUCT_INTEL_31244,
  59           0,
  60           "Intel 31244 Serial ATA Controller",
  61           artisea_chip_map,
  62         },
  63         { 0,
  64           0,
  65           NULL,
  66           NULL
  67         }
  68 };
  69
  70 struct artisea_cmd_map
  71 {
  72         u_int8_t offset;
  73         u_int8_t size;
  74 };
  75
  76 static const struct artisea_cmd_map artisea_dpa_cmd_map[] =
  77 {
  78         {ARTISEA_SUPDDR, 4},    /* 0 Data */
  79         {ARTISEA_SUPDER, 1},    /* 1 Error */
  80         {ARTISEA_SUPDCSR, 2},   /* 2 Sector Count */
  81         {ARTISEA_SUPDSNR, 2},   /* 3 Sector Number */
  82         {ARTISEA_SUPDCLR, 2},   /* 4 Cylinder Low */
  83         {ARTISEA_SUPDCHR, 2},   /* 5 Cylinder High */
  84         {ARTISEA_SUPDDHR, 1},   /* 6 Device/Head */
  85         {ARTISEA_SUPDCR, 1},    /* 7 Command */
  86         {ARTISEA_SUPDSR, 1},    /* 8 Status */
  87         {ARTISEA_SUPDFR, 2}     /* 9 Feature */
  88 };
  89
  90 #define ARTISEA_NUM_CHAN 4
  91
  92 CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc),
  93     artsata_match, artsata_attach, NULL, NULL);
  94
  95 static int
  96 artsata_match(device_t parent, cfdata_t match, void *aux)
  97 {
  98         struct pci_attach_args *pa = aux;
  99
 100         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
 101                 if (pciide_lookup_product(pa->pa_id, pciide_artsata_products))
 102                         return (2);
 103         }
 104         return (0);
 105 }
 106
 107 static void
 108 artsata_attach(device_t parent, device_t self, void *aux)
 109 {
 110         struct pci_attach_args *pa = aux;
 111         struct pciide_softc *sc = device_private(self);
 112
 113         sc->sc_wdcdev.sc_atac.atac_dev = self;
 114
 115         pciide_common_attach(sc, pa,
 116             pciide_lookup_product(pa->pa_id, pciide_artsata_products));
 117
 118 }
 119
 120 static void
 121 artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp,
 122     bus_size_t *cmdsizep, bus_size_t *ctlsizep,
 123     int (*pci_intr)(void *))
 124 {
 125         struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
 126         struct ata_channel *wdc_cp = &cp->ata_channel;
 127         struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
 128         const char *intrstr;
 129         pci_intr_handle_t intrhandle;
 130         int i;
 131
 132         cp->compat = 0;
 133
 134         if (sc->sc_pci_ih == NULL) {
 135                 if (pci_intr_map(pa, &intrhandle) != 0) {
 136                         aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 137                             "couldn't map native-PCI interrupt\n");
 138                         goto bad;
 139                 }
 140                 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
 141                 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
 142                     intrhandle, IPL_BIO, pci_intr, sc);
 143                 if (sc->sc_pci_ih != NULL) {
 144                         aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 145                             "using %s for native-PCI interrupt\n",
 146                             intrstr ? intrstr : "unknown interrupt");
 147                 } else {
 148                         aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 149                             "couldn't establish native-PCI interrupt");
 150                         if (intrstr != NULL)
 151                                 aprint_error(" at %s", intrstr);
 152                         aprint_error("\n");
 153                         goto bad;
 154                 }
 155         }
 156         cp->ih = sc->sc_pci_ih;
 157         wdr->cmd_iot = sc->sc_ba5_st;
 158         if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
 159             ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
 160             &wdr->cmd_baseioh) != 0) {
 161                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 162                     "couldn't map %s channel cmd regs\n", cp->name);
 163                 goto bad;
 164         }
 165
 166         wdr->ctl_iot = sc->sc_ba5_st;
 167         if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
 168             ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
 169                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 170                     "couldn't map %s channel ctl regs\n", cp->name);
 171                 goto bad;
 172         }
 173         wdr->ctl_ioh = cp->ctl_baseioh;
 174
 175         for (i = 0; i < WDC_NREG + 2; i++) {
 176
 177                 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
 178                     artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
 179                     &wdr->cmd_iohs[i]) != 0) {
 180                         aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 181                             "couldn't subregion %s channel cmd regs\n",
 182                             cp->name);
 183                         goto bad;
 184                 }
 185         }
 186         wdr->data32iot = wdr->cmd_iot;
 187         wdr->data32ioh = wdr->cmd_iohs[0];
 188
 189         wdr->sata_iot = wdr->cmd_iot;
 190         wdr->sata_baseioh = wdr->cmd_baseioh;
 191
 192         if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
 193             ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1,
 194             &wdr->sata_status) != 0) {
 195                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 196                     "couldn't map channel %d sata_status regs\n",
 197                     wdc_cp->ch_channel);
 198                 goto bad;
 199         }
 200         if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
 201             ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1,
 202             &wdr->sata_error) != 0) {
 203                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 204                     "couldn't map channel %d sata_error regs\n",
 205                     wdc_cp->ch_channel);
 206                 goto bad;
 207         }
 208         if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
 209             ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1,
 210             &wdr->sata_control) != 0) {
 211                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 212                     "couldn't map channel %d sata_control regs\n",
 213                     wdc_cp->ch_channel);
 214                 goto bad;
 215         }
 216
 217         wdcattach(wdc_cp);
 218         return;
 219
 220 bad:
 221         wdc_cp->ch_flags |= ATACH_DISABLED;
 222         return;
 223 }
 224
 225 static int
 226 artisea_chansetup(struct pciide_softc *sc, int channel,
 227     pcireg_t interface)
 228 {
 229         struct pciide_channel *cp = &sc->pciide_channels[channel];
 230         sc->wdc_chanarray[channel] = &cp->ata_channel;
 231         cp->name = PCIIDE_CHANNEL_NAME(channel);
 232         cp->ata_channel.ch_channel = channel;
 233         cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
 234         cp->ata_channel.ch_queue =
 235             malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
 236         cp->ata_channel.ch_ndrive = 2;
 237         if (cp->ata_channel.ch_queue == NULL) {
 238                 aprint_error("%s %s channel: "
 239                     "can't allocate memory for command queue",
 240                 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name);
 241                 return 0;
 242         }
 243         return 1;
 244 }
 245
 246 static void
 247 artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
 248 {
 249         struct pciide_channel *pc;
 250         int chan;
 251         u_int32_t dma_ctl;
 252         u_int32_t cacheline_len;
 253
 254         aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 255             "bus-master DMA support present");
 256
 257         sc->sc_dma_ok = 1;
 258
 259         /*
 260          * Errata #4 says that if the cacheline length is not set correctly,
 261          * we can get corrupt MWI and Memory-Block-Write transactions.
 262          */
 263         cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
 264             PCI_BHLC_REG));
 265         if (cacheline_len == 0) {
 266                 aprint_verbose(", but unused (cacheline size not set in PCI conf)\n");
 267                 sc->sc_dma_ok = 0;
 268                 return;
 269         }
 270
 271         /*
 272          * Final step of the work-around is to force the DMA engine to use
 273          * the cache-line length information.
 274          */
 275         dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
 276         dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
 277         pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
 278
 279         sc->sc_wdcdev.dma_arg = sc;
 280         sc->sc_wdcdev.dma_init = pciide_dma_init;
 281         sc->sc_wdcdev.dma_start = pciide_dma_start;
 282         sc->sc_wdcdev.dma_finish = pciide_dma_finish;
 283         sc->sc_dma_iot = sc->sc_ba5_st;
 284         sc->sc_dmat = pa->pa_dmat;
 285
 286         if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
 287             PCIIDE_OPTIONS_NODMA) {
 288                 aprint_verbose(
 289                     ", but unused (forced off by config file)\n");
 290                 sc->sc_dma_ok = 0;
 291                 return;
 292         }
 293
 294         /*
 295          * Set up the default handles for the DMA registers.
 296          * Just reserve 32 bits for each handle, unless space
 297          * doesn't permit it.
 298          */
 299         for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
 300                 pc = &sc->pciide_channels[chan];
 301                 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
 302                     ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
 303                     &pc->dma_iohs[IDEDMA_CMD]) != 0 ||
 304                     bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
 305                     ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
 306                     &pc->dma_iohs[IDEDMA_CTL]) != 0 ||
 307                     bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
 308                     ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
 309                     &pc->dma_iohs[IDEDMA_TBL]) != 0) {
 310                         sc->sc_dma_ok = 0;
 311                         aprint_verbose(", but can't subregion registers\n");
 312                         return;
 313                 }
 314         }
 315
 316         aprint_verbose("\n");
 317 }
 318
 319 static void
 320 artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa)
 321 {
 322         struct pciide_channel *cp;
 323         bus_size_t cmdsize, ctlsize;
 324         pcireg_t interface;
 325         int channel;
 326
 327         interface = PCI_INTERFACE(pa->pa_class);
 328
 329         aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 330             "interface wired in DPA mode\n");
 331
 332         if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT,
 333             0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0)
 334                 return;
 335
 336         artisea_mapreg_dma(sc, pa);
 337
 338         sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
 339
 340         sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
 341         sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
 342         if (sc->sc_dma_ok) {
 343                 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
 344                 sc->sc_wdcdev.irqack = pciide_irqack;
 345                 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
 346                 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
 347         }
 348         sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
 349
 350         sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
 351         sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
 352         sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
 353
 354         wdc_allocate_regs(&sc->sc_wdcdev);
 355
 356         /*
 357          * Perform a quick check to ensure that the device isn't configured
 358          * in Spread-spectrum clocking mode.  This feature is buggy and has
 359          * been removed from the latest documentation.
 360          *
 361          * Note that although this bit is in the Channel regs, it's the same
 362          * for all channels, so we check it just once here.
 363          */
 364         if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
 365             ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
 366             ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
 367                 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 368                     "Spread-specturm clocking not supported by device\n");
 369                 return;
 370         }
 371
 372         /* Clear the LED0-only bit.  */
 373         pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0,
 374             pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) &
 375             ~SUECSR0_LED0_ONLY);
 376
 377         for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
 378              channel++) {
 379                 cp = &sc->pciide_channels[channel];
 380                 if (artisea_chansetup(sc, channel, interface) == 0)
 381                         continue;
 382                 /* XXX We can probably do interrupts more efficiently.  */
 383                 artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr);
 384         }
 385 }
 386
 387 static void
 388 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 389 {
 390         struct pciide_channel *cp;
 391         bus_size_t cmdsize, ctlsize;
 392         pcireg_t interface;
 393         int channel;
 394
 395         if (pciide_chipen(sc, pa) == 0)
 396                 return;
 397
 398         interface = PCI_INTERFACE(pa->pa_class);
 399
 400         if (interface == 0) {
 401                 artisea_chip_map_dpa (sc, pa);
 402                 return;
 403         }
 404
 405         aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 406             "bus-master DMA support present");
 407 #ifdef PCIIDE_I31244_DISABLEDMA
 408         if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 &&
 409             PCI_REVISION(pa->pa_class) == 0) {
 410                 aprint_verbose(" but disabled due to rev. 0");
 411                 sc->sc_dma_ok = 0;
 412         } else
 413 #endif
 414                 pciide_mapreg_dma(sc, pa);
 415         aprint_verbose("\n");
 416
 417         /*
 418          * XXX Configure LEDs to show activity.
 419          */
 420
 421         sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
 422         sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
 423         if (sc->sc_dma_ok) {
 424                 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
 425                 sc->sc_wdcdev.irqack = pciide_irqack;
 426                 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
 427                 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
 428         }
 429         sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
 430
 431         sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
 432         sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
 433
 434         wdc_allocate_regs(&sc->sc_wdcdev);
 435
 436         for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
 437              channel++) {
 438                 cp = &sc->pciide_channels[channel];
 439                 if (pciide_chansetup(sc, channel, interface) == 0)
 440                         continue;
 441                 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
 442                     pciide_pci_intr);
 443         }
 444 }