sys/dev/pci/cxgb_common.h

   1 /**************************************************************************
   2
   3 Copyright (c) 2007, Chelsio Inc.
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Neither the name of the Chelsio Corporation nor the names of its
  13     contributors may be used to endorse or promote products derived from
  14     this software without specific prior written permission.
  15
  16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26 POSSIBILITY OF SUCH DAMAGE.
  27
  28 $FreeBSD: src/sys/dev/cxgb/common/cxgb_common.h,v 1.7 2007/09/09 01:28:03 kmacy Exp $
  29
  30 ***************************************************************************/
  31 #ifndef __CHELSIO_COMMON_H
  32 #define __CHELSIO_COMMON_H
  33
  34 #ifdef CONFIG_DEFINED
  35 #include <cxgb_osdep.h>
  36 #else
  37 #ifdef __FreeBSD__
  38 #include <dev/cxgb/cxgb_osdep.h>
  39 #endif
  40 #ifdef __NetBSD__
  41 #include <dev/pci/cxgb_osdep.h>
  42 // ??? #include <dev/pci/cxgb_toedev.h>
  43 #endif
  44 #endif
  45
  46 enum {
  47     MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
  48     EEPROMSIZE     = 8192,  /* Serial EEPROM size */
  49     SERNUM_LEN     = 16,    /* Serial # length */
  50     RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
  51     TCB_SIZE       = 128,   /* TCB size */
  52     NMTUS          = 16,    /* size of MTU table */
  53     NCCTRL_WIN     = 32,    /* # of congestion control windows */
  54     NTX_SCHED      = 8,     /* # of HW Tx scheduling queues */
  55     PROTO_SRAM_LINES = 128, /* size of protocol sram */
  56     MAX_NPORTS     = 4,
  57     TP_TMR_RES     = 200,
  58     TP_SRAM_OFFSET = 4096,  /* TP SRAM content offset in eeprom */
  59     TP_SRAM_LEN    = 2112,  /* TP SRAM content offset in eeprom */
  60 };
  61
  62 #define MAX_RX_COALESCING_LEN 12288U
  63
  64 enum {
  65     PAUSE_RX      = 1 << 0,
  66     PAUSE_TX      = 1 << 1,
  67     PAUSE_AUTONEG = 1 << 2
  68 };
  69
  70 enum {
  71     SUPPORTED_IRQ      = 1 << 24
  72 };
  73
  74 enum {                            /* adapter interrupt-maintained statistics */
  75     STAT_ULP_CH0_PBL_OOB,
  76     STAT_ULP_CH1_PBL_OOB,
  77     STAT_PCI_CORR_ECC,
  78
  79     IRQ_NUM_STATS             /* keep last */
  80 };
  81
  82 enum {
  83     TP_VERSION_MAJOR    = 1,
  84     TP_VERSION_MINOR    = 1,
  85     TP_VERSION_MICRO    = 0
  86 };
  87
  88 #define S_TP_VERSION_MAJOR      16
  89 #define M_TP_VERSION_MAJOR      0xFF
  90 #define V_TP_VERSION_MAJOR(x)       ((x) << S_TP_VERSION_MAJOR)
  91 #define G_TP_VERSION_MAJOR(x)       \
  92         (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
  93
  94 #define S_TP_VERSION_MINOR      8
  95 #define M_TP_VERSION_MINOR      0xFF
  96 #define V_TP_VERSION_MINOR(x)       ((x) << S_TP_VERSION_MINOR)
  97 #define G_TP_VERSION_MINOR(x)       \
  98         (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
  99
 100 #define S_TP_VERSION_MICRO      0
 101 #define M_TP_VERSION_MICRO      0xFF
 102 #define V_TP_VERSION_MICRO(x)       ((x) << S_TP_VERSION_MICRO)
 103 #define G_TP_VERSION_MICRO(x)       \
 104         (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
 105
 106 enum {
 107     FW_VERSION_MAJOR = 4,
 108     FW_VERSION_MINOR = 7,
 109     FW_VERSION_MICRO = 0
 110 };
 111
 112 enum {
 113     SGE_QSETS = 8,            /* # of SGE Tx/Rx/RspQ sets */
 114     SGE_RXQ_PER_SET = 2,      /* # of Rx queues per set */
 115     SGE_TXQ_PER_SET = 3       /* # of Tx queues per set */
 116 };
 117
 118 enum sge_context_type {           /* SGE egress context types */
 119     SGE_CNTXT_RDMA  = 0,
 120     SGE_CNTXT_ETH   = 2,
 121     SGE_CNTXT_OFLD  = 4,
 122     SGE_CNTXT_CTRL  = 5
 123 };
 124
 125 enum {
 126     AN_PKT_SIZE    = 32,      /* async notification packet size */
 127     IMMED_PKT_SIZE = 48       /* packet size for immediate data */
 128 };
 129
 130 struct sg_ent {                   /* SGE scatter/gather entry */
 131     u32 len[2];
 132     u64 addr[2];
 133 };
 134
 135 #ifndef SGE_NUM_GENBITS
 136 /* Must be 1 or 2 */
 137 # define SGE_NUM_GENBITS 2
 138 #endif
 139
 140 #define TX_DESC_FLITS 16U
 141 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
 142
 143 struct cphy;
 144
 145 struct mdio_ops {
 146     int  (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
 147              int reg_addr, unsigned int *val);
 148         int  (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
 149               int reg_addr, unsigned int val);
 150 };
 151
 152 struct adapter_info {
 153     unsigned char          nports0;        /* # of ports on channel 0 */
 154     unsigned char          nports1;        /* # of ports on channel 1 */
 155     unsigned char          phy_base_addr;  /* MDIO PHY base address */
 156     unsigned char          mdien:1;
 157     unsigned char          mdiinv:1;
 158     unsigned int           gpio_out;       /* GPIO output settings */
 159     unsigned int           gpio_intr;      /* GPIO IRQ enable mask */
 160     unsigned long          caps;           /* adapter capabilities */
 161     const struct mdio_ops *mdio_ops;       /* MDIO operations */
 162     const char            *desc;           /* product description */
 163 };
 164
 165 struct port_type_info {
 166     void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
 167              const struct mdio_ops *ops);
 168     unsigned int caps;
 169     const char *desc;
 170 };
 171
 172 struct mc5_stats {
 173     unsigned long parity_err;
 174     unsigned long active_rgn_full;
 175     unsigned long nfa_srch_err;
 176     unsigned long unknown_cmd;
 177     unsigned long reqq_parity_err;
 178     unsigned long dispq_parity_err;
 179     unsigned long del_act_empty;
 180 };
 181
 182 struct mc7_stats {
 183     unsigned long corr_err;
 184     unsigned long uncorr_err;
 185     unsigned long parity_err;
 186     unsigned long addr_err;
 187 };
 188
 189 struct mac_stats {
 190     u64 tx_octets;            /* total # of octets in good frames */
 191     u64 tx_octets_bad;        /* total # of octets in error frames */
 192     u64 tx_frames;            /* all good frames */
 193     u64 tx_mcast_frames;      /* good multicast frames */
 194     u64 tx_bcast_frames;      /* good broadcast frames */
 195     u64 tx_pause;             /* # of transmitted pause frames */
 196     u64 tx_deferred;          /* frames with deferred transmissions */
 197     u64 tx_late_collisions;   /* # of late collisions */
 198     u64 tx_total_collisions;  /* # of total collisions */
 199     u64 tx_excess_collisions; /* frame errors from excessive collissions */
 200     u64 tx_underrun;          /* # of Tx FIFO underruns */
 201     u64 tx_len_errs;          /* # of Tx length errors */
 202     u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
 203     u64 tx_excess_deferral;   /* # of frames with excessive deferral */
 204     u64 tx_fcs_errs;          /* # of frames with bad FCS */
 205
 206     u64 tx_frames_64;         /* # of Tx frames in a particular range */
 207     u64 tx_frames_65_127;
 208     u64 tx_frames_128_255;
 209     u64 tx_frames_256_511;
 210     u64 tx_frames_512_1023;
 211     u64 tx_frames_1024_1518;
 212     u64 tx_frames_1519_max;
 213
 214     u64 rx_octets;            /* total # of octets in good frames */
 215     u64 rx_octets_bad;        /* total # of octets in error frames */
 216     u64 rx_frames;            /* all good frames */
 217     u64 rx_mcast_frames;      /* good multicast frames */
 218     u64 rx_bcast_frames;      /* good broadcast frames */
 219     u64 rx_pause;             /* # of received pause frames */
 220     u64 rx_fcs_errs;          /* # of received frames with bad FCS */
 221     u64 rx_align_errs;        /* alignment errors */
 222     u64 rx_symbol_errs;       /* symbol errors */
 223     u64 rx_data_errs;         /* data errors */
 224     u64 rx_sequence_errs;     /* sequence errors */
 225     u64 rx_runt;              /* # of runt frames */
 226     u64 rx_jabber;            /* # of jabber frames */
 227     u64 rx_short;             /* # of short frames */
 228     u64 rx_too_long;          /* # of oversized frames */
 229     u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
 230
 231     u64 rx_frames_64;         /* # of Rx frames in a particular range */
 232     u64 rx_frames_65_127;
 233     u64 rx_frames_128_255;
 234     u64 rx_frames_256_511;
 235     u64 rx_frames_512_1023;
 236     u64 rx_frames_1024_1518;
 237     u64 rx_frames_1519_max;
 238
 239     u64 rx_cong_drops;        /* # of Rx drops due to SGE congestion */
 240
 241     unsigned long tx_fifo_parity_err;
 242     unsigned long rx_fifo_parity_err;
 243     unsigned long tx_fifo_urun;
 244     unsigned long rx_fifo_ovfl;
 245     unsigned long serdes_signal_loss;
 246     unsigned long xaui_pcs_ctc_err;
 247     unsigned long xaui_pcs_align_change;
 248
 249     unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
 250     unsigned long num_resets;  /* # times reset due to stuck TX */
 251 };
 252
 253 struct tp_mib_stats {
 254     u32 ipInReceive_hi;
 255     u32 ipInReceive_lo;
 256     u32 ipInHdrErrors_hi;
 257     u32 ipInHdrErrors_lo;
 258     u32 ipInAddrErrors_hi;
 259     u32 ipInAddrErrors_lo;
 260     u32 ipInUnknownProtos_hi;
 261     u32 ipInUnknownProtos_lo;
 262     u32 ipInDiscards_hi;
 263     u32 ipInDiscards_lo;
 264     u32 ipInDelivers_hi;
 265     u32 ipInDelivers_lo;
 266     u32 ipOutRequests_hi;
 267     u32 ipOutRequests_lo;
 268     u32 ipOutDiscards_hi;
 269     u32 ipOutDiscards_lo;
 270     u32 ipOutNoRoutes_hi;
 271     u32 ipOutNoRoutes_lo;
 272     u32 ipReasmTimeout;
 273     u32 ipReasmReqds;
 274     u32 ipReasmOKs;
 275     u32 ipReasmFails;
 276
 277     u32 reserved[8];
 278
 279     u32 tcpActiveOpens;
 280     u32 tcpPassiveOpens;
 281     u32 tcpAttemptFails;
 282     u32 tcpEstabResets;
 283     u32 tcpOutRsts;
 284     u32 tcpCurrEstab;
 285     u32 tcpInSegs_hi;
 286     u32 tcpInSegs_lo;
 287     u32 tcpOutSegs_hi;
 288     u32 tcpOutSegs_lo;
 289     u32 tcpRetransSeg_hi;
 290     u32 tcpRetransSeg_lo;
 291     u32 tcpInErrs_hi;
 292     u32 tcpInErrs_lo;
 293     u32 tcpRtoMin;
 294     u32 tcpRtoMax;
 295 };
 296
 297 struct tp_params {
 298     unsigned int nchan;          /* # of channels */
 299     unsigned int pmrx_size;      /* total PMRX capacity */
 300     unsigned int pmtx_size;      /* total PMTX capacity */
 301     unsigned int cm_size;        /* total CM capacity */
 302     unsigned int chan_rx_size;   /* per channel Rx size */
 303     unsigned int chan_tx_size;   /* per channel Tx size */
 304     unsigned int rx_pg_size;     /* Rx page size */
 305     unsigned int tx_pg_size;     /* Tx page size */
 306     unsigned int rx_num_pgs;     /* # of Rx pages */
 307     unsigned int tx_num_pgs;     /* # of Tx pages */
 308     unsigned int ntimer_qs;      /* # of timer queues */
 309     unsigned int tre;            /* log2 of core clocks per TP tick */
 310     unsigned int dack_re;        /* DACK timer resolution */
 311 };
 312
 313 struct qset_params {                   /* SGE queue set parameters */
 314     unsigned int polling;          /* polling/interrupt service for rspq */
 315     unsigned int lro;              /* large receive offload */
 316     unsigned int coalesce_nsecs;   /* irq coalescing timer */
 317     unsigned int rspq_size;        /* # of entries in response queue */
 318     unsigned int fl_size;          /* # of entries in regular free list */
 319     unsigned int jumbo_size;       /* # of entries in jumbo free list */
 320     unsigned int txq_size[SGE_TXQ_PER_SET];  /* Tx queue sizes */
 321     unsigned int cong_thres;       /* FL congestion threshold */
 322     unsigned int vector;           /* Interrupt (line or vector) number */
 323 };
 324
 325 struct sge_params {
 326     unsigned int max_pkt_size;     /* max offload pkt size */
 327     struct qset_params qset[SGE_QSETS];
 328 };
 329
 330 struct mc5_params {
 331     unsigned int mode;       /* selects MC5 width */
 332     unsigned int nservers;   /* size of server region */
 333     unsigned int nfilters;   /* size of filter region */
 334     unsigned int nroutes;    /* size of routing region */
 335 };
 336
 337 /* Default MC5 region sizes */
 338 enum {
 339     DEFAULT_NSERVERS = 512,
 340     DEFAULT_NFILTERS = 128
 341 };
 342
 343 /* MC5 modes, these must be non-0 */
 344 enum {
 345     MC5_MODE_144_BIT = 1,
 346     MC5_MODE_72_BIT  = 2
 347 };
 348
 349 /* MC5 min active region size */
 350 enum { MC5_MIN_TIDS = 16 };
 351
 352 struct vpd_params {
 353     unsigned int cclk;
 354     unsigned int mclk;
 355     unsigned int uclk;
 356     unsigned int mdc;
 357     unsigned int mem_timing;
 358     u8 sn[SERNUM_LEN + 1];
 359     u8 eth_base[6];
 360     u8 port_type[MAX_NPORTS];
 361     unsigned short xauicfg[2];
 362 };
 363
 364 struct pci_params {
 365     unsigned int   vpd_cap_addr;
 366     unsigned int   pcie_cap_addr;
 367     unsigned short speed;
 368     unsigned char  width;
 369     unsigned char  variant;
 370 };
 371
 372 enum {
 373     PCI_VARIANT_PCI,
 374     PCI_VARIANT_PCIX_MODE1_PARITY,
 375     PCI_VARIANT_PCIX_MODE1_ECC,
 376     PCI_VARIANT_PCIX_266_MODE2,
 377     PCI_VARIANT_PCIE
 378 };
 379
 380 struct adapter_params {
 381     struct sge_params sge;
 382     struct mc5_params mc5;
 383     struct tp_params  tp;
 384     struct vpd_params vpd;
 385     struct pci_params pci;
 386
 387     const struct adapter_info *info;
 388
 389 #ifdef CONFIG_CHELSIO_T3_CORE
 390     unsigned short mtus[NMTUS];
 391     unsigned short a_wnd[NCCTRL_WIN];
 392     unsigned short b_wnd[NCCTRL_WIN];
 393 #endif
 394     unsigned int   nports;              /* # of ethernet ports */
 395     unsigned int   chan_map;            /* bitmap of in-use Tx channels */
 396     unsigned int   stats_update_period; /* MAC stats accumulation period */
 397     unsigned int   linkpoll_period;     /* link poll period in 0.1s */
 398     unsigned int   rev;                 /* chip revision */
 399     unsigned int   offload;
 400 };
 401
 402 enum {                      /* chip revisions */
 403     T3_REV_A  = 0,
 404     T3_REV_B  = 2,
 405     T3_REV_B2 = 3,
 406     T3_REV_C  = 4,
 407 };
 408
 409 struct trace_params {
 410     u32 sip;
 411         u32 sip_mask;
 412     u32 dip;
 413         u32 dip_mask;
 414     u16 sport;
 415     u16 sport_mask;
 416     u16 dport;
 417     u16 dport_mask;
 418     u32 vlan:12;
 419     u32 vlan_mask:12;
 420     u32 intf:4;
 421     u32 intf_mask:4;
 422     u8  proto;
 423     u8  proto_mask;
 424 };
 425
 426 struct link_config {
 427     unsigned int   supported;        /* link capabilities */
 428     unsigned int   advertising;      /* advertised capabilities */
 429         unsigned short requested_speed;  /* speed user has requested */
 430     unsigned short speed;            /* actual link speed */
 431         unsigned char  requested_duplex; /* duplex user has requested */
 432     unsigned char  duplex;           /* actual link duplex */
 433     unsigned char  requested_fc;     /* flow control user has requested */
 434     unsigned char  fc;               /* actual link flow control */
 435     unsigned char  autoneg;          /* autonegotiating? */
 436     unsigned int link_ok;          /* link up? */
 437 };
 438
 439 #define SPEED_INVALID   0xffff
 440 #define DUPLEX_INVALID  0xff
 441
 442 struct mc5 {
 443     adapter_t *adapter;
 444     unsigned int tcam_size;
 445     unsigned char part_type;
 446     unsigned char parity_enabled;
 447     unsigned char mode;
 448     struct mc5_stats stats;
 449 };
 450
 451 static inline unsigned int t3_mc5_size(const struct mc5 *p)
 452 {
 453     return p->tcam_size;
 454 }
 455
 456 struct mc7 {
 457     adapter_t *adapter;     /* backpointer to adapter */
 458     unsigned int size;      /* memory size in bytes */
 459     unsigned int width;     /* MC7 interface width */
 460     unsigned int offset;    /* register address offset for MC7 instance */
 461     const char *name;       /* name of MC7 instance */
 462     struct mc7_stats stats; /* MC7 statistics */
 463 };
 464
 465 static inline unsigned int t3_mc7_size(const struct mc7 *p)
 466 {
 467     return p->size;
 468 }
 469
 470 struct cmac {
 471     adapter_t *adapter;
 472     unsigned int offset;
 473     unsigned char nucast;    /* # of address filters for unicast MACs */
 474     unsigned char multiport; /* multiple ports connected to this MAC */
 475     unsigned char ext_port;  /* external MAC port */
 476     unsigned char promisc_map;  /* which external ports are promiscuous */
 477     unsigned int tx_tcnt;
 478     unsigned int tx_xcnt;
 479     u64 tx_mcnt;
 480     unsigned int rx_xcnt;
 481     unsigned int rx_ocnt;
 482     u64 rx_mcnt;
 483     unsigned int toggle_cnt;
 484     unsigned int txen;
 485     u64 rx_pause;
 486     struct mac_stats stats;
 487 };
 488
 489 enum {
 490     MAC_DIRECTION_RX = 1,
 491     MAC_DIRECTION_TX = 2,
 492     MAC_RXFIFO_SIZE  = 32768
 493 };
 494
 495 /* IEEE 802.3ae specified MDIO devices */
 496 enum {
 497     MDIO_DEV_PMA_PMD = 1,
 498     MDIO_DEV_WIS     = 2,
 499     MDIO_DEV_PCS     = 3,
 500     MDIO_DEV_XGXS    = 4
 501 };
 502
 503 /* PHY loopback direction */
 504 enum {
 505     PHY_LOOPBACK_TX = 1,
 506     PHY_LOOPBACK_RX = 2
 507 };
 508
 509 /* PHY interrupt types */
 510 enum {
 511     cphy_cause_link_change = 1,
 512     cphy_cause_fifo_error = 2
 513 };
 514
 515 /* PHY operations */
 516 struct cphy_ops {
 517     void (*destroy)(struct cphy *phy);
 518     int (*reset)(struct cphy *phy, int wait);
 519
 520     int (*intr_enable)(struct cphy *phy);
 521     int (*intr_disable)(struct cphy *phy);
 522     int (*intr_clear)(struct cphy *phy);
 523     int (*intr_handler)(struct cphy *phy);
 524
 525     int (*autoneg_enable)(struct cphy *phy);
 526     int (*autoneg_restart)(struct cphy *phy);
 527
 528     int (*advertise)(struct cphy *phy, unsigned int advertise_map);
 529     int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
 530     int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
 531     int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
 532                    int *duplex, int *fc);
 533     int (*power_down)(struct cphy *phy, int enable);
 534 };
 535
 536 /* A PHY instance */
 537 struct cphy {
 538     int addr;                            /* PHY address */
 539     adapter_t *adapter;                  /* associated adapter */
 540     unsigned long fifo_errors;           /* FIFO over/under-flows */
 541     const struct cphy_ops *ops;          /* PHY operations */
 542     int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
 543              int reg_addr, unsigned int *val);
 544     int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
 545               int reg_addr, unsigned int val);
 546 };
 547
 548 /* Convenience MDIO read/write wrappers */
 549 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
 550                 unsigned int *valp)
 551 {
 552         return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
 553 }
 554
 555 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
 556                  unsigned int val)
 557 {
 558         return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
 559 }
 560
 561 /* Convenience initializer */
 562 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
 563                  int phy_addr, struct cphy_ops *phy_ops,
 564                  const struct mdio_ops *mdio_ops)
 565 {
 566     phy->adapter = adapter;
 567     phy->addr    = phy_addr;
 568     phy->ops     = phy_ops;
 569     if (mdio_ops) {
 570         phy->mdio_read  = mdio_ops->read;
 571         phy->mdio_write = mdio_ops->write;
 572     }
 573 }
 574
 575 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
 576 #define MAC_STATS_ACCUM_SECS 180
 577
 578 /* The external MAC needs accumulation every 30 seconds */
 579 #define VSC_STATS_ACCUM_SECS 30
 580
 581 #define XGM_REG(reg_addr, idx) \
 582     ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
 583
 584 struct addr_val_pair {
 585     unsigned int reg_addr;
 586     unsigned int val;
 587 };
 588
 589 #ifdef CONFIG_DEFINED
 590 #include <cxgb_adapter.h>
 591 #else
 592 #ifdef __FreeBSD__
 593 #include <dev/cxgb/cxgb_adapter.h>
 594 #endif
 595 #ifdef __NetBSD__
 596 #include <dev/pci/cxgb_adapter.h>
 597 #endif
 598 #endif
 599
 600 #ifndef PCI_VENDOR_ID_CHELSIO
 601 # define PCI_VENDOR_ID_CHELSIO 0x1425
 602 #endif
 603
 604 #define for_each_port(adapter, iter) \
 605     for (iter = 0; iter < (adapter)->params.nports; ++iter)
 606
 607 #define adapter_info(adap) ((adap)->params.info)
 608
 609 static inline int uses_xaui(const adapter_t *adap)
 610 {
 611     return adapter_info(adap)->caps & SUPPORTED_AUI;
 612 }
 613
 614 static inline int is_10G(const adapter_t *adap)
 615 {
 616     return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
 617 }
 618
 619 static inline int is_offload(const adapter_t *adap)
 620 {
 621 #ifdef CONFIG_CHELSIO_T3_CORE
 622     return adap->params.offload;
 623 #else
 624     return 0;
 625 #endif
 626 }
 627
 628 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
 629 {
 630     return adap->params.vpd.cclk / 1000;
 631 }
 632
 633 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
 634                           unsigned int ticks)
 635 {
 636     return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
 637 }
 638
 639 static inline unsigned int is_pcie(const adapter_t *adap)
 640 {
 641     return adap->params.pci.variant == PCI_VARIANT_PCIE;
 642 }
 643
 644 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
 645 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
 646            unsigned int offset);
 647 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
 648             int attempts, int delay, u32 *valp);
 649
 650 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
 651                   int polarity, int attempts, int delay)
 652 {
 653     return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
 654                    delay, NULL);
 655 }
 656
 657 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
 658             unsigned int set);
 659 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
 660 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
 661 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
 662
 663 void t3_intr_enable(adapter_t *adapter);
 664 void t3_intr_disable(adapter_t *adapter);
 665 void t3_intr_clear(adapter_t *adapter);
 666 void t3_port_intr_enable(adapter_t *adapter, int idx);
 667 void t3_port_intr_disable(adapter_t *adapter, int idx);
 668 void t3_port_intr_clear(adapter_t *adapter, int idx);
 669 int t3_slow_intr_handler(adapter_t *adapter);
 670 int t3_phy_intr_handler(adapter_t *adapter);
 671
 672 void t3_link_changed(adapter_t *adapter, int port_id);
 673 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
 674 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
 675 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
 676 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
 677 int t3_seeprom_wp(adapter_t *adapter, int enable);
 678 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
 679           u32 *data, int byte_oriented);
 680 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
 681 int t3_check_tpsram_version(adapter_t *adapter);
 682 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
 683 int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size);
 684 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
 685 int t3_check_fw_version(adapter_t *adapter);
 686 int t3_init_hw(adapter_t *adapter, u32 fw_params);
 687 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
 688 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
 689 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
 690 void t3_led_ready(adapter_t *adapter);
 691 void t3_fatal_err(adapter_t *adapter);
 692 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
 693 void t3_enable_filters(adapter_t *adap);
 694 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
 695            const u16 *rspq);
 696 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
 697 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
 698 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
 699 void t3_port_failover(adapter_t *adapter, int port);
 700 void t3_failover_done(adapter_t *adapter, int port);
 701 void t3_failover_clear(adapter_t *adapter);
 702 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
 703             unsigned int *valp);
 704 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
 705            u64 *buf);
 706
 707 int t3_mac_reset(struct cmac *mac);
 708 void t3b_pcs_reset(struct cmac *mac);
 709 int t3_mac_enable(struct cmac *mac, int which);
 710 int t3_mac_disable(struct cmac *mac, int which);
 711 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
 712 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
 713 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
 714 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
 715 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
 716 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
 717                    int fc);
 718 int t3b2_mac_watchdog_task(struct cmac *mac);
 719
 720 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
 721 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
 722         unsigned int nroutes);
 723 void t3_mc5_intr_handler(struct mc5 *mc5);
 724 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
 725               u32 *buf);
 726
 727 #ifdef CONFIG_CHELSIO_T3_CORE
 728 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
 729 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
 730 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
 731 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
 732 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
 733                   unsigned short alpha[NCCTRL_WIN],
 734           unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
 735 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
 736 void t3_get_cong_cntl_tab(adapter_t *adap,
 737               unsigned short incr[NMTUS][NCCTRL_WIN]);
 738 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
 739                 int filter_index, int invert, int enable);
 740 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
 741 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
 742 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
 743              unsigned int *ipg);
 744 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
 745 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
 746              unsigned int start, unsigned int n);
 747 #endif
 748
 749 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
 750 void t3_sge_init(adapter_t *adap, struct sge_params *p);
 751 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
 752                enum sge_context_type type, int respq, u64 base_addr,
 753                unsigned int size, unsigned int token, int gen,
 754                unsigned int cidx);
 755 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
 756             u64 base_addr, unsigned int size, unsigned int esize,
 757             unsigned int cong_thres, int gen, unsigned int cidx);
 758 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
 759              u64 base_addr, unsigned int size,
 760              unsigned int fl_thres, int gen, unsigned int cidx);
 761 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
 762             unsigned int size, int rspq, int ovfl_mode,
 763             unsigned int credits, unsigned int credit_thres);
 764 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
 765 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
 766 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
 767 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
 768 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
 769 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
 770 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
 771 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
 772 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
 773               unsigned int credits);
 774
 775 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
 776 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
 777 int t3_vsc7323_init(adapter_t *adap, int nports);
 778 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
 779 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
 780 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
 781 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
 782 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
 783 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
 784
 785 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 786                const struct mdio_ops *mdio_ops);
 787 void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 788              const struct mdio_ops *mdio_ops);
 789 void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 790              const struct mdio_ops *mdio_ops);
 791 void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 792              const struct mdio_ops *mdio_ops);
 793 void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 794             const struct mdio_ops *mdio_ops);
 795 void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
 796                  const struct mdio_ops *mdio_ops);
 797 #endif /* __CHELSIO_COMMON_H */