sys/dev/pci/hptide.c

   1 /*      $NetBSD: hptide.c,v 1.25 2008/03/18 20:46:36 cube Exp $ */
   2
   3 /*
   4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.25 2008/03/18 20:46:36 cube Exp $");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32
  33 #include <dev/pci/pcivar.h>
  34 #include <dev/pci/pcidevs.h>
  35 #include <dev/pci/pciidereg.h>
  36 #include <dev/pci/pciidevar.h>
  37 #include <dev/pci/pciide_hpt_reg.h>
  38
  39 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*);
  40 static void hpt_setup_channel(struct ata_channel*);
  41 static int  hpt_pci_intr(void *);
  42
  43 static int  hptide_match(device_t, cfdata_t, void *);
  44 static void hptide_attach(device_t, device_t, void *);
  45
  46 CFATTACH_DECL_NEW(hptide, sizeof(struct pciide_softc),
  47     hptide_match, hptide_attach, NULL, NULL);
  48
  49 static const struct pciide_product_desc pciide_triones_products[] =  {
  50         { PCI_PRODUCT_TRIONES_HPT302,
  51           0,
  52           NULL,
  53           hpt_chip_map
  54         },
  55         { PCI_PRODUCT_TRIONES_HPT366,
  56           0,
  57           NULL,
  58           hpt_chip_map,
  59         },
  60         { PCI_PRODUCT_TRIONES_HPT371,
  61           0,
  62           NULL,
  63           hpt_chip_map,
  64         },
  65         { PCI_PRODUCT_TRIONES_HPT372A,
  66           0,
  67           NULL,
  68           hpt_chip_map
  69         },
  70         { PCI_PRODUCT_TRIONES_HPT374,
  71           0,
  72           NULL,
  73           hpt_chip_map
  74         },
  75         { 0,
  76           0,
  77           NULL,
  78           NULL
  79         }
  80 };
  81
  82 static int
  83 hptide_match(device_t parent, cfdata_t match, void *aux)
  84 {
  85         struct pci_attach_args *pa = aux;
  86
  87         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) {
  88                 if (pciide_lookup_product(pa->pa_id, pciide_triones_products))
  89                         return (2);
  90         }
  91         return (0);
  92 }
  93
  94 static void
  95 hptide_attach(device_t parent, device_t self, void *aux)
  96 {
  97         struct pci_attach_args *pa = aux;
  98         struct pciide_softc *sc = device_private(self);
  99
 100         sc->sc_wdcdev.sc_atac.atac_dev = self;
 101
 102         pciide_common_attach(sc, pa,
 103             pciide_lookup_product(pa->pa_id, pciide_triones_products));
 104
 105 }
 106
 107 static void
 108 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
 109 {
 110         struct pciide_channel *cp;
 111         int i, compatchan, revision;
 112         pcireg_t interface;
 113         bus_size_t cmdsize, ctlsize;
 114
 115         if (pciide_chipen(sc, pa) == 0)
 116                 return;
 117
 118         revision = PCI_REVISION(pa->pa_class);
 119         aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 120             "Triones/Highpoint ");
 121         switch (sc->sc_pp->ide_product) {
 122         case PCI_PRODUCT_TRIONES_HPT302:
 123                 aprint_normal("HPT302 IDE Controller\n");
 124                 break;
 125         case PCI_PRODUCT_TRIONES_HPT371:
 126                 aprint_normal("HPT371 IDE Controller\n");
 127                 break;
 128         case PCI_PRODUCT_TRIONES_HPT374:
 129                 aprint_normal("HPT374 IDE Controller\n");
 130                 break;
 131         case PCI_PRODUCT_TRIONES_HPT372A:
 132                 aprint_normal("HPT372A IDE Controller\n");
 133                 break;
 134         case PCI_PRODUCT_TRIONES_HPT366:
 135                 if (revision == HPT372_REV)
 136                         aprint_normal("HPT372 IDE Controller\n");
 137                 else if (revision == HPT370_REV)
 138                         aprint_normal("HPT370 IDE Controller\n");
 139                 else if (revision == HPT370A_REV)
 140                         aprint_normal("HPT370A IDE Controller\n");
 141                 else if (revision == HPT368_REV)
 142                         aprint_normal("HPT368 IDE Controller\n");
 143                 else if (revision == HPT366_REV)
 144                         aprint_normal("HPT366 IDE Controller\n");
 145                 else
 146                         aprint_normal("unknown HPT IDE controller rev %d\n",
 147                             revision);
 148                 break;
 149         default:
 150                 aprint_normal("unknown HPT IDE controller 0x%x\n",
 151                     sc->sc_pp->ide_product);
 152         }
 153
 154         /*
 155          * when the chip is in native mode it identifies itself as a
 156          * 'misc mass storage'. Fake interface in this case.
 157          */
 158         if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
 159                 interface = PCI_INTERFACE(pa->pa_class);
 160         } else {
 161                 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
 162                     PCIIDE_INTERFACE_PCI(0);
 163                 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 164                     (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
 165                      revision == HPT372_REV)) ||
 166                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
 167                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
 168                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
 169                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
 170                         interface |= PCIIDE_INTERFACE_PCI(1);
 171         }
 172
 173         aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
 174             "bus-master DMA support present");
 175         pciide_mapreg_dma(sc, pa);
 176         aprint_verbose("\n");
 177         sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
 178         if (sc->sc_dma_ok) {
 179                 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
 180                 sc->sc_wdcdev.irqack = pciide_irqack;
 181         }
 182         sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
 183         sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
 184
 185         sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel;
 186         sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
 187         if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 188             (revision == HPT366_REV || revision == HPT368_REV)) {
 189                 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
 190                 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
 191         } else {
 192                 sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
 193                 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
 194                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
 195                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
 196                     sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
 197                     (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 198                     revision == HPT372_REV))
 199                         sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
 200                 else
 201                         sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
 202         }
 203
 204         wdc_allocate_regs(&sc->sc_wdcdev);
 205
 206         for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
 207                 cp = &sc->pciide_channels[i];
 208                 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) {
 209                         compatchan = i;
 210                         if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
 211                            HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
 212                                 aprint_normal(
 213                                     "%s: %s channel ignored (disabled)\n",
 214                                     device_xname(
 215                                       sc->sc_wdcdev.sc_atac.atac_dev),
 216                                     cp->name);
 217                                 cp->ata_channel.ch_flags |= ATACH_DISABLED;
 218                                 continue;
 219                         }
 220                 } else {
 221                         /*
 222                          * The 366 has 2 PCI IDE functions, one for primary and
 223                          * one for secondary. So we need to call
 224                          * pciide_mapregs_compat() with the real channel.
 225                          */
 226                         if (pa->pa_function == 0)
 227                                 compatchan = 0;
 228                         else if (pa->pa_function == 1)
 229                                 compatchan = 1;
 230                         else {
 231                                 aprint_error_dev(
 232                                     sc->sc_wdcdev.sc_atac.atac_dev,
 233                                     "unexpected PCI function %d\n",
 234                                     pa->pa_function);
 235                                 return;
 236                         }
 237                 }
 238                 if (pciide_chansetup(sc, i, interface) == 0)
 239                         continue;
 240                 if (interface & PCIIDE_INTERFACE_PCI(i)) {
 241                         pciide_mapregs_native(pa, cp, &cmdsize,
 242                             &ctlsize, hpt_pci_intr);
 243                 } else {
 244                         pciide_mapregs_compat(pa, cp, compatchan,
 245                             &cmdsize, &ctlsize);
 246                         if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
 247                                 pciide_map_compat_intr(pa, cp,
 248                                     sc->sc_cy_compatchan);
 249                 }
 250                 wdcattach(&cp->ata_channel);
 251         }
 252         if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 253             (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
 254              revision == HPT372_REV)) ||
 255             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
 256             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
 257             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
 258             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
 259                 /*
 260                  * HPT370_REV and highter has a bit to disable interrupts,
 261                  * make sure to clear it
 262                  */
 263                 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
 264                     pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
 265                     ~HPT_CSEL_IRQDIS);
 266         }
 267         /* set clocks, etc (mandatory on 372/4, optional otherwise) */
 268         if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
 269              revision == HPT372_REV ) ||
 270             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
 271             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
 272             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
 273             sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
 274                 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
 275                     (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
 276                      HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
 277         return;
 278 }
 279
 280 static void
 281 hpt_setup_channel(struct ata_channel *chp)
 282 {
 283         struct ata_drive_datas *drvp;
 284         int drive, s;
 285         int cable;
 286         u_int32_t before, after;
 287         u_int32_t idedma_ctl;
 288         struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
 289         struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
 290         int revision =
 291              PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
 292         const u_int32_t *tim_pio, *tim_dma, *tim_udma;
 293
 294         cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
 295
 296         /* setup DMA if needed */
 297         pciide_channel_dma_setup(cp);
 298
 299         idedma_ctl = 0;
 300
 301         /* select the timing arrays for the chip */
 302         switch (sc->sc_pp->ide_product) {
 303         case PCI_PRODUCT_TRIONES_HPT374:
 304                 tim_udma = hpt374_udma;
 305                 tim_dma = hpt374_dma;
 306                 tim_pio = hpt374_pio;
 307                 break;
 308         case PCI_PRODUCT_TRIONES_HPT302:
 309         case PCI_PRODUCT_TRIONES_HPT371:
 310         case PCI_PRODUCT_TRIONES_HPT372A:
 311                 tim_udma = hpt372_udma;
 312                 tim_dma = hpt372_dma;
 313                 tim_pio = hpt372_pio;
 314                 break;
 315         case PCI_PRODUCT_TRIONES_HPT366:
 316         default:
 317                 switch (revision) {
 318                 case HPT372_REV:
 319                         tim_udma = hpt372_udma;
 320                         tim_dma = hpt372_dma;
 321                         tim_pio = hpt372_pio;
 322                         break;
 323                 case HPT370_REV:
 324                 case HPT370A_REV:
 325                         tim_udma = hpt370_udma;
 326                         tim_dma = hpt370_dma;
 327                         tim_pio = hpt370_pio;
 328                         break;
 329                 case HPT368_REV:
 330                 case HPT366_REV:
 331                 default:
 332                         tim_udma = hpt366_udma;
 333                         tim_dma = hpt366_dma;
 334                         tim_pio = hpt366_pio;
 335                         break;
 336                 }
 337         }
 338
 339         /* Per drive settings */
 340         for (drive = 0; drive < chp->ch_ndrive; drive++) {
 341                 drvp = &chp->ch_drive[drive];
 342                 /* If no drive, skip */
 343                 if ((drvp->drive_flags & DRIVE) == 0)
 344                         continue;
 345                 before = pci_conf_read(sc->sc_pc, sc->sc_tag,
 346                                         HPT_IDETIM(chp->ch_channel, drive));
 347
 348                 /* add timing values, setup DMA if needed */
 349                 if (drvp->drive_flags & DRIVE_UDMA) {
 350                         /* use Ultra/DMA */
 351                         s = splbio();
 352                         drvp->drive_flags &= ~DRIVE_DMA;
 353                         splx(s);
 354                         if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 &&
 355                             drvp->UDMA_mode > 2)
 356                                 drvp->UDMA_mode = 2;
 357                         after = tim_udma[drvp->UDMA_mode];
 358                         idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 359                 } else if (drvp->drive_flags & DRIVE_DMA) {
 360                         /*
 361                          * use Multiword DMA.
 362                          * Timings will be used for both PIO and DMA, so adjust
 363                          * DMA mode if needed
 364                          */
 365                         if (drvp->PIO_mode >= 3 &&
 366                             (drvp->DMA_mode + 2) > drvp->PIO_mode) {
 367                                 drvp->DMA_mode = drvp->PIO_mode - 2;
 368                         }
 369                         after = tim_dma[drvp->DMA_mode];
 370                         idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
 371                 } else {
 372                         /* PIO only */
 373                         after = tim_pio[drvp->PIO_mode];
 374                 }
 375                 pci_conf_write(sc->sc_pc, sc->sc_tag,
 376                     HPT_IDETIM(chp->ch_channel, drive), after);
 377                 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x "
 378                     "(BIOS 0x%08x)\n", device_xname(drvp->drv_softc),
 379                     after, before), DEBUG_PROBE);
 380         }
 381         if (idedma_ctl != 0) {
 382                 /* Add software bits in status register */
 383                 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
 384                     idedma_ctl);
 385         }
 386 }
 387
 388 static int
 389 hpt_pci_intr(void *arg)
 390 {
 391         struct pciide_softc *sc = arg;
 392         struct pciide_channel *cp;
 393         struct ata_channel *wdc_cp;
 394         int rv = 0;
 395         int dmastat, i, crv;
 396
 397         for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
 398                 cp = &sc->pciide_channels[i];
 399                 dmastat = bus_space_read_1(sc->sc_dma_iot,
 400                     cp->dma_iohs[IDEDMA_CTL], 0);
 401                 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
 402                     IDEDMA_CTL_INTR)
 403                         continue;
 404                 wdc_cp = &cp->ata_channel;
 405                 crv = wdcintr(wdc_cp);
 406                 if (crv == 0) {
 407                         aprint_error("%s:%d: bogus intr\n",
 408                             device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i);
 409                         bus_space_write_1(sc->sc_dma_iot,
 410                             cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
 411                 } else
 412                         rv = 1;
 413         }
 414         return rv;
 415 }