sys/dev/pci/if_dgereg.h

   1 /*      $NetBSD: if_dgereg.h,v 1.2 2005/12/11 12:22:49 christos Exp $   */
   2
   3 /*
   4  * Copyright (c) 2004, SUNET, Swedish University Computer Network.
   5  * All rights reserved.
   6  *
   7  * Written by Anders Magnusson for SUNET, Swedish University Computer Network.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      SUNET, Swedish University Computer Network.
  21  * 4. The name of SUNET may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /* PCI registers */
  38 #define DGE_PCI_BAR     0x10
  39 #define DGE_PCIX_CMD    0xe4
  40
  41 /* PCIX CMD bits */
  42 #define PCIX_MMRBC_MSK  0x000c0000
  43 #define PCIX_MMRBC_512  0x00000000
  44 #define PCIX_MMRBC_1024 0x00040000
  45 #define PCIX_MMRBC_2048 0x00080000
  46 #define PCIX_MMRBC_4096 0x000c0000
  47
  48
  49 /* General registers */
  50 #define DGE_CTRL0       0x000
  51 #define DGE_CTRL1       0x008
  52 #define DGE_STATUS      0x010
  53 #define DGE_EECD        0x018
  54 #define DGE_MFS         0x020
  55
  56 /* Interrupt control registers */
  57 #define DGE_ICR         0x080
  58 #define DGE_ICS         0x088
  59 #define DGE_IMS         0x090
  60 #define DGE_IMC         0x098
  61
  62 /* Receiver control registers */
  63 #define DGE_RCTL        0x0100
  64 #define DGE_FCRTL       0x0108
  65 #define DGE_FCRTH       0x0110
  66 #define DGE_RDBAL       0x0118
  67 #define DGE_RDBAH       0x011c
  68 #define DGE_RDLEN       0x0120
  69 #define DGE_RDH         0x0128
  70 #define DGE_RDT         0x0130
  71 #define DGE_RDTR        0x0138
  72 #define DGE_RXDCTL      0x0140
  73 #define DGE_RAIDC       0x0148
  74 #define DGE_RXCSUM      0x0158
  75 #define DGE_RAL         0x0180
  76 #define DGE_RAH         0x0184
  77 #define DGE_MTA         0x0200
  78
  79 /* Transmit control registers */
  80 #define DGE_TCTL        0x0600
  81 #define DGE_TDBAL       0x0608
  82 #define DGE_TDBAH       0x060c
  83 #define DGE_TDLEN       0x0610
  84 #define DGE_TDH         0x0618
  85 #define DGE_TDT         0x0620
  86 #define DGE_TIDV        0x0628
  87 #define DGE_TXDCTL      0x0630
  88 #define DGE_TSPMT       0x0638
  89 #define DGE_PAP         0x0640
  90
  91 /* PHY communications */
  92 #define DGE_MDIO        0x0758
  93 #define DGE_MDIRW       0x0760
  94
  95 /* Statistics */
  96 #define DGE_TPRL        0x2000
  97 #define DGE_TPRH        0x2004
  98
  99 /*
 100  * CTRL0 bit definitions.
 101  */
 102 #define CTRL0_LRST      0x00000008
 103 #define CTRL0_JFE       0x00000010
 104 #define CTRL0_XLE       0x00000020
 105 #define CTRL0_MDCS      0x00000040
 106 #define CTRL0_CMDC      0x00000080
 107 #define CTRL0_SDP0      0x00040000
 108 #define CTRL0_SDP1      0x00080000
 109 #define CTRL0_SDP2      0x00100000
 110 #define CTRL0_SDP3      0x00200000
 111 #define CTRL0_SDP0_DIR  0x00400000
 112 #define CTRL0_SDP1_DIR  0x00800000
 113 #define CTRL0_SDP2_DIR  0x01000000
 114 #define CTRL0_SDP3_DIR  0x02000000
 115 #define CTRL0_RST       0x04000000
 116 #define CTRL0_RPE       0x08000000
 117 #define CTRL0_TPE       0x10000000
 118 #define CTRL0_VME       0x40000000
 119
 120 /*
 121  * CTRL1 bit definitions.
 122  */
 123 #define CTRL1_EE_RST    0x00002000
 124 /*
 125  * STATUS bit definitions.
 126  */
 127 #define STATUS_LINKUP   0x00000002
 128 #define STATUS_BUS64    0x00001000
 129 #define STATUS_PCIX     0x00002000
 130 #define STATUS_PCIX_MSK 0x0000C000
 131 #define STATUS_PCIX_66  0x00000000
 132 #define STATUS_PCIX_100 0x00004000
 133 #define STATUS_PCIX_133 0x00008000
 134
 135 /*
 136  * Interrupt control registers bit definitions.
 137  */
 138 #define ICR_TXDW        0x00000001
 139 #define ICR_TXQE        0x00000002
 140 #define ICR_LSC         0x00000004
 141 #define ICR_RXSEQ       0x00000008
 142 #define ICR_RXDMT0      0x00000010
 143 #define ICR_RXO         0x00000040
 144 #define ICR_RXT0        0x00000080
 145 #define ICR_GPI0        0x00000800
 146 #define ICR_GPI1        0x00001000
 147 #define ICR_GPI2        0x00002000
 148 #define ICR_GPI3        0x00004000
 149
 150 /*
 151  * RCTL bit definitions.
 152  */
 153 #define RCTL_RXEN       0x00000002
 154 #define RCTL_SBP        0x00000004
 155 #define RCTL_UPE        0x00000008
 156 #define RCTL_MPE        0x00000010
 157 #define RCTL_RDMTS_12   0x00000000
 158 #define RCTL_RDMTS_14   0x00000100
 159 #define RCTL_RDMTS_18   0x00000200
 160 #define RCTL_BAM        0x00008000
 161 #define RCTL_BSIZE_2k   0x00000000
 162 #define RCTL_BSIZE_4k   0x00010000
 163 #define RCTL_BSIZE_8k   0x00020000
 164 #define RCTL_BSIZE_16k  0x00030000
 165 #define RCTL_VFE        0x00040000
 166 #define RCTL_CFIEN      0x00080000
 167 #define RCTL_CFI        0x00100000
 168 #define RCTL_RPDA_MC    0x00400000
 169 #define RCTL_CFF        0x00800000
 170 #define RCTL_SECRC      0x04000000
 171
 172 #define RCTL_MO(x)      ((x) << 12)
 173
 174 #define FCRTL_XONE      0x80000000
 175
 176 /*
 177  * RXDCTL macros.
 178  */
 179 #define RXDCTL_PTHRESH(x) (x)
 180 #define RXDCTL_HTHRESH(x) ((x) << 9)
 181 #define RXDCTL_WTHRESH(x) ((x) << 18)
 182
 183 /*
 184  * RXCSUM bit definitions.
 185  */
 186 #define RXCSUM_IPOFL    0x00000100
 187 #define RXCSUM_TUOFL    0x00000200
 188
 189 /*
 190  * RAH/RAL macros.
 191  */
 192 #define RAH_AV          0x80000000
 193 #define RA_TABSIZE      16              /* # of direct-filtered addresses */
 194 #define RA_ADDR(reg, idx) ((reg) + (idx) * 8)
 195
 196 /*
 197  * MTA macros.
 198  */
 199 #define MC_TABSIZE      128             /* Size of multicast array table */
 200
 201 /*
 202  * TCTL bit definitions.
 203  */
 204 #define TCTL_TCE        0x00000001
 205 #define TCTL_TXEN       0x00000002
 206 #define TCTL_TPDE       0x00000004
 207
 208 /*
 209  * TXDCTL macros.
 210  */
 211 #define TXDCTL_PTHRESH(x) (x)
 212 #define TXDCTL_HTHRESH(x) ((x) << 8)
 213 #define TXDCTL_WTHRESH(x) ((x) << 16)
 214
 215 /*
 216  * MDIO communication bits.
 217  * This is for "New Protocol".
 218  */
 219 #define MDIO_REG(x)     ((x) & 0xffff)
 220 #define MDIO_DEV(x)     ((x) << 16)
 221 #define MDIO_PHY(x)     ((x) << 21)
 222 #define MDIO_ADDR       0
 223 #define MDIO_WRITE      (1 << 26)
 224 #define MDIO_READ       (1 << 27)
 225 #define MDIO_OLD_P      (1 << 28)
 226 #define MDIO_CMD        (1 << 30)
 227
 228 /*
 229  * EEPROM stuff.
 230  * The 10GbE card uses an ATMEL AT93C46 in 64x16 mode,
 231  * see http://www.atmel.com/dyn/resources/prod_documents/doc0172.pdf
 232  */
 233 /* EEPROM bit masks in the EECD register */
 234 #define EECD_SK         0x01
 235 #define EECD_CS         0x02
 236 #define EECD_DI         0x04
 237 #define EECD_DO         0x08
 238
 239 #define EEPROM_SIZE     64      /* 64 word in length */
 240 #define EEPROM_CKSUM    0xbaba
 241
 242 #define EE_ADDR01       0       /* Offset in EEPROM for MAC address 0-1 */
 243 #define EE_ADDR23       1       /* Offset in EEPROM for MAC address 2-3 */
 244 #define EE_ADDR45       2       /* Offset in EEPROM for MAC address 4-5 */
 245
 246 /*
 247  * Transmit descriptor definitions.
 248  */
 249 struct dge_tdes {
 250         uint32_t dt_baddrl;     /* Lower 32 bits of buffer address */
 251         uint32_t dt_baddrh;     /* Upper 32 bits of buffer address */
 252         uint32_t dt_ctl;        /* Command/Type/Length */
 253         uint8_t  dt_status;     /* Transmitted data status info */
 254         uint8_t  dt_popts;      /* Packet options */
 255         uint16_t dt_vlan;       /* VLAN information */
 256 } __packed;
 257
 258 /*
 259  * Context transmit descriptor, "overlayed" on the above struct.
 260  */
 261 struct dge_ctdes {
 262 #if 0
 263         uint8_t  dc_ipcss;      /* IP checksum start */
 264         uint8_t  dc_ipcso;      /* IP checksum offset */
 265         uint16_t dc_ipcse;      /* IP checksum ending */
 266         uint8_t  dc_tucss;      /* TCP/UDP checksum start */
 267         uint8_t  dc_tucso;      /* TCP/UDP checksum offset */
 268         uint16_t dc_tucse;      /* TCP/UDP checksum ending */
 269         uint32_t dc_ctl;        /* Command/Type/Length (as above) */
 270         uint8_t  dc_status;     /* Status info (as above) */
 271         uint8_t  dc_hdrlen;     /* Header length */
 272         uint16_t dc_mss;        /* Maximum segment size */
 273 #else
 274         uint32_t dc_tcpip_ipcs; /* IP checksum context */
 275         uint32_t dc_tcpip_tucs; /* TCP/UDP checksum context */
 276         uint32_t dc_tcpip_cmdlen;
 277         uint32_t dc_tcpip_seg;  /* TCP segmentation context */
 278 #endif
 279 } __packed;
 280
 281 #define TDESC_DTYP_CTD  0x00000000
 282 #define TDESC_DTYP_DATA 0x00100000
 283 #define TDESC_DCMD_IDE  0x80000000
 284 #define TDESC_DCMD_VLE  0x40000000
 285 #define TDESC_DCMD_RS   0x08000000
 286 #define TDESC_DCMD_TSE  0x04000000
 287 #define TDESC_DCMD_EOP  0x01000000
 288 #define TDESC_TUCMD_IDE 0x80000000
 289 #define TDESC_TUCMD_RS  0x08000000
 290 #define TDESC_TUCMD_TSE 0x04000000
 291 #define TDESC_TUCMD_IP  0x02000000
 292 #define TDESC_TUCMD_TCP 0x01000000
 293
 294 #define DGE_TCPIP_IPCSS(x) (x)
 295 #define DGE_TCPIP_IPCSO(x) ((x) << 8)
 296 #define DGE_TCPIP_IPCSE(x) ((x) << 16)
 297 #define DGE_TCPIP_TUCSS(x) (x)
 298 #define DGE_TCPIP_TUCSO(x) ((x) << 8)
 299 #define DGE_TCPIP_TUCSE(x) ((x) << 16)
 300
 301 #define TDESC_STA_DD    0x01
 302
 303 #define TDESC_POPTS_TXSM 0x02
 304 #define TDESC_POPTS_IXSM 0x01
 305 /*
 306  * Receive descriptor definitions.
 307  */
 308 struct dge_rdes {
 309         uint32_t dr_baddrl;     /* Lower 32 bits of buffer address */
 310         uint32_t dr_baddrh;     /* Upper 32 bits of buffer address */
 311         uint16_t dr_len;        /* Length of receive packet */
 312         uint16_t dr_cksum;      /* Packet checksum */
 313         uint8_t  dr_status;     /* Received data status info */
 314         uint8_t  dr_errors;     /* Receive errors */
 315         uint16_t dr_special;    /* VLAN (802.1q) information */
 316 } __packed;
 317
 318 #define RDESC_STS_PIF   0x80    /* Exact filter match */
 319 #define RDESC_STS_IPCS  0x40    /* IP Checksum calculated */
 320 #define RDESC_STS_TCPCS 0x20    /* TCP checksum calculated */
 321 #define RDESC_STS_VP    0x08    /* Packet is 802.1q */
 322 #define RDESC_STS_IXSM  0x04    /* Ignore checksum */
 323 #define RDESC_STS_EOP   0x02    /* End of packet */
 324 #define RDESC_STS_DD    0x01    /* Descriptor done */
 325
 326 #define RDESC_ERR_RXE   0x80    /* RX data error */
 327 #define RDESC_ERR_IPE   0x40    /* IP checksum error */
 328 #define RDESC_ERR_TCPE  0x20    /* TCP/UDP checksum error */
 329 #define RDESC_ERR_P     0x08    /* Parity error */
 330 #define RDESC_ERR_SE    0x02    /* Symbol error */
 331 #define RDESC_ERR_CE    0x01    /* CRC/Alignment error */