sys/dev/pci/if_iwireg.h

   1 /*      $NetBSD: if_iwireg.h,v 1.18 2007/12/25 18:33:40 perry Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2004, 2005
   5  *      Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice unmodified, this list of conditions, and the following
  12  *    disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #define IWI_CMD_RING_COUNT      16
  31 #define IWI_TX_RING_COUNT       64
  32 #define IWI_RX_RING_COUNT       32
  33
  34 #define IWI_TX_DESC_SIZE        (sizeof (struct iwi_tx_desc))
  35 #define IWI_CMD_DESC_SIZE       (sizeof (struct iwi_cmd_desc))
  36
  37 #define IWI_CSR_INTR            0x0008
  38 #define IWI_CSR_INTR_MASK       0x000c
  39 #define IWI_CSR_INDIRECT_ADDR   0x0010
  40 #define IWI_CSR_INDIRECT_DATA   0x0014
  41 #define IWI_CSR_AUTOINC_ADDR    0x0018
  42 #define IWI_CSR_AUTOINC_DATA    0x001c
  43 #define IWI_CSR_RST             0x0020
  44 #define IWI_CSR_CTL             0x0024
  45 #define IWI_CSR_IO              0x0030
  46 #define IWI_CSR_CMD_BASE        0x0200
  47 #define IWI_CSR_CMD_SIZE        0x0204
  48 #define IWI_CSR_TX1_BASE        0x0208
  49 #define IWI_CSR_TX1_SIZE        0x020c
  50 #define IWI_CSR_TX2_BASE        0x0210
  51 #define IWI_CSR_TX2_SIZE        0x0214
  52 #define IWI_CSR_TX3_BASE        0x0218
  53 #define IWI_CSR_TX3_SIZE        0x021c
  54 #define IWI_CSR_TX4_BASE        0x0220
  55 #define IWI_CSR_TX4_SIZE        0x0224
  56 #define IWI_CSR_CMD_RIDX        0x0280
  57 #define IWI_CSR_TX1_RIDX        0x0284
  58 #define IWI_CSR_TX2_RIDX        0x0288
  59 #define IWI_CSR_TX3_RIDX        0x028c
  60 #define IWI_CSR_TX4_RIDX        0x0290
  61 #define IWI_CSR_RX_RIDX         0x02a0
  62 #define IWI_CSR_RX_BASE         0x0500
  63 #define IWI_CSR_ERRORLOG        0x0610
  64 #define IWI_CSR_TABLE0_SIZE     0x0700
  65 #define IWI_CSR_TABLE0_BASE     0x0704
  66 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE
  67 #define IWI_CSR_NODE_BASE       0x0c0c
  68 #define IWI_CSR_CMD_WIDX        0x0f80
  69 #define IWI_CSR_TX1_WIDX        0x0f84
  70 #define IWI_CSR_TX2_WIDX        0x0f88
  71 #define IWI_CSR_TX3_WIDX        0x0f8c
  72 #define IWI_CSR_TX4_WIDX        0x0f90
  73 #define IWI_CSR_RX_WIDX         0x0fa0
  74 #define IWI_CSR_READ_INT        0x0ff4
  75
  76 /* flags for IWI_CSR_INTR */
  77 #define IWI_INTR_RX_DONE        0x00000002
  78 #define IWI_INTR_CMD_DONE       0x00000800
  79 #define IWI_INTR_TX1_DONE       0x00001000
  80 #define IWI_INTR_TX2_DONE       0x00002000
  81 #define IWI_INTR_TX3_DONE       0x00004000
  82 #define IWI_INTR_TX4_DONE       0x00008000
  83 #define IWI_INTR_FW_INITED      0x01000000
  84 #define IWI_INTR_RADIO_OFF      0x04000000
  85 #define IWI_INTR_FATAL_ERROR    0x40000000
  86 #define IWI_INTR_PARITY_ERROR   0x80000000
  87
  88 #define IWI_INTR_MASK                                           \
  89         (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE |                 \
  90          IWI_INTR_TX1_DONE | IWI_INTR_TX2_DONE |                \
  91          IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE |                \
  92          IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF |              \
  93          IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR)
  94
  95 /* flags for IWI_CSR_RST */
  96 #define IWI_RST_PRINCETON_RESET 0x00000001
  97 #define IWI_RST_STANDBY         0x00000004
  98 #define IWI_RST_LED_ACTIVITY    0x00000010      /* tx/rx traffic led */
  99 #define IWI_RST_LED_ASSOCIATED  0x00000020      /* station associated led */
 100 #define IWI_RST_LED_OFDM        0x00000040      /* ofdm/cck led */
 101 #define IWI_RST_SW_RESET        0x00000080
 102 #define IWI_RST_MASTER_DISABLED 0x00000100
 103 #define IWI_RST_STOP_MASTER     0x00000200
 104 #define IWI_RST_GATE_ODMA       0x02000000
 105 #define IWI_RST_GATE_IDMA       0x04000000
 106 #define IWI_RST_GATE_ADMA       0x20000000
 107
 108 /* flags for IWI_CSR_CTL */
 109 #define IWI_CTL_CLOCK_READY     0x00000001
 110 #define IWI_CTL_ALLOW_STANDBY   0x00000002
 111 #define IWI_CTL_INIT            0x00000004
 112
 113 /* flags for IWI_CSR_IO */
 114 #define IWI_IO_RADIO_ENABLED    0x00010000
 115
 116 /* flags for IWI_CSR_READ_INT */
 117 #define IWI_READ_INT_INIT_HOST  0x20000000
 118
 119 /* error log definitions */
 120 struct iwi_error {
 121         uint32_t        type;
 122         uint32_t        reserved2;
 123         uint32_t        reserved3;
 124         uint32_t        reserved4;
 125         uint32_t        reserved5;
 126         uint32_t        reserved6;
 127         uint32_t        reserved7;
 128 } __packed;
 129
 130 /* constants for command blocks */
 131 #define IWI_CB_DEFAULT_CTL      0x8cea0000
 132 #define IWI_CB_MAXDATALEN       8191
 133
 134 /* supported rates */
 135 #define IWI_RATE_DS1    10
 136 #define IWI_RATE_DS2    20
 137 #define IWI_RATE_DS5    55
 138 #define IWI_RATE_DS11   110
 139 #define IWI_RATE_OFDM6  13
 140 #define IWI_RATE_OFDM9  15
 141 #define IWI_RATE_OFDM12 5
 142 #define IWI_RATE_OFDM18 7
 143 #define IWI_RATE_OFDM24 9
 144 #define IWI_RATE_OFDM36 11
 145 #define IWI_RATE_OFDM48 1
 146 #define IWI_RATE_OFDM54 3
 147
 148 /* firmware binary image header */
 149 struct iwi_firmware_ohdr {
 150         uint32_t        version;
 151         uint32_t        mode;
 152 } __packed;
 153 #define IWI_FW_REQ_MAJOR        3
 154 #define IWI_FW_REQ_MINOR        0
 155 #define IWI_FW_GET_MAJOR(ver)   (((ver) & 0x00ff0000) >> 16)
 156 #define IWI_FW_GET_MINOR(ver)   (((ver) & 0xff000000) >> 24)
 157
 158 struct iwi_firmware_hdr {
 159         uint32_t        version;        /* version stamp */
 160         uint32_t        bsize;          /* size of boot image */
 161         uint32_t        usize;          /* size of ucode image */
 162         uint32_t        fsize;          /* size of firmware image */
 163 } __packed;
 164
 165 struct iwi_hdr {
 166         uint8_t type;
 167 #define IWI_HDR_TYPE_DATA       0
 168 #define IWI_HDR_TYPE_COMMAND    1
 169 #define IWI_HDR_TYPE_NOTIF      3
 170 #define IWI_HDR_TYPE_FRAME      9
 171
 172         uint8_t seq;
 173         uint8_t flags;
 174 #define IWI_HDR_FLAG_IRQ        0x04
 175
 176         uint8_t reserved;
 177 } __packed;
 178
 179 struct iwi_notif {
 180         uint32_t        reserved[2];
 181         uint8_t         type;
 182 #define IWI_NOTIF_TYPE_ASSOCIATION      10
 183 #define IWI_NOTIF_TYPE_AUTHENTICATION   11
 184 #define IWI_NOTIF_TYPE_SCAN_CHANNEL     12
 185 #define IWI_NOTIF_TYPE_SCAN_COMPLETE    13
 186 #define IWI_NOTIF_TYPE_FRAG_LENGTH      14
 187 #define IWI_NOTIF_TYPE_LINK_QUALITY     15      /* "link deterioration" */
 188 #define IWI_NOTIF_TYPE_BEACON           17      /* beacon state, e.g. miss */
 189 #define IWI_NOTIF_TYPE_TGI_TX_KEY       18      /* WPA transmit key */
 190 #define IWI_NOTIF_TYPE_CALIBRATION      20
 191 #define IWI_NOTIF_TYPE_NOISE            25
 192
 193         uint8_t         flags;
 194         uint16_t        len;
 195 } __packed;
 196
 197 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */
 198 struct iwi_notif_authentication {
 199         uint8_t state;
 200 #define IWI_AUTH_FAIL           0
 201 #define IWI_AUTH_SENT_1         1               /* tx first frame */
 202 #define IWI_AUTH_RECV_2         2               /* rx second frame */
 203 #define IWI_AUTH_SEQ1_PASS      3               /* 1st exchange passed */
 204 #define IWI_AUTH_SEQ1_FAIL      4               /* 1st exchange failed */
 205 #define IWI_AUTH_SUCCESS        9
 206
 207 } __packed;
 208
 209 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */
 210 struct iwi_notif_association {
 211         uint8_t                 state;
 212 #define IWI_ASSOC_FAIL          0
 213 #define IWI_ASSOC_SUCCESS       12
 214
 215         struct ieee80211_frame  frame;
 216         uint16_t                capinfo;
 217         uint16_t                status;
 218         uint16_t                associd;
 219 } __packed;
 220
 221 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */
 222 struct iwi_notif_scan_channel {
 223         uint8_t nchan;
 224         uint8_t reserved[47];
 225 } __packed;
 226
 227 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */
 228 struct iwi_notif_scan_complete {
 229         uint8_t type;
 230         uint8_t nchan;
 231         uint8_t status;
 232         uint8_t reserved;
 233 } __packed;
 234
 235 /* structure for notification IWI_NOTIF_TYPE_BEACON */
 236 struct iwi_notif_beacon_state {
 237         uint32_t        state;
 238 #define IWI_BEACON_MISS         1
 239
 240         uint32_t        number;
 241 } __packed;
 242
 243 /* received frame header */
 244 struct iwi_frame {
 245         uint32_t        reserved1[2];
 246         uint8_t         chan;
 247         uint8_t         status;
 248         uint8_t         rate;
 249         uint8_t         rssi;   /* receiver signal strength indicator */
 250         uint8_t         agc;    /* automatic gain control */
 251         uint8_t         rssi_dbm;
 252         uint16_t        signal;
 253         uint16_t        noise;
 254         uint8_t         antenna;
 255         uint8_t         control;
 256         uint8_t         reserved2[2];
 257         uint16_t        len;
 258 } __packed;
 259
 260 /* header for transmission */
 261 struct iwi_tx_desc {
 262         struct iwi_hdr  hdr;
 263         uint32_t        reserved1;
 264         uint8_t         station;
 265         uint8_t         reserved2[3];
 266         uint8_t         cmd;
 267 #define IWI_DATA_CMD_TX 0x0b
 268
 269         uint8_t         seq;
 270         uint16_t        len;
 271         uint8_t         priority;
 272         uint8_t         flags;
 273 #define IWI_DATA_FLAG_SHPREAMBLE        0x04
 274 #define IWI_DATA_FLAG_NO_WEP            0x20
 275 #define IWI_DATA_FLAG_NEED_ACK          0x80
 276
 277         uint8_t         xflags;
 278 #define IWI_DATA_XFLAG_CCK      0x01
 279 #define IWI_DATA_XFLAG_OFDM     0x00
 280 #define IWI_DATA_XFLAG_QOS      0x10
 281
 282         uint8_t         wep_txkey;
 283 #define IWI_DATA_KEY_WEP40              0x40
 284 #define IWI_DATA_KEY_WEP104             0x80
 285
 286         uint8_t         wepkey[IEEE80211_KEYBUF_SIZE];
 287         uint8_t         rate;
 288         uint8_t         antenna;
 289         uint8_t         reserved3[10];
 290         struct ieee80211_qosframe_addr4 wh;
 291         uint32_t        iv;
 292         uint32_t        eiv;
 293         uint32_t        nseg;
 294 #define IWI_MAX_NSEG    6
 295
 296         uint32_t        seg_addr[IWI_MAX_NSEG];
 297         uint16_t        seg_len[IWI_MAX_NSEG];
 298 } __packed;
 299
 300 /* command */
 301 struct iwi_cmd_desc {
 302         struct iwi_hdr  hdr;
 303         uint8_t         type;
 304 #define IWI_CMD_ENABLE                          2
 305 #define IWI_CMD_SET_CONFIGURATION               6
 306 #define IWI_CMD_SET_ESSID                       8
 307 #define IWI_CMD_SET_MAC_ADDRESS                 11
 308 #define IWI_CMD_SET_RTS_THRESHOLD               15
 309 #define IWI_CMD_SET_FRAG_THRESHOLD              16
 310 #define IWI_CMD_SET_POWER_MODE                  17
 311 #define IWI_CMD_SET_WEP_KEY                     18
 312 #define IWI_CMD_ASSOCIATE                       21
 313 #define IWI_CMD_SET_RATES                       22
 314 #define IWI_CMD_ABORT_SCAN                      23
 315 #define IWI_CMD_SET_WME_PARAMS                  25
 316 #define IWI_CMD_SCAN_V2                         26
 317 #define IWI_CMD_SET_OPTIE                       31
 318 #define IWI_CMD_DISABLE                         33
 319 #define IWI_CMD_SET_IV                          34
 320 #define IWI_CMD_SET_TX_POWER                    35
 321 #define IWI_CMD_SET_SENSITIVITY                 42
 322 #define IWI_CMD_SET_WMEIE                       84
 323
 324         uint8_t         len;
 325         uint16_t        reserved;
 326         uint8_t         data[120];
 327 } __packed;
 328
 329 /* node information (IBSS) */
 330 struct iwi_ibssnode {
 331         uint8_t bssid[IEEE80211_ADDR_LEN];
 332         uint8_t reserved[2];
 333 } __packed;
 334
 335 /* constants for 'mode' fields */
 336 #define IWI_MODE_11A    0
 337 #define IWI_MODE_11B    1
 338 #define IWI_MODE_11G    2
 339
 340 /* possible values for command IWI_CMD_SET_POWER_MODE */
 341 #define IWI_POWER_MODE_CAM      0       /* no power save */
 342 #define IWI_POWER_MODE_PSP      3
 343 #define IWI_POWER_MODE_MAX      5       /* max power save operation */
 344
 345 /* structure for command IWI_CMD_SET_RATES */
 346 struct iwi_rateset {
 347         uint8_t mode;
 348         uint8_t nrates;
 349         uint8_t type;
 350 #define IWI_RATESET_TYPE_NEGOTIATED     0
 351 #define IWI_RATESET_TYPE_SUPPORTED      1
 352
 353         uint8_t reserved;
 354 #define IWI_RATESET_SIZE        12
 355         uint8_t rates[IWI_RATESET_SIZE];
 356 } __packed;
 357
 358 /* structure for command IWI_CMD_SET_TX_POWER */
 359 struct iwi_txpower {
 360         uint8_t nchan;
 361         uint8_t mode;
 362         struct {
 363                 uint8_t chan;
 364                 uint8_t power;
 365 #define IWI_TXPOWER_MAX         20
 366 #define IWI_TXPOWER_RATIO       (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX)
 367         } __packed chan[37];
 368 } __packed;
 369
 370 /* structure for command IWI_CMD_ASSOCIATE */
 371 struct iwi_associate {
 372         uint8_t         chan;           /* channel # */
 373         uint8_t         auth;           /* type and key */
 374 #define IWI_AUTH_OPEN   0
 375 #define IWI_AUTH_SHARED 1
 376 #define IWI_AUTH_NONE   3
 377
 378         uint8_t         type;           /* request */
 379 #define IWI_HC_ASSOC            0
 380 #define IWI_HC_REASSOC          1
 381 #define IWI_HC_DISASSOC         2
 382 #define IWI_HC_IBSS_START       3
 383 #define IWI_HC_IBSS_RECONF      4
 384 #define IWI_HC_DISASSOC_QUIET   5
 385
 386         uint8_t         reserved1;
 387         uint16_t        policy;
 388 #define IWI_POLICY_WME  1
 389 #define IWI_POLICY_WPA  2
 390
 391         uint8_t         plen;           /* preamble length */
 392 #define IWI_ASSOC_SHPREAMBLE    (1 << 2) /* ogre */
 393
 394         uint8_t         mode;
 395         uint8_t         bssid[IEEE80211_ADDR_LEN];
 396         uint8_t         tstamp[8];
 397         uint16_t        capinfo;
 398         uint16_t        lintval;
 399         uint16_t        intval;
 400         uint8_t         dst[IEEE80211_ADDR_LEN];
 401         uint32_t        reserved3;
 402         uint16_t        reserved4;
 403 } __packed;
 404
 405 #define IWI_SCAN_CHANNELS       54
 406
 407 #define IWI_SCAN_TYPE_FIRST_BEACON      0
 408 #define IWI_SCAN_TYPE_PASSIVE           1
 409 #define IWI_SCAN_TYPE_ACTIVE_DIRECT     2
 410 #define IWI_SCAN_TYPE_ACTIVE_BROADCAST  3
 411 #define IWI_SCAN_TYPE_ACTIVE_BDIRECT    4
 412 #define IWI_SCAN_TYPES                  5
 413
 414 #define iwi_scan_type_set(s, i, t)                      \
 415         do {                                            \
 416                 if ((i) % 2 == 0)                       \
 417                         (s).type[(i) / 2].lsn = (t);    \
 418                 else                                    \
 419                         (s).type[(i) / 2].msn = (t);    \
 420         } while(0)
 421
 422 /* structure for command IWI_CMD_SCAN_V2 */
 423 struct iwi_scan_v2 {
 424         u_int32_t       fsidx;
 425         u_int8_t        channels[IWI_SCAN_CHANNELS];
 426 #define IWI_CHAN_5GHZ   (0 << 6)
 427 #define IWI_CHAN_2GHZ   (1 << 6)
 428
 429         struct {
 430 #if _BYTE_ORDER == _LITTLE_ENDIAN
 431                 u_int8_t msn:4;
 432                 u_int8_t lsn:4;
 433 #else
 434                 u_int8_t lsn:4;
 435                 u_int8_t msn:4;
 436 #endif
 437         } __packed type[IWI_SCAN_CHANNELS / 2];
 438
 439         u_int8_t        reserved1;
 440         u_int16_t       dwelltime[IWI_SCAN_TYPES];
 441
 442 } __packed;
 443
 444 /* structure for command IWI_CMD_SET_CONFIGURATION */
 445 struct iwi_configuration {
 446         uint8_t bluetooth_coexistence;
 447         uint8_t reserved1;
 448         uint8_t answer_pbreq;
 449         uint8_t allow_invalid_frames;
 450         uint8_t multicast_enabled;
 451         uint8_t drop_unicast_unencrypted;
 452         uint8_t disable_unicast_decryption;
 453         uint8_t drop_multicast_unencrypted;
 454         uint8_t disable_multicast_decryption;
 455         uint8_t antenna;
 456 #define IWI_ANTENNA_AUTO        0       /* firmware selects best antenna */
 457 #define IWI_ANTENNA_A           1       /* use antenna A only */
 458 #define IWI_ANTENNA_B           3       /* use antenna B only */
 459 #define IWI_ANTENNA_SLOWDIV     2       /* slow diversity algorithm */
 460
 461         uint8_t include_crc;            /* include crc in rx'd frames */
 462         uint8_t use_protection;         /* auto-detect 11g operation */
 463         uint8_t protection_ctsonly;     /* use CTS-to-self protection */
 464         uint8_t enable_multicast_filtering;
 465         uint8_t bluetooth_threshold;    /* collision threshold */
 466         uint8_t silence_threshold;      /* silence over/under threshold */
 467         uint8_t allow_beacon_and_probe_resp;
 468         uint8_t allow_mgt;
 469         uint8_t noise_reported;         /* report noise stats to host */
 470         uint8_t reserved5;
 471 } __packed;
 472
 473 /* structure for command IWI_CMD_SET_WEP_KEY */
 474 struct iwi_wep_key {
 475         uint8_t cmd;
 476 #define IWI_WEP_KEY_CMD_SETKEY  0x08
 477
 478         uint8_t seq;
 479         uint8_t idx;
 480         uint8_t len;
 481         uint8_t key[IEEE80211_KEYBUF_SIZE];
 482 } __packed;
 483
 484 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */
 485
 486 /* structure for command IWI_CMD_SET_WME_PARAMS */
 487 struct iwi_wme_params {
 488         uint16_t        cwmin[WME_NUM_AC];
 489         uint16_t        cwmax[WME_NUM_AC];
 490         uint8_t         aifsn[WME_NUM_AC];
 491         uint8_t         acm[WME_NUM_AC];
 492         uint16_t        burst[WME_NUM_AC];
 493 } __packed;
 494
 495 #define IWI_MEM_START_ADDR      0x00300000
 496
 497 #define IWI_MEM_EEPROM_CTL      (IWI_MEM_START_ADDR + 0x40)
 498 #define IWI_MEM_EVENT_CTL       (IWI_MEM_START_ADDR + 0x04)
 499
 500 /*
 501  * led control bits
 502  */
 503 #define IWI_LED_ACTIVITY        0x00000010
 504 #define IWI_LED_ASSOCIATED      0x00000020
 505 #define IWI_LED_OFDM            0x00000040
 506
 507 #define IWI_LED_MASK    (IWI_LED_ACTIVITY | \
 508                                IWI_LED_ASSOCIATED | \
 509                                IWI_LED_OFDM)
 510
 511 #define IWI_LED_OFF(sc)                                                  \
 512         do {                                                             \
 513                 MEM_WRITE_4(sc, IWI_MEM_EVENT_CTL, ~IWI_LED_MASK); \
 514         } while (/* CONSTCOND */ 0)
 515
 516
 517 #define IWI_EEPROM_MAC          0x21
 518 #define IWI_EEPROM_NIC_TYPE     0x25
 519
 520 #define IWI_EEPROM_DELAY        1       /* minimum hold time (microsecond) */
 521
 522 #define IWI_EEPROM_C    (1 << 0)        /* Serial Clock */
 523 #define IWI_EEPROM_S    (1 << 1)        /* Chip Select */
 524 #define IWI_EEPROM_D    (1 << 2)        /* Serial data input */
 525 #define IWI_EEPROM_Q    (1 << 4)        /* Serial data output */
 526
 527 #define IWI_EEPROM_SHIFT_D      2
 528 #define IWI_EEPROM_SHIFT_Q      4
 529
 530 /*
 531  * control and status registers access macros
 532  */
 533 #define CSR_READ_1(sc, reg)                                             \
 534         bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
 535
 536 #define CSR_READ_2(sc, reg)                                             \
 537         bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
 538
 539 #define CSR_READ_4(sc, reg)                                             \
 540         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 541
 542 #define CSR_READ_REGION_4(sc, offset, datap, count)                     \
 543         bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset),     \
 544             (datap), (count))
 545
 546 #define CSR_WRITE_1(sc, reg, val)                                       \
 547         bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 548
 549 #define CSR_WRITE_2(sc, reg, val)                                       \
 550         bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 551
 552 #define CSR_WRITE_4(sc, reg, val)                                       \
 553         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 554
 555 #define CSR_WRITE_REGION_1(sc, offset, datap, count)                    \
 556         bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset),    \
 557             (datap), (count))
 558
 559 /*
 560  * indirect memory space access macros
 561  */
 562 #define MEM_WRITE_1(sc, addr, val) do {                                 \
 563         CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
 564         CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val));                \
 565 } while (/* CONSTCOND */0)
 566
 567 #define MEM_WRITE_2(sc, addr, val) do {                                 \
 568         CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
 569         CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val));                \
 570 } while (/* CONSTCOND */0)
 571
 572 #define MEM_WRITE_4(sc, addr, val) do {                                 \
 573         CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
 574         CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val));                \
 575 } while (/* CONSTCOND */0)
 576
 577 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do {                      \
 578         CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr));               \
 579         CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len));   \
 580 } while (/* CONSTCOND */0)
 581
 582 /*
 583  * EEPROM access macro
 584  */
 585 #define IWI_EEPROM_CTL(sc, val) do {                                    \
 586         MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val));                   \
 587         DELAY(IWI_EEPROM_DELAY);                                        \
 588 } while (/* CONSTCOND */0)