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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_lmc.c
blobeb2cfe8e3d62c7e0a5e89d6c417525246aedecc5
1 /* $NetBSD: if_lmc.c,v 1.47 2009/05/06 09:25:15 cegger Exp $ */
2
3 /*-
4 * Copyright (c) 2002-2006 David Boggs. <boggs@boggs.palo-alto.ca.us>
5 * All rights reserved.
6 *
7 * BSD LICENSE:
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * GNU GENERAL PUBLIC LICENSE:
31 *
32 * This program is free software; you can redistribute it and/or modify it
33 * under the terms of the GNU General Public License as published by the Free
34 * Software Foundation; either version 2 of the License, or (at your option)
35 * any later version.
36 *
37 * This program is distributed in the hope that it will be useful, but WITHOUT
38 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
39 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
40 * more details.
41 *
42 * You should have received a copy of the GNU General Public License along with
43 * this program; if not, write to the Free Software Foundation, Inc., 59
44 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
45 *
46 * DESCRIPTION:
47 *
48 * This is an open-source Unix device driver for PCI-bus WAN interface cards.
49 * It sends and receives packets in HDLC frames over synchronous links.
50 * A generic PC plus Unix plus some LMC cards makes an OPEN router.
51 * This driver works with FreeBSD, NetBSD, OpenBSD, BSD/OS and Linux.
52 * It has been tested on i386 (32-bit little-end), PowerPC (32-bit
53 * big-end), Sparc (64-bit big-end), and Alpha (64-bit little-end)
54 * architectures.
55 *
56 * HISTORY AND AUTHORS:
57 *
58 * Ron Crane had the neat idea to use a Fast Ethernet chip as a PCI
59 * interface and add an Ethernet-to-HDLC gate array to make a WAN card.
60 * David Boggs designed the Ethernet-to-HDLC gate arrays and PC cards.
61 * We did this at our company, LAN Media Corporation (LMC).
62 * SBE Corp aquired LMC and continues to make the cards.
63 *
64 * Since the cards use Tulip Ethernet chips, we started with Matt Thomas'
65 * ubiquitous "de" driver. Michael Graff stripped out the Ethernet stuff
66 * and added HSSI stuff. Basil Gunn ported it to Solaris (lost) and
67 * Rob Braun ported it to Linux. Andrew Stanley-Jones added support
68 * for three more cards and wrote the first version of lmcconfig.
69 * During 2002-5 David Boggs rewrote it and now feels responsible for it.
70 *
71 * RESPONSIBLE INDIVIDUAL:
72 *
73 * Send bug reports and improvements to <boggs@boggs.palo-alto.ca.us>.
74 */
75
76 # include <sys/cdefs.h>
77 __KERNEL_RCSID(0, "$NetBSD: if_lmc.c,v 1.47 2009/05/06 09:25:15 cegger Exp $");
78 # include <sys/param.h> /* OS version */
79 # include "opt_inet.h" /* INET6, INET */
80 # include "opt_altq_enabled.h" /* ALTQ */
81 # include "bpfilter.h" /* NBPFILTER */
82 # define IOREF_CSR 1 /* 1=IO refs; 0=MEM refs */
83 # define IFNET 1
84 # define NETDEV 0
85 # define NAPI 0
86 # define SPPP 1
87 # define P2P 0
88 # define GEN_HDLC 0
89 # define SYNC_PPP 0
90 # define NETGRAPH 0
91 # define DEVICE_POLLING 0
92 #
93 # include <sys/systm.h>
94 # include <sys/kernel.h>
95 # include <sys/module.h>
96 # include <sys/mbuf.h>
97 # include <sys/socket.h>
98 # include <sys/sockio.h>
99 # include <sys/device.h>
100 # include <sys/reboot.h>
101 # include <sys/kauth.h>
102 # include <sys/proc.h>
103 # include <net/if.h>
104 # include <net/if_types.h>
105 # include <net/if_media.h>
106 # include <net/netisr.h>
107 # include <sys/bus.h>
108 # include <sys/intr.h>
109 # include <machine/lock.h>
110 # include <machine/types.h>
111 # include <dev/pci/pcivar.h>
112 # include <uvm/uvm_extern.h>
113 # if INET || INET6
114 # include <netinet/in.h>
115 # include <netinet/in_var.h>
116 # endif
117 # if SPPP
118 # include <net/if_spppvar.h>
119 # endif
120 # if NBPFILTER
121 # include <net/bpf.h>
122 # endif
123 # if !defined(ALTQ)
124 # define ALTQ 0
125 # endif
126 /* and finally... */
127 # include "if_lmc.h"
128
129
130
131
132 /* The SROM is a generic 93C46 serial EEPROM (64 words by 16 bits). */
133 /* Data is set up before the RISING edge of CLK; CLK is parked low. */
134 static void /* context: process */
135 srom_shift_bits(softc_t *sc, u_int32_t data, u_int32_t len)
136 {
137 u_int32_t csr = READ_CSR(sc, TLP_SROM_MII);
138 for (; len>0; len--)
139 { /* MSB first */
140 if (data & (1<<(len-1)))
141 csr |= TLP_SROM_DIN; /* DIN setup */
142 else
143 csr &= ~TLP_SROM_DIN; /* DIN setup */
144 WRITE_CSR(sc, TLP_SROM_MII, csr);
145 csr |= TLP_SROM_CLK; /* CLK rising edge */
146 WRITE_CSR(sc, TLP_SROM_MII, csr);
147 csr &= ~TLP_SROM_CLK; /* CLK falling edge */
148 WRITE_CSR(sc, TLP_SROM_MII, csr);
149 }
150 }
151
152 /* Data is sampled on the RISING edge of CLK; CLK is parked low. */
153 static u_int16_t /* context: process */
154 srom_read(softc_t *sc, u_int8_t addr)
155 {
156 int i;
157 u_int32_t csr;
158 u_int16_t data;
159
160 /* Enable SROM access. */
161 csr = (TLP_SROM_SEL | TLP_SROM_RD | TLP_MII_MDOE);
162 WRITE_CSR(sc, TLP_SROM_MII, csr);
163 /* CS rising edge prepares SROM for a new cycle. */
164 csr |= TLP_SROM_CS;
165 WRITE_CSR(sc, TLP_SROM_MII, csr); /* assert CS */
166 srom_shift_bits(sc, 6, 4); /* issue read cmd */
167 srom_shift_bits(sc, addr, 6); /* issue address */
168 for (data=0, i=16; i>=0; i--) /* read ->17<- bits of data */
169 { /* MSB first */
170 csr = READ_CSR(sc, TLP_SROM_MII); /* DOUT sampled */
171 data = (data<<1) | ((csr & TLP_SROM_DOUT) ? 1:0);
172 csr |= TLP_SROM_CLK; /* CLK rising edge */
173 WRITE_CSR(sc, TLP_SROM_MII, csr);
174 csr &= ~TLP_SROM_CLK; /* CLK falling edge */
175 WRITE_CSR(sc, TLP_SROM_MII, csr);
176 }
177 /* Disable SROM access. */
178 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOE);
179
180 return data;
181 }
182
183 /* The SROM is formatted by the mfgr and should NOT be written! */
184 /* But lmcconfig can rewrite it in case it gets overwritten somehow. */
185 static void /* context: process */
186 srom_write(softc_t *sc, u_int8_t addr, u_int16_t data)
187 {
188 u_int32_t csr;
189 int i;
190
191 /* Enable SROM access. */
192 csr = (TLP_SROM_SEL | TLP_SROM_RD | TLP_MII_MDOE);
193 WRITE_CSR(sc, TLP_SROM_MII, csr);
194
195 /* Issue write-enable command. */
196 csr |= TLP_SROM_CS;
197 WRITE_CSR(sc, TLP_SROM_MII, csr); /* assert CS */
198 srom_shift_bits(sc, 4, 4); /* issue write enable cmd */
199 srom_shift_bits(sc, 63, 6); /* issue address */
200 csr &= ~TLP_SROM_CS;
201 WRITE_CSR(sc, TLP_SROM_MII, csr); /* deassert CS */
202
203 /* Issue erase command. */
204 csr |= TLP_SROM_CS;
205 WRITE_CSR(sc, TLP_SROM_MII, csr); /* assert CS */
206 srom_shift_bits(sc, 7, 4); /* issue erase cmd */
207 srom_shift_bits(sc, addr, 6); /* issue address */
208 csr &= ~TLP_SROM_CS;
209 WRITE_CSR(sc, TLP_SROM_MII, csr); /* deassert CS */
210
211 /* Issue write command. */
212 csr |= TLP_SROM_CS;
213 WRITE_CSR(sc, TLP_SROM_MII, csr); /* assert CS */
214 for (i=0; i<10; i++) /* 100 ms max wait */
215 if ((READ_CSR(sc, TLP_SROM_MII) & TLP_SROM_DOUT)==0) SLEEP(10000);
216 srom_shift_bits(sc, 5, 4); /* issue write cmd */
217 srom_shift_bits(sc, addr, 6); /* issue address */
218 srom_shift_bits(sc, data, 16); /* issue data */
219 csr &= ~TLP_SROM_CS;
220 WRITE_CSR(sc, TLP_SROM_MII, csr); /* deassert CS */
221
222 /* Issue write-disable command. */
223 csr |= TLP_SROM_CS;
224 WRITE_CSR(sc, TLP_SROM_MII, csr); /* assert CS */
225 for (i=0; i<10; i++) /* 100 ms max wait */
226 if ((READ_CSR(sc, TLP_SROM_MII) & TLP_SROM_DOUT)==0) SLEEP(10000);
227 srom_shift_bits(sc, 4, 4); /* issue write disable cmd */
228 srom_shift_bits(sc, 0, 6); /* issue address */
229 csr &= ~TLP_SROM_CS;
230 WRITE_CSR(sc, TLP_SROM_MII, csr); /* deassert CS */
231
232 /* Disable SROM access. */
233 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOE);
234 }
235
236 /* Not all cards have BIOS roms. */
237 /* The BIOS ROM is an AMD 29F010 1Mbit (128K by 8) EEPROM. */
238 static u_int8_t /* context: process */
239 bios_read(softc_t *sc, u_int32_t addr)
240 {
241 u_int32_t srom_mii;
242
243 /* Load the BIOS rom address register. */
244 WRITE_CSR(sc, TLP_BIOS_ROM, addr);
245
246 /* Enable the BIOS rom. */
247 srom_mii = TLP_BIOS_SEL | TLP_BIOS_RD | TLP_MII_MDOE;
248 WRITE_CSR(sc, TLP_SROM_MII, srom_mii);
249
250 /* Wait at least 20 PCI cycles. */
251 DELAY(20);
252
253 /* Read the BIOS rom data. */
254 srom_mii = READ_CSR(sc, TLP_SROM_MII);
255
256 /* Disable the BIOS rom. */
257 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOE);
258
259 return (u_int8_t)srom_mii & 0xFF;
260 }
261
262 static void /* context: process */
263 bios_write_phys(softc_t *sc, u_int32_t addr, u_int8_t data)
264 {
265 u_int32_t srom_mii;
266
267 /* Load the BIOS rom address register. */
268 WRITE_CSR(sc, TLP_BIOS_ROM, addr);
269
270 /* Enable the BIOS rom. */
271 srom_mii = TLP_BIOS_SEL | TLP_BIOS_WR | TLP_MII_MDOE;
272
273 /* Load the data into the data register. */
274 srom_mii = (srom_mii & 0xFFFFFF00) | (data & 0xFF);
275 WRITE_CSR(sc, TLP_SROM_MII, srom_mii);
276
277 /* Wait at least 20 PCI cycles. */
278 DELAY(20);
279
280 /* Disable the BIOS rom. */
281 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOE);
282 }
283
284 static void /* context: process */
285 bios_write(softc_t *sc, u_int32_t addr, u_int8_t data)
286 {
287 u_int8_t read_data;
288
289 /* this sequence enables writing */
290 bios_write_phys(sc, 0x5555, 0xAA);
291 bios_write_phys(sc, 0x2AAA, 0x55);
292 bios_write_phys(sc, 0x5555, 0xA0);
293 bios_write_phys(sc, addr, data);
294
295 /* Wait for the write operation to complete. */
296 for (;;) /* interruptible syscall */
297 {
298 for (;;)
299 {
300 read_data = bios_read(sc, addr);
301 if ((read_data & 0x80) == (data & 0x80)) break;
302 if (read_data & 0x20)
303 { /* Data sheet says read it again. */
304 read_data = bios_read(sc, addr);
305 if ((read_data & 0x80) == (data & 0x80)) break;
306 if (sc->config.debug)
307 printf("%s: bios_write() failed; rom addr=0x%x\n",
308 NAME_UNIT, addr);
309 return;
310 }
311 }
312 read_data = bios_read(sc, addr);
313 if (read_data == data) break;
314 }
315 }
316
317 static void /* context: process */
318 bios_erase(softc_t *sc)
319 {
320 unsigned char read_data;
321
322 /* This sequence enables erasing: */
323 bios_write_phys(sc, 0x5555, 0xAA);
324 bios_write_phys(sc, 0x2AAA, 0x55);
325 bios_write_phys(sc, 0x5555, 0x80);
326 bios_write_phys(sc, 0x5555, 0xAA);
327 bios_write_phys(sc, 0x2AAA, 0x55);
328 bios_write_phys(sc, 0x5555, 0x10);
329
330 /* Wait for the erase operation to complete. */
331 for (;;) /* interruptible syscall */
332 {
333 for (;;)
334 {
335 read_data = bios_read(sc, 0);
336 if (read_data & 0x80) break;
337 if (read_data & 0x20)
338 { /* Data sheet says read it again. */
339 read_data = bios_read(sc, 0);
340 if (read_data & 0x80) break;
341 if (sc->config.debug)
342 printf("%s: bios_erase() failed\n", NAME_UNIT);
343 return;
344 }
345 }
346 read_data = bios_read(sc, 0);
347 if (read_data == 0xFF) break;
348 }
349 }
350
351 /* MDIO is 3-stated between tranactions. */
352 /* MDIO is set up before the RISING edge of MDC; MDC is parked low. */
353 static void /* context: process */
354 mii_shift_bits(softc_t *sc, u_int32_t data, u_int32_t len)
355 {
356 u_int32_t csr = READ_CSR(sc, TLP_SROM_MII);
357 for (; len>0; len--)
358 { /* MSB first */
359 if (data & (1<<(len-1)))
360 csr |= TLP_MII_MDOUT; /* MDOUT setup */
361 else
362 csr &= ~TLP_MII_MDOUT; /* MDOUT setup */
363 WRITE_CSR(sc, TLP_SROM_MII, csr);
364 csr |= TLP_MII_MDC; /* MDC rising edge */
365 WRITE_CSR(sc, TLP_SROM_MII, csr);
366 csr &= ~TLP_MII_MDC; /* MDC falling edge */
367 WRITE_CSR(sc, TLP_SROM_MII, csr);
368 }
369 }
370
371 /* The specification for the MII is IEEE Std 802.3 clause 22. */
372 /* MDIO is sampled on the RISING edge of MDC; MDC is parked low. */
373 static u_int16_t /* context: process */
374 mii_read(softc_t *sc, u_int8_t regad)
375 {
376 int i;
377 u_int32_t csr;
378 u_int16_t data = 0;
379
380 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOUT);
381
382 mii_shift_bits(sc, 0xFFFFF, 20); /* preamble */
383 mii_shift_bits(sc, 0xFFFFF, 20); /* preamble */
384 mii_shift_bits(sc, 1, 2); /* start symbol */
385 mii_shift_bits(sc, 2, 2); /* read op */
386 mii_shift_bits(sc, 0, 5); /* phyad=0 */
387 mii_shift_bits(sc, regad, 5); /* regad */
388 csr = READ_CSR(sc, TLP_SROM_MII);
389 csr |= TLP_MII_MDOE;
390 WRITE_CSR(sc, TLP_SROM_MII, csr);
391 mii_shift_bits(sc, 0, 2); /* turn-around */
392 for (i=15; i>=0; i--) /* data */
393 { /* MSB first */
394 csr = READ_CSR(sc, TLP_SROM_MII); /* MDIN sampled */
395 data = (data<<1) | ((csr & TLP_MII_MDIN) ? 1:0);
396 csr |= TLP_MII_MDC; /* MDC rising edge */
397 WRITE_CSR(sc, TLP_SROM_MII, csr);
398 csr &= ~TLP_MII_MDC; /* MDC falling edge */
399 WRITE_CSR(sc, TLP_SROM_MII, csr);
400 }
401 return data;
402 }
403
404 static void /* context: process */
405 mii_write(softc_t *sc, u_int8_t regad, u_int16_t data)
406 {
407 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOUT);
408 mii_shift_bits(sc, 0xFFFFF, 20); /* preamble */
409 mii_shift_bits(sc, 0xFFFFF, 20); /* preamble */
410 mii_shift_bits(sc, 1, 2); /* start symbol */
411 mii_shift_bits(sc, 1, 2); /* write op */
412 mii_shift_bits(sc, 0, 5); /* phyad=0 */
413 mii_shift_bits(sc, regad, 5); /* regad */
414 mii_shift_bits(sc, 2, 2); /* turn-around */
415 mii_shift_bits(sc, data, 16); /* data */
416 WRITE_CSR(sc, TLP_SROM_MII, TLP_MII_MDOE);
417 if (regad == 16) sc->led_state = data; /* a small optimization */
418 }
419
420 static void
421 mii16_set_bits(softc_t *sc, u_int16_t bits)
422 {
423 u_int16_t mii16 = mii_read(sc, 16);
424 mii16 |= bits;
425 mii_write(sc, 16, mii16);
426 }
427
428 static void
429 mii16_clr_bits(softc_t *sc, u_int16_t bits)
430 {
431 u_int16_t mii16 = mii_read(sc, 16);
432 mii16 &= ~bits;
433 mii_write(sc, 16, mii16);
434 }
435
436 static void
437 mii17_set_bits(softc_t *sc, u_int16_t bits)
438 {
439 u_int16_t mii17 = mii_read(sc, 17);
440 mii17 |= bits;
441 mii_write(sc, 17, mii17);
442 }
443
444 static void
445 mii17_clr_bits(softc_t *sc, u_int16_t bits)
446 {
447 u_int16_t mii17 = mii_read(sc, 17);
448 mii17 &= ~bits;
449 mii_write(sc, 17, mii17);
450 }
451
452 /*
453 * Watchdog code is more readable if it refreshes LEDs
454 * once a second whether they need it or not.
455 * But MII refs take 150 uSecs each, so remember the last value
456 * written to MII16 and avoid LED writes that do nothing.
457 */
458
459 static void
460 led_off(softc_t *sc, u_int16_t led)
461 {
462 if ((led & sc->led_state) == led) return;
463 mii16_set_bits(sc, led);
464 }
465
466 static void
467 led_on(softc_t *sc, u_int16_t led)
468 {
469 if ((led & sc->led_state) == 0) return;
470 mii16_clr_bits(sc, led);
471 }
472
473 static void
474 led_inv(softc_t *sc, u_int16_t led)
475 {
476 u_int16_t mii16 = mii_read(sc, 16);
477 mii16 ^= led;
478 mii_write(sc, 16, mii16);
479 }
480
481 /*
482 * T1 & T3 framer registers are accessed through MII regs 17 & 18.
483 * Write the address to MII reg 17 then R/W data through MII reg 18.
484 * The hardware interface is an Intel-style 8-bit muxed A/D bus.
485 */
486 static void
487 framer_write(softc_t *sc, u_int16_t addr, u_int8_t data)
488 {
489 mii_write(sc, 17, addr);
490 mii_write(sc, 18, data);
491 }
492
493 static u_int8_t
494 framer_read(softc_t *sc, u_int16_t addr)
495 {
496 mii_write(sc, 17, addr);
497 return (u_int8_t)mii_read(sc, 18);
498 }
499
500 /* Tulip's hardware implementation of General Purpose IO
501 * (GPIO) pins makes life difficult for software.
502 * Bits 7-0 in the Tulip GPIO CSR are used for two purposes
503 * depending on the state of bit 8.
504 * If bit 8 is 0 then bits 7-0 are "data" bits.
505 * If bit 8 is 1 then bits 7-0 are "direction" bits.
506 * If a direction bit is one, the data bit is an output.
507 * The problem is that the direction bits are WRITE-ONLY.
508 * Software must remember the direction bits in a shadow copy.
509 * (sc->gpio_dir) in order to change some but not all of the bits.
510 * All accesses to the Tulip GPIO register use these five procedures.
511 */
512
513 static void
514 gpio_make_input(softc_t *sc, u_int32_t bits)
515 {
516 sc->gpio_dir &= ~bits;
517 WRITE_CSR(sc, TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
518 }
519
520 static void
521 gpio_make_output(softc_t *sc, u_int32_t bits)
522 {
523 sc->gpio_dir |= bits;
524 WRITE_CSR(sc, TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
525 }
526
527 static u_int32_t
528 gpio_read(softc_t *sc)
529 {
530 return READ_CSR(sc, TLP_GPIO);
531 }
532
533 static void
534 gpio_set_bits(softc_t *sc, u_int32_t bits)
535 {
536 WRITE_CSR(sc, TLP_GPIO, (gpio_read(sc) | bits) & 0xFF);
537 }
538
539 static void
540 gpio_clr_bits(softc_t *sc, u_int32_t bits)
541 {
542 WRITE_CSR(sc, TLP_GPIO, (gpio_read(sc) & ~bits) & 0xFF);
543 }
544
545 /* Reset ALL of the flip-flops in the gate array to zero. */
546 /* This does NOT change the gate array programming. */
547 /* Called during initialization so it must not sleep. */
548 static void /* context: kernel (boot) or process (syscall) */
549 xilinx_reset(softc_t *sc)
550 {
551 /* Drive RESET low to force initialization. */
552 gpio_clr_bits(sc, GPIO_RESET);
553 gpio_make_output(sc, GPIO_RESET);
554
555 /* Hold RESET low for more than 10 uSec. */
556 DELAY(50);
557
558 /* Done with RESET; make it an input. */
559 gpio_make_input(sc, GPIO_RESET);
560 }
561
562 /* Load Xilinx gate array program from on-board rom. */
563 /* This changes the gate array programming. */
564 static void /* context: process */
565 xilinx_load_from_rom(softc_t *sc)
566 {
567 int i;
568
569 /* Drive MODE low to load from ROM rather than GPIO. */
570 gpio_clr_bits(sc, GPIO_MODE);
571 gpio_make_output(sc, GPIO_MODE);
572
573 /* Drive DP & RESET low to force configuration. */
574 gpio_clr_bits(sc, GPIO_RESET | GPIO_DP);
575 gpio_make_output(sc, GPIO_RESET | GPIO_DP);
576
577 /* Hold RESET & DP low for more than 10 uSec. */
578 DELAY(50);
579
580 /* Done with RESET & DP; make them inputs. */
581 gpio_make_input(sc, GPIO_DP | GPIO_RESET);
582
583 /* BUSY-WAIT for Xilinx chip to configure itself from ROM bits. */
584 for (i=0; i<100; i++) /* 1 sec max delay */
585 if ((gpio_read(sc) & GPIO_DP)==0) SLEEP(10000);
586
587 /* Done with MODE; make it an input. */
588 gpio_make_input(sc, GPIO_MODE);
589 }
590
591 /* Load the Xilinx gate array program from userland bits. */
592 /* This changes the gate array programming. */
593 static int /* context: process */
594 xilinx_load_from_file(softc_t *sc, char *addr, u_int32_t len)
595 {
596 char *data;
597 int i, j, error;
598
599 /* Get some pages to hold the Xilinx bits; biggest file is < 6 KB. */
600 if (len > 8192) return EFBIG; /* too big */
601 data = malloc(len, M_TEMP, M_WAITOK);
602 if (data == NULL) return ENOMEM;
603
604 /* Copy the Xilinx bits from userland. */
605 if ((error = copyin(addr, data, len)))
606 {
607 free(data, M_TEMP);
608 return error;
609 }
610
611 /* Drive MODE high to load from GPIO rather than ROM. */
612 gpio_set_bits(sc, GPIO_MODE);
613 gpio_make_output(sc, GPIO_MODE);
614
615 /* Drive DP & RESET low to force configuration. */
616 gpio_clr_bits(sc, GPIO_RESET | GPIO_DP);
617 gpio_make_output(sc, GPIO_RESET | GPIO_DP);
618
619 /* Hold RESET & DP low for more than 10 uSec. */
620 DELAY(50);
621
622 /* Done with RESET & DP; make them inputs. */
623 gpio_make_input(sc, GPIO_RESET | GPIO_DP);
624
625 /* BUSY-WAIT for Xilinx chip to clear its config memory. */
626 gpio_make_input(sc, GPIO_INIT);
627 for (i=0; i<10000; i++) /* 1 sec max delay */
628 if ((gpio_read(sc) & GPIO_INIT)==0) SLEEP(10000);
629
630 /* Configure CLK and DATA as outputs. */
631 gpio_set_bits(sc, GPIO_CLK); /* park CLK high */
632 gpio_make_output(sc, GPIO_CLK | GPIO_DATA);
633
634 /* Write bits to Xilinx; CLK is parked HIGH. */
635 /* DATA is set up before the RISING edge of CLK. */
636 for (i=0; i<len; i++)
637 for (j=0; j<8; j++)
638 { /* LSB first */
639 if (data[i] & (1<<j))
640 gpio_set_bits(sc, GPIO_DATA); /* DATA setup */
641 else
642 gpio_clr_bits(sc, GPIO_DATA); /* DATA setup */
643 gpio_clr_bits(sc, GPIO_CLK); /* CLK falling edge */
644 gpio_set_bits(sc, GPIO_CLK); /* CLK rising edge */
645 }
646
647 /* Stop driving all Xilinx-related signals. */
648 /* Pullup and pulldown resistors take over. */
649 gpio_make_input(sc, GPIO_CLK | GPIO_DATA | GPIO_MODE);
650
651 free(data, M_TEMP);
652
653 return 0;
654 }
655
656 /* Write fragments of a command into the synthesized oscillator. */
657 /* DATA is set up before the RISING edge of CLK. CLK is parked low. */
658 static void
659 synth_shift_bits(softc_t *sc, u_int32_t data, u_int32_t len)
660 {
661 int i;
662
663 for (i=0; i<len; i++)
664 { /* LSB first */
665 if (data & (1<<i))
666 gpio_set_bits(sc, GPIO_DATA); /* DATA setup */
667 else
668 gpio_clr_bits(sc, GPIO_DATA); /* DATA setup */
669 gpio_set_bits(sc, GPIO_CLK); /* CLK rising edge */
670 gpio_clr_bits(sc, GPIO_CLK); /* CLK falling edge */
671 }
672 }
673
674 /* Write a command to the synthesized oscillator on SSI and HSSIc. */
675 static void /* context: process */
676 synth_write(softc_t *sc, struct synth *synth)
677 {
678 /* SSI cards have a programmable prescaler */
679 if (sc->status.card_type == CSID_LMC_SSI)
680 {
681 if (synth->prescale == 9) /* divide by 512 */
682 mii17_set_bits(sc, MII17_SSI_PRESCALE);
683 else /* divide by 32 */
684 mii17_clr_bits(sc, MII17_SSI_PRESCALE);
685 }
686
687 gpio_clr_bits(sc, GPIO_DATA | GPIO_CLK);
688 gpio_make_output(sc, GPIO_DATA | GPIO_CLK);
689
690 /* SYNTH is a low-true chip enable for the AV9110 chip. */
691 gpio_set_bits(sc, GPIO_SSI_SYNTH);
692 gpio_make_output(sc, GPIO_SSI_SYNTH);
693 gpio_clr_bits(sc, GPIO_SSI_SYNTH);
694
695 /* Serially shift the command into the AV9110 chip. */
696 synth_shift_bits(sc, synth->n, 7);
697 synth_shift_bits(sc, synth->m, 7);
698 synth_shift_bits(sc, synth->v, 1);
699 synth_shift_bits(sc, synth->x, 2);
700 synth_shift_bits(sc, synth->r, 2);
701 synth_shift_bits(sc, 0x16, 5); /* enable clk/x output */
702
703 /* SYNTH (chip enable) going high ends the command. */
704 gpio_set_bits(sc, GPIO_SSI_SYNTH);
705 gpio_make_input(sc, GPIO_SSI_SYNTH);
706
707 /* Stop driving serial-related signals; pullups/pulldowns take over. */
708 gpio_make_input(sc, GPIO_DATA | GPIO_CLK);
709
710 /* remember the new synthesizer parameters */
711 if (&sc->config.synth != synth) sc->config.synth = *synth;
712 }
713
714 /* Write a command to the DAC controlling the VCXO on some T3 adapters. */
715 /* The DAC is a TI-TLV5636: 12-bit resolution and a serial interface. */
716 /* DATA is set up before the FALLING edge of CLK. CLK is parked HIGH. */
717 static void /* context: process */
718 dac_write(softc_t *sc, u_int16_t data)
719 {
720 int i;
721
722 /* Prepare to use DATA and CLK. */
723 gpio_set_bits(sc, GPIO_DATA | GPIO_CLK);
724 gpio_make_output(sc, GPIO_DATA | GPIO_CLK);
725
726 /* High-to-low transition prepares DAC for new value. */
727 gpio_set_bits(sc, GPIO_T3_DAC);
728 gpio_make_output(sc, GPIO_T3_DAC);
729 gpio_clr_bits(sc, GPIO_T3_DAC);
730
731 /* Serially shift command bits into DAC. */
732 for (i=0; i<16; i++)
733 { /* MSB first */
734 if (data & (1<<(15-i)))
735 gpio_set_bits(sc, GPIO_DATA); /* DATA setup */
736 else
737 gpio_clr_bits(sc, GPIO_DATA); /* DATA setup */
738 gpio_clr_bits(sc, GPIO_CLK); /* CLK falling edge */
739 gpio_set_bits(sc, GPIO_CLK); /* CLK rising edge */
740 }
741
742 /* Done with DAC; make it an input; loads new value into DAC. */
743 gpio_set_bits(sc, GPIO_T3_DAC);
744 gpio_make_input(sc, GPIO_T3_DAC);
745
746 /* Stop driving serial-related signals; pullups/pulldowns take over. */
747 gpio_make_input(sc, GPIO_DATA | GPIO_CLK);
748 }
749
750 /* Begin HSSI card code */
751
752 static struct card hssi_card =
753 {
754 .ident = hssi_ident,
755 .watchdog = hssi_watchdog,
756 .ioctl = hssi_ioctl,
757 .attach = hssi_attach,
758 .detach = hssi_detach,
759 };
760
761 static void
762 hssi_ident(softc_t *sc)
763 {
764 printf(", EIA-613");
765 }
766
767 static void /* context: softirq */
768 hssi_watchdog(softc_t *sc)
769 {
770 u_int16_t mii16 = mii_read(sc, 16) & MII16_HSSI_MODEM;
771
772 sc->status.link_state = STATE_UP;
773
774 led_inv(sc, MII16_HSSI_LED_UL); /* Software is alive. */
775 led_on(sc, MII16_HSSI_LED_LL); /* always on (SSI cable) */
776
777 /* Check the transmit clock. */
778 if (sc->status.tx_speed == 0)
779 {
780 led_on(sc, MII16_HSSI_LED_UR);
781 sc->status.link_state = STATE_DOWN;
782 }
783 else
784 led_off(sc, MII16_HSSI_LED_UR);
785
786 /* Is the modem ready? */
787 if ((mii16 & MII16_HSSI_CA)==0)
788 {
789 led_off(sc, MII16_HSSI_LED_LR);
790 sc->status.link_state = STATE_DOWN;
791 }
792 else
793 led_on(sc, MII16_HSSI_LED_LR);
794
795 /* Print the modem control signals if they changed. */
796 if ((sc->config.debug) && (mii16 != sc->last_mii16))
797 {
798 const char *on = "ON ", *off = "OFF";
799 printf("%s: TA=%s CA=%s LA=%s LB=%s LC=%s TM=%s\n", NAME_UNIT,
800 (mii16 & MII16_HSSI_TA) ? on : off,
801 (mii16 & MII16_HSSI_CA) ? on : off,
802 (mii16 & MII16_HSSI_LA) ? on : off,
803 (mii16 & MII16_HSSI_LB) ? on : off,
804 (mii16 & MII16_HSSI_LC) ? on : off,
805 (mii16 & MII16_HSSI_TM) ? on : off);
806 }
807
808 /* SNMP one-second-report */
809 sc->status.snmp.hssi.sigs = mii16 & MII16_HSSI_MODEM;
810
811 /* Remember this state until next time. */
812 sc->last_mii16 = mii16;
813
814 /* If a loop back is in effect, link status is UP */
815 if (sc->config.loop_back != CFG_LOOP_NONE)
816 sc->status.link_state = STATE_UP;
817 }
818
819 static int /* context: process */
820 hssi_ioctl(softc_t *sc, struct ioctl *ioctl)
821 {
822 int error = 0;
823
824 if (ioctl->cmd == IOCTL_SNMP_SIGS)
825 {
826 u_int16_t mii16 = mii_read(sc, 16);
827 mii16 &= ~MII16_HSSI_MODEM;
828 mii16 |= (MII16_HSSI_MODEM & ioctl->data);
829 mii_write(sc, 16, mii16);
830 }
831 else if (ioctl->cmd == IOCTL_SET_STATUS)
832 {
833 if (ioctl->data)
834 mii16_set_bits(sc, MII16_HSSI_TA);
835 else
836 mii16_clr_bits(sc, MII16_HSSI_TA);
837 }
838 else
839 error = EINVAL;
840
841 return error;
842 }
843
844 /* Must not sleep. */
845 static void
846 hssi_attach(softc_t *sc, struct config *config)
847 {
848 if (config == NULL) /* startup config */
849 {
850 sc->status.card_type = READ_PCI_CFG(sc, TLP_CSID);
851 sc->config.crc_len = CFG_CRC_16;
852 sc->config.loop_back = CFG_LOOP_NONE;
853 sc->config.tx_clk_src = CFG_CLKMUX_ST;
854 sc->config.dte_dce = CFG_DTE;
855 sc->config.synth.n = 52; /* 52.000 Mbs */
856 sc->config.synth.m = 5;
857 sc->config.synth.v = 0;
858 sc->config.synth.x = 0;
859 sc->config.synth.r = 0;
860 sc->config.synth.prescale = 2;
861 }
862 else if (config != &sc->config) /* change config */
863 {
864 u_int32_t *old_synth = (u_int32_t *)&sc->config.synth;
865 u_int32_t *new_synth = (u_int32_t *)&config->synth;
866 if ((sc->config.crc_len == config->crc_len) &&
867 (sc->config.loop_back == config->loop_back) &&
868 (sc->config.tx_clk_src == config->tx_clk_src) &&
869 (sc->config.dte_dce == config->dte_dce) &&
870 (*old_synth == *new_synth))
871 return; /* nothing changed */
872 sc->config.crc_len = config->crc_len;
873 sc->config.loop_back = config->loop_back;
874 sc->config.tx_clk_src = config->tx_clk_src;
875 sc->config.dte_dce = config->dte_dce;
876 *old_synth = *new_synth;
877 }
878 /* If (config == &sc->config) then the FPGA microcode
879 * was just initialized and the current config should
880 * be reloaded into the card.
881 */
882
883 /* set CRC length */
884 if (sc->config.crc_len == CFG_CRC_32)
885 mii16_set_bits(sc, MII16_HSSI_CRC32);
886 else
887 mii16_clr_bits(sc, MII16_HSSI_CRC32);
888
889 /* Assert pin LA in HSSI conn: ask modem for local loop. */
890 if (sc->config.loop_back == CFG_LOOP_LL)
891 mii16_set_bits(sc, MII16_HSSI_LA);
892 else
893 mii16_clr_bits(sc, MII16_HSSI_LA);
894
895 /* Assert pin LB in HSSI conn: ask modem for remote loop. */
896 if (sc->config.loop_back == CFG_LOOP_RL)
897 mii16_set_bits(sc, MII16_HSSI_LB);
898 else
899 mii16_clr_bits(sc, MII16_HSSI_LB);
900
901 if (sc->status.card_type == CSID_LMC_HSSI)
902 {
903 /* set TXCLK src */
904 if (sc->config.tx_clk_src == CFG_CLKMUX_ST)
905 gpio_set_bits(sc, GPIO_HSSI_TXCLK);
906 else
907 gpio_clr_bits(sc, GPIO_HSSI_TXCLK);
908 gpio_make_output(sc, GPIO_HSSI_TXCLK);
909 }
910 else if (sc->status.card_type == CSID_LMC_HSSIc)
911 { /* cPCI HSSI rev C has extra features */
912 /* Set TXCLK source. */
913 u_int16_t mii16 = mii_read(sc, 16);
914 mii16 &= ~MII16_HSSI_CLKMUX;
915 mii16 |= (sc->config.tx_clk_src&3)<<13;
916 mii_write(sc, 16, mii16);
917
918 /* cPCI HSSI implements loopback towards the net. */
919 if (sc->config.loop_back == CFG_LOOP_LINE)
920 mii16_set_bits(sc, MII16_HSSI_LOOP);
921 else
922 mii16_clr_bits(sc, MII16_HSSI_LOOP);
923
924 /* Set DTE/DCE mode. */
925 if (sc->config.dte_dce == CFG_DCE)
926 gpio_set_bits(sc, GPIO_HSSI_DCE);
927 else
928 gpio_clr_bits(sc, GPIO_HSSI_DCE);
929 gpio_make_output(sc, GPIO_HSSI_DCE);
930
931 /* Program the synthesized oscillator. */
932 synth_write(sc, &sc->config.synth);
933 }
934 }
935
936 static void
937 hssi_detach(softc_t *sc)
938 {
939 mii16_clr_bits(sc, MII16_HSSI_TA);
940 led_on(sc, MII16_LED_ALL);
941 }
942
943 /* End HSSI card code */
944
945 /* Begin DS3 card code */
946
947 static struct card t3_card =
948 {
949 .ident = t3_ident,
950 .watchdog = t3_watchdog,
951 .ioctl = t3_ioctl,
952 .attach = t3_attach,
953 .detach = t3_detach,
954 };
955
956 static void
957 t3_ident(softc_t *sc)
958 {
959 printf(", TXC03401 rev B");
960 }
961
962 static void /* context: softirq */
963 t3_watchdog(softc_t *sc)
964 {
965 u_int16_t CV;
966 u_int8_t CERR, PERR, MERR, FERR, FEBE;
967 u_int8_t ctl1, stat16, feac;
968 u_int16_t mii16;
969
970 sc->status.link_state = STATE_UP;
971
972 /* Read the alarm registers. */
973 ctl1 = framer_read(sc, T3CSR_CTL1);
974 stat16 = framer_read(sc, T3CSR_STAT16);
975 mii16 = mii_read(sc, 16);
976
977 /* Always ignore the RTLOC alarm bit. */
978 stat16 &= ~STAT16_RTLOC;
979
980 /* Software is alive. */
981 led_inv(sc, MII16_DS3_LED_GRN);
982
983 /* Receiving Alarm Indication Signal (AIS). */
984 if (stat16 & STAT16_RAIS) /* receiving ais */
985 led_on(sc, MII16_DS3_LED_BLU);
986 else if (ctl1 & CTL1_TXAIS) /* sending ais */
987 led_inv(sc, MII16_DS3_LED_BLU);
988 else
989 led_off(sc, MII16_DS3_LED_BLU);
990
991 /* Receiving Remote Alarm Indication (RAI). */
992 if (stat16 & STAT16_XERR) /* receiving rai */
993 led_on(sc, MII16_DS3_LED_YEL);
994 else if ((ctl1 & CTL1_XTX) == 0) /* sending rai */
995 led_inv(sc, MII16_DS3_LED_YEL);
996 else
997 led_off(sc, MII16_DS3_LED_YEL);
998
999 /* If certain status bits are set then the link is 'down'. */
1000 /* The bad bits are: rxlos rxoof rxais rxidl xerr. */
1001 if (stat16 & ~(STAT16_FEAC | STAT16_SEF))
1002 sc->status.link_state = STATE_DOWN;
1003
1004 /* Declare local Red Alarm if the link is down. */
1005 if (sc->status.link_state == STATE_DOWN)
1006 led_on(sc, MII16_DS3_LED_RED);
1007 else if (sc->loop_timer) /* loopback is active */
1008 led_inv(sc, MII16_DS3_LED_RED);
1009 else
1010 led_off(sc, MII16_DS3_LED_RED);
1011
1012 /* Print latched error bits if they changed. */
1013 if ((sc->config.debug) && ((stat16 & ~STAT16_FEAC) != sc->last_stat16))
1014 {
1015 const char *on = "ON ", *off = "OFF";
1016 printf("%s: RLOS=%s ROOF=%s RAIS=%s RIDL=%s SEF=%s XERR=%s\n",
1017 NAME_UNIT,
1018 (stat16 & STAT16_RLOS) ? on : off,
1019 (stat16 & STAT16_ROOF) ? on : off,
1020 (stat16 & STAT16_RAIS) ? on : off,
1021 (stat16 & STAT16_RIDL) ? on : off,
1022 (stat16 & STAT16_SEF) ? on : off,
1023 (stat16 & STAT16_XERR) ? on : off);
1024 }
1025
1026 /* Check and print error counters if non-zero. */
1027 CV = framer_read(sc, T3CSR_CVHI)<<8;
1028 CV += framer_read(sc, T3CSR_CVLO);
1029 PERR = framer_read(sc, T3CSR_PERR);
1030 CERR = framer_read(sc, T3CSR_CERR);
1031 FERR = framer_read(sc, T3CSR_FERR);
1032 MERR = framer_read(sc, T3CSR_MERR);
1033 FEBE = framer_read(sc, T3CSR_FEBE);
1034
1035 /* CV is invalid during LOS. */
1036 if (stat16 & STAT16_RLOS) CV = 0;
1037 /* CERR & FEBE are invalid in M13 mode */
1038 if (sc->config.format == CFG_FORMAT_T3M13) CERR = FEBE = 0;
1039 /* FEBE is invalid during AIS. */
1040 if (stat16 & STAT16_RAIS) FEBE = 0;
1041 if (sc->config.debug && (CV || PERR || CERR || FERR || MERR || FEBE))
1042 printf("%s: CV=%u PERR=%u CERR=%u FERR=%u MERR=%u FEBE=%u\n",
1043 NAME_UNIT, CV, PERR, CERR, FERR, MERR, FEBE);
1044
1045 /* Driver keeps crude link-level error counters (SNMP is better). */
1046 sc->status.cntrs.lcv_errs += CV;
1047 sc->status.cntrs.par_errs += PERR;
1048 sc->status.cntrs.cpar_errs += CERR;
1049 sc->status.cntrs.frm_errs += FERR;
1050 sc->status.cntrs.mfrm_errs += MERR;
1051 sc->status.cntrs.febe_errs += FEBE;
1052
1053 /* Check for FEAC messages (FEAC not defined in M13 mode). */
1054 if (FORMAT_T3CPAR && (stat16 & STAT16_FEAC)) do
1055 {
1056 feac = framer_read(sc, T3CSR_FEAC_STK);
1057 if ((feac & FEAC_STK_VALID)==0) break;
1058 /* Ignore RxFEACs while a far end loopback has been requested. */
1059 if (sc->status.snmp.t3.line & TLOOP_FAR_LINE) continue;
1060 switch (feac & FEAC_STK_FEAC)
1061 {
1062 case T3BOP_LINE_UP: break;
1063 case T3BOP_LINE_DOWN: break;
1064 case T3BOP_LOOP_DS3:
1065 {
1066 if (sc->last_FEAC == T3BOP_LINE_DOWN)
1067 {
1068 if (sc->config.debug)
1069 printf("%s: Received a 'line loopback deactivate' FEAC msg\n", NAME_UNIT);
1070 mii16_clr_bits(sc, MII16_DS3_LNLBK);
1071 sc->loop_timer = 0;
1072 }
1073 if (sc->last_FEAC == T3BOP_LINE_UP)
1074 {
1075 if (sc->config.debug)
1076 printf("%s: Received a 'line loopback activate' FEAC msg\n", NAME_UNIT);
1077 mii16_set_bits(sc, MII16_DS3_LNLBK);
1078 sc->loop_timer = 300;
1079 }
1080 break;
1081 }
1082 case T3BOP_OOF:
1083 {
1084 if (sc->config.debug)
1085 printf("%s: Received a 'far end LOF' FEAC msg\n", NAME_UNIT);
1086 break;
1087 }
1088 case T3BOP_IDLE:
1089 {
1090 if (sc->config.debug)
1091 printf("%s: Received a 'far end IDL' FEAC msg\n", NAME_UNIT);
1092 break;
1093 }
1094 case T3BOP_AIS:
1095 {
1096 if (sc->config.debug)
1097 printf("%s: Received a 'far end AIS' FEAC msg\n", NAME_UNIT);
1098 break;
1099 }
1100 case T3BOP_LOS:
1101 {
1102 if (sc->config.debug)
1103 printf("%s: Received a 'far end LOS' FEAC msg\n", NAME_UNIT);
1104 break;
1105 }
1106 default:
1107 {
1108 if (sc->config.debug)
1109 printf("%s: Received a 'type 0x%02X' FEAC msg\n", NAME_UNIT, feac & FEAC_STK_FEAC);
1110 break;
1111 }
1112 }
1113 sc->last_FEAC = feac & FEAC_STK_FEAC;
1114 } while (feac & FEAC_STK_MORE);
1115 stat16 &= ~STAT16_FEAC;
1116
1117 /* Send Service-Affecting priority FEAC messages */
1118 if (((sc->last_stat16 ^ stat16) & 0xF0) && (FORMAT_T3CPAR))
1119 {
1120 /* Transmit continuous FEACs */
1121 framer_write(sc, T3CSR_CTL14,
1122 framer_read(sc, T3CSR_CTL14) & ~CTL14_FEAC10);
1123 if (stat16 & STAT16_RLOS)
1124 framer_write(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_LOS);
1125 else if (stat16 & STAT16_ROOF)
1126 framer_write(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_OOF);
1127 else if (stat16 & STAT16_RAIS)
1128 framer_write(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_AIS);
1129 else if (stat16 & STAT16_RIDL)
1130 framer_write(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_IDLE);
1131 else
1132 framer_write(sc, T3CSR_TX_FEAC, CTL5_EMODE);
1133 }
1134
1135 /* Start sending RAI, Remote Alarm Indication. */
1136 if ((stat16 & STAT16_ROOF) && !(stat16 & STAT16_RLOS) &&
1137 !(sc->last_stat16 & STAT16_ROOF))
1138 framer_write(sc, T3CSR_CTL1, ctl1 &= ~CTL1_XTX);
1139 /* Stop sending RAI, Remote Alarm Indication. */
1140 else if (!(stat16 & STAT16_ROOF) && (sc->last_stat16 & STAT16_ROOF))
1141 framer_write(sc, T3CSR_CTL1, ctl1 |= CTL1_XTX);
1142
1143 /* Start sending AIS, Alarm Indication Signal */
1144 if ((stat16 & STAT16_RLOS) && !(sc->last_stat16 & STAT16_RLOS))
1145 {
1146 mii16_set_bits(sc, MII16_DS3_FRAME);
1147 framer_write(sc, T3CSR_CTL1, ctl1 | CTL1_TXAIS);
1148 }
1149 /* Stop sending AIS, Alarm Indication Signal */
1150 else if (!(stat16 & STAT16_RLOS) && (sc->last_stat16 & STAT16_RLOS))
1151 {
1152 mii16_clr_bits(sc, MII16_DS3_FRAME);
1153 framer_write(sc, T3CSR_CTL1, ctl1 & ~CTL1_TXAIS);
1154 }
1155
1156 /* Time out loopback requests. */
1157 if (sc->loop_timer)
1158 if (--sc->loop_timer == 0)
1159 if (mii16 & MII16_DS3_LNLBK)
1160 {
1161 if (sc->config.debug)
1162 printf("%s: Timeout: Loop Down after 300 seconds\n", NAME_UNIT);
1163 mii16_clr_bits(sc, MII16_DS3_LNLBK); /* line loopback off */
1164 }
1165
1166 /* SNMP error counters */
1167 sc->status.snmp.t3.lcv = CV;
1168 sc->status.snmp.t3.pcv = PERR;
1169 sc->status.snmp.t3.ccv = CERR;
1170 sc->status.snmp.t3.febe = FEBE;
1171
1172 /* SNMP Line Status */
1173 sc->status.snmp.t3.line = 0;
1174 if (!(ctl1 & CTL1_XTX)) sc->status.snmp.t3.line |= TLINE_TX_RAI;
1175 if (stat16 & STAT16_XERR) sc->status.snmp.t3.line |= TLINE_RX_RAI;
1176 if (ctl1 & CTL1_TXAIS) sc->status.snmp.t3.line |= TLINE_TX_AIS;
1177 if (stat16 & STAT16_RAIS) sc->status.snmp.t3.line |= TLINE_RX_AIS;
1178 if (stat16 & STAT16_ROOF) sc->status.snmp.t3.line |= TLINE_LOF;
1179 if (stat16 & STAT16_RLOS) sc->status.snmp.t3.line |= TLINE_LOS;
1180 if (stat16 & STAT16_SEF) sc->status.snmp.t3.line |= T3LINE_SEF;
1181
1182 /* SNMP Loopback Status */
1183 sc->status.snmp.t3.loop &= ~TLOOP_FAR_LINE;
1184 if (sc->config.loop_back == CFG_LOOP_TULIP)
1185 sc->status.snmp.t3.loop |= TLOOP_NEAR_OTHER;
1186 if (ctl1 & CTL1_3LOOP) sc->status.snmp.t3.loop |= TLOOP_NEAR_INWARD;
1187 if (mii16 & MII16_DS3_TRLBK) sc->status.snmp.t3.loop |= TLOOP_NEAR_OTHER;
1188 if (mii16 & MII16_DS3_LNLBK) sc->status.snmp.t3.loop |= TLOOP_NEAR_LINE;
1189 /*if (ctl12 & CTL12_RTPLOOP) sc->status.snmp.t3.loop |= TLOOP_NEAR_PAYLOAD; */
1190
1191 /* Remember this state until next time. */
1192 sc->last_stat16 = stat16;
1193
1194 /* If an INWARD loopback is in effect, link status is UP */
1195 if (sc->config.loop_back != CFG_LOOP_NONE) /* XXX INWARD ONLY */
1196 sc->status.link_state = STATE_UP;
1197 }
1198
1199 static void /* context: process */
1200 t3_send_dbl_feac(softc_t *sc, int feac1, int feac2)
1201 {
1202 u_int8_t tx_feac;
1203 int i;
1204
1205 /* The FEAC transmitter could be sending a continuous */
1206 /* FEAC msg when told to send a double FEAC message. */
1207 /* So save the current state of the FEAC transmitter. */
1208 tx_feac = framer_read(sc, T3CSR_TX_FEAC);
1209 /* Load second FEAC code and stop FEAC transmitter. */
1210 framer_write(sc, T3CSR_TX_FEAC, CTL5_EMODE + feac2);
1211 /* FEAC transmitter sends 10 more FEACs and then stops. */
1212 SLEEP(20000); /* sending one FEAC takes 1700 uSecs */
1213 /* Load first FEAC code and start FEAC transmitter. */
1214 framer_write(sc, T3CSR_DBL_FEAC, CTL13_DFEXEC + feac1);
1215 /* Wait for double FEAC sequence to complete -- about 70 ms. */
1216 for (i=0; i<10; i++) /* max delay 100 ms */
1217 if (framer_read(sc, T3CSR_DBL_FEAC) & CTL13_DFEXEC) SLEEP(10000);
1218 /* Flush received FEACS; do not respond to our own loop cmd! */
1219 while (framer_read(sc, T3CSR_FEAC_STK) & FEAC_STK_VALID) DELAY(1);
1220 /* Restore previous state of the FEAC transmitter. */
1221 /* If it was sending a continous FEAC, it will resume. */
1222 framer_write(sc, T3CSR_TX_FEAC, tx_feac);
1223 }
1224
1225 static int /* context: process */
1226 t3_ioctl(softc_t *sc, struct ioctl *ioctl)
1227 {
1228 int error = 0;
1229
1230 switch (ioctl->cmd)
1231 {
1232 case IOCTL_SNMP_SEND: /* set opstatus? */
1233 {
1234 if (sc->config.format != CFG_FORMAT_T3CPAR)
1235 error = EINVAL;
1236 else if (ioctl->data == TSEND_LINE)
1237 {
1238 sc->status.snmp.t3.loop |= TLOOP_FAR_LINE;
1239 t3_send_dbl_feac(sc, T3BOP_LINE_UP, T3BOP_LOOP_DS3);
1240 }
1241 else if (ioctl->data == TSEND_RESET)
1242 {
1243 t3_send_dbl_feac(sc, T3BOP_LINE_DOWN, T3BOP_LOOP_DS3);
1244 sc->status.snmp.t3.loop &= ~TLOOP_FAR_LINE;
1245 }
1246 else
1247 error = EINVAL;
1248 break;
1249 }
1250 case IOCTL_SNMP_LOOP: /* set opstatus = test? */
1251 {
1252 if (ioctl->data == CFG_LOOP_NONE)
1253 {
1254 mii16_clr_bits(sc, MII16_DS3_FRAME);
1255 mii16_clr_bits(sc, MII16_DS3_TRLBK);
1256 mii16_clr_bits(sc, MII16_DS3_LNLBK);
1257 framer_write(sc, T3CSR_CTL1,
1258 framer_read(sc, T3CSR_CTL1) & ~CTL1_3LOOP);
1259 framer_write(sc, T3CSR_CTL12,
1260 framer_read(sc, T3CSR_CTL12) & ~(CTL12_RTPLOOP | CTL12_RTPLLEN));
1261 }
1262 else if (ioctl->data == CFG_LOOP_LINE)
1263 mii16_set_bits(sc, MII16_DS3_LNLBK);
1264 else if (ioctl->data == CFG_LOOP_OTHER)
1265 mii16_set_bits(sc, MII16_DS3_TRLBK);
1266 else if (ioctl->data == CFG_LOOP_INWARD)
1267 framer_write(sc, T3CSR_CTL1,
1268 framer_read(sc, T3CSR_CTL1) | CTL1_3LOOP);
1269 else if (ioctl->data == CFG_LOOP_DUAL)
1270 {
1271 mii16_set_bits(sc, MII16_DS3_LNLBK);
1272 framer_write(sc, T3CSR_CTL1,
1273 framer_read(sc, T3CSR_CTL1) | CTL1_3LOOP);
1274 }
1275 else if (ioctl->data == CFG_LOOP_PAYLOAD)
1276 {
1277 mii16_set_bits(sc, MII16_DS3_FRAME);
1278 framer_write(sc, T3CSR_CTL12,
1279 framer_read(sc, T3CSR_CTL12) | CTL12_RTPLOOP);
1280 framer_write(sc, T3CSR_CTL12,
1281 framer_read(sc, T3CSR_CTL12) | CTL12_RTPLLEN);
1282 DELAY(25); /* at least two frames (22 uS) */
1283 framer_write(sc, T3CSR_CTL12,
1284 framer_read(sc, T3CSR_CTL12) & ~CTL12_RTPLLEN);
1285 }
1286 else
1287 error = EINVAL;
1288 break;
1289 }
1290 case IOCTL_SET_STATUS:
1291 {
1292 #if 0
1293 if (ioctl->data)
1294 framer_write(sc, T3CSR_CTL1,
1295 framer_read(sc, T3CSR_CTL1) & ~CTL1_TXIDL);
1296 else /* off */
1297 framer_write(sc, T3CSR_CTL1,
1298 framer_read(sc, T3CSR_CTL1) | CTL1_TXIDL);
1299 #endif
1300 break;
1301 }
1302 default:
1303 error = EINVAL;
1304 break;
1305 }
1306
1307 return error;
1308 }
1309
1310 /* Must not sleep. */
1311 static void
1312 t3_attach(softc_t *sc, struct config *config)
1313 {
1314 int i;
1315 u_int8_t ctl1;
1316
1317 if (config == NULL) /* startup config */
1318 {
1319 sc->status.card_type = CSID_LMC_T3;
1320 sc->config.crc_len = CFG_CRC_16;
1321 sc->config.loop_back = CFG_LOOP_NONE;
1322 sc->config.format = CFG_FORMAT_T3CPAR;
1323 sc->config.cable_len = 10; /* meters */
1324 sc->config.scrambler = CFG_SCRAM_DL_KEN;
1325 sc->config.tx_clk_src = CFG_CLKMUX_INT;
1326
1327 /* Center the VCXO -- get within 20 PPM of 44736000. */
1328 dac_write(sc, 0x9002); /* set Vref = 2.048 volts */
1329 dac_write(sc, 2048); /* range is 0..4095 */
1330 }
1331 else if (config != &sc->config) /* change config */
1332 {
1333 if ((sc->config.crc_len == config->crc_len) &&
1334 (sc->config.loop_back == config->loop_back) &&
1335 (sc->config.format == config->format) &&
1336 (sc->config.cable_len == config->cable_len) &&
1337 (sc->config.scrambler == config->scrambler) &&
1338 (sc->config.tx_clk_src == config->tx_clk_src))
1339 return; /* nothing changed */
1340 sc->config.crc_len = config->crc_len;
1341 sc->config.loop_back = config->loop_back;
1342 sc->config.format = config->format;
1343 sc->config.cable_len = config->cable_len;
1344 sc->config.scrambler = config->scrambler;
1345 sc->config.tx_clk_src = config->tx_clk_src;
1346 }
1347
1348 /* Set cable length. */
1349 if (sc->config.cable_len > 30)
1350 mii16_clr_bits(sc, MII16_DS3_ZERO);
1351 else
1352 mii16_set_bits(sc, MII16_DS3_ZERO);
1353
1354 /* Set payload scrambler polynomial. */
1355 if (sc->config.scrambler == CFG_SCRAM_LARS)
1356 mii16_set_bits(sc, MII16_DS3_POLY);
1357 else
1358 mii16_clr_bits(sc, MII16_DS3_POLY);
1359
1360 /* Set payload scrambler on/off. */
1361 if (sc->config.scrambler == CFG_SCRAM_OFF)
1362 mii16_clr_bits(sc, MII16_DS3_SCRAM);
1363 else
1364 mii16_set_bits(sc, MII16_DS3_SCRAM);
1365
1366 /* Set CRC length. */
1367 if (sc->config.crc_len == CFG_CRC_32)
1368 mii16_set_bits(sc, MII16_DS3_CRC32);
1369 else
1370 mii16_clr_bits(sc, MII16_DS3_CRC32);
1371
1372 /* Loopback towards host thru the line interface. */
1373 if (sc->config.loop_back == CFG_LOOP_OTHER)
1374 mii16_set_bits(sc, MII16_DS3_TRLBK);
1375 else
1376 mii16_clr_bits(sc, MII16_DS3_TRLBK);
1377
1378 /* Loopback towards network thru the line interface. */
1379 if (sc->config.loop_back == CFG_LOOP_LINE)
1380 mii16_set_bits(sc, MII16_DS3_LNLBK);
1381 else if (sc->config.loop_back == CFG_LOOP_DUAL)
1382 mii16_set_bits(sc, MII16_DS3_LNLBK);
1383 else
1384 mii16_clr_bits(sc, MII16_DS3_LNLBK);
1385
1386 /* Configure T3 framer chip; write EVERY writeable register. */
1387 ctl1 = CTL1_SER | CTL1_XTX;
1388 if (sc->config.format == CFG_FORMAT_T3M13) ctl1 |= CTL1_M13MODE;
1389 if (sc->config.loop_back == CFG_LOOP_INWARD) ctl1 |= CTL1_3LOOP;
1390 if (sc->config.loop_back == CFG_LOOP_DUAL) ctl1 |= CTL1_3LOOP;
1391 framer_write(sc, T3CSR_CTL1, ctl1);
1392 framer_write(sc, T3CSR_TX_FEAC, CTL5_EMODE);
1393 framer_write(sc, T3CSR_CTL8, CTL8_FBEC);
1394 framer_write(sc, T3CSR_CTL12, CTL12_DLCB1 | CTL12_C21 | CTL12_MCB1);
1395 framer_write(sc, T3CSR_DBL_FEAC, 0);
1396 framer_write(sc, T3CSR_CTL14, CTL14_RGCEN | CTL14_TGCEN);
1397 framer_write(sc, T3CSR_INTEN, 0);
1398 framer_write(sc, T3CSR_CTL20, CTL20_CVEN);
1399
1400 /* Clear error counters and latched error bits */
1401 /* that may have happened while initializing. */
1402 for (i=0; i<21; i++) framer_read(sc, i);
1403 }
1404
1405 static void
1406 t3_detach(softc_t *sc)
1407 {
1408 framer_write(sc, T3CSR_CTL1,
1409 framer_read(sc, T3CSR_CTL1) | CTL1_TXIDL);
1410 led_on(sc, MII16_LED_ALL);
1411 }
1412
1413 /* End DS3 card code */
1414
1415 /* Begin SSI card code */
1416
1417 static struct card ssi_card =
1418 {
1419 .ident = ssi_ident,
1420 .watchdog = ssi_watchdog,
1421 .ioctl = ssi_ioctl,
1422 .attach = ssi_attach,
1423 .detach = ssi_detach,
1424 };
1425
1426 static void
1427 ssi_ident(softc_t *sc)
1428 {
1429 printf(", LTC1343/44");
1430 }
1431
1432 static void /* context: softirq */
1433 ssi_watchdog(softc_t *sc)
1434 {
1435 u_int16_t cable;
1436 u_int16_t mii16 = mii_read(sc, 16) & MII16_SSI_MODEM;
1437
1438 sc->status.link_state = STATE_UP;
1439
1440 /* Software is alive. */
1441 led_inv(sc, MII16_SSI_LED_UL);
1442
1443 /* Check the transmit clock. */
1444 if (sc->status.tx_speed == 0)
1445 {
1446 led_on(sc, MII16_SSI_LED_UR);
1447 sc->status.link_state = STATE_DOWN;
1448 }
1449 else
1450 led_off(sc, MII16_SSI_LED_UR);
1451
1452 /* Check the external cable. */
1453 cable = mii_read(sc, 17);
1454 cable = cable & MII17_SSI_CABLE_MASK;
1455 cable = cable >> MII17_SSI_CABLE_SHIFT;
1456 if (cable == 7)
1457 {
1458 led_off(sc, MII16_SSI_LED_LL); /* no cable */
1459 sc->status.link_state = STATE_DOWN;
1460 }
1461 else
1462 led_on(sc, MII16_SSI_LED_LL);
1463
1464 /* The unit at the other end of the cable is ready if: */
1465 /* DTE mode and DCD pin is asserted */
1466 /* DCE mode and DSR pin is asserted */
1467 if (((sc->config.dte_dce == CFG_DTE) && !(mii16 & MII16_SSI_DCD)) ||
1468 ((sc->config.dte_dce == CFG_DCE) && !(mii16 & MII16_SSI_DSR)))
1469 {
1470 led_off(sc, MII16_SSI_LED_LR);
1471 sc->status.link_state = STATE_DOWN;
1472 }
1473 else
1474 led_on(sc, MII16_SSI_LED_LR);
1475
1476 if (sc->config.debug && (cable != sc->status.cable_type))
1477 printf("%s: SSI cable type changed to '%s'\n",
1478 NAME_UNIT, ssi_cables[cable]);
1479 sc->status.cable_type = cable;
1480
1481 /* Print the modem control signals if they changed. */
1482 if ((sc->config.debug) && (mii16 != sc->last_mii16))
1483 {
1484 const char *on = "ON ", *off = "OFF";
1485 printf("%s: DTR=%s DSR=%s RTS=%s CTS=%s DCD=%s RI=%s LL=%s RL=%s TM=%s\n",
1486 NAME_UNIT,
1487 (mii16 & MII16_SSI_DTR) ? on : off,
1488 (mii16 & MII16_SSI_DSR) ? on : off,
1489 (mii16 & MII16_SSI_RTS) ? on : off,
1490 (mii16 & MII16_SSI_CTS) ? on : off,
1491 (mii16 & MII16_SSI_DCD) ? on : off,
1492 (mii16 & MII16_SSI_RI) ? on : off,
1493 (mii16 & MII16_SSI_LL) ? on : off,
1494 (mii16 & MII16_SSI_RL) ? on : off,
1495 (mii16 & MII16_SSI_TM) ? on : off);
1496 }
1497
1498 /* SNMP one-second report */
1499 sc->status.snmp.ssi.sigs = mii16 & MII16_SSI_MODEM;
1500
1501 /* Remember this state until next time. */
1502 sc->last_mii16 = mii16;
1503
1504 /* If a loop back is in effect, link status is UP */
1505 if (sc->config.loop_back != CFG_LOOP_NONE)
1506 sc->status.link_state = STATE_UP;
1507 }
1508
1509 static int /* context: process */
1510 ssi_ioctl(softc_t *sc, struct ioctl *ioctl)
1511 {
1512 int error = 0;
1513
1514 if (ioctl->cmd == IOCTL_SNMP_SIGS)
1515 {
1516 u_int16_t mii16 = mii_read(sc, 16);
1517 mii16 &= ~MII16_SSI_MODEM;
1518 mii16 |= (MII16_SSI_MODEM & ioctl->data);
1519 mii_write(sc, 16, mii16);
1520 }
1521 else if (ioctl->cmd == IOCTL_SET_STATUS)
1522 {
1523 if (ioctl->data)
1524 mii16_set_bits(sc, (MII16_SSI_DTR | MII16_SSI_RTS | MII16_SSI_DCD));
1525 else
1526 mii16_clr_bits(sc, (MII16_SSI_DTR | MII16_SSI_RTS | MII16_SSI_DCD));
1527 }
1528 else
1529 error = EINVAL;
1530
1531 return error;
1532 }
1533
1534 /* Must not sleep. */
1535 static void
1536 ssi_attach(softc_t *sc, struct config *config)
1537 {
1538 if (config == NULL) /* startup config */
1539 {
1540 sc->status.card_type = CSID_LMC_SSI;
1541 sc->config.crc_len = CFG_CRC_16;
1542 sc->config.loop_back = CFG_LOOP_NONE;
1543 sc->config.tx_clk_src = CFG_CLKMUX_ST;
1544 sc->config.dte_dce = CFG_DTE;
1545 sc->config.synth.n = 51; /* 1.536 MHz */
1546 sc->config.synth.m = 83;
1547 sc->config.synth.v = 1;
1548 sc->config.synth.x = 1;
1549 sc->config.synth.r = 1;
1550 sc->config.synth.prescale = 4;
1551 }
1552 else if (config != &sc->config) /* change config */
1553 {
1554 u_int32_t *old_synth = (u_int32_t *)&sc->config.synth;
1555 u_int32_t *new_synth = (u_int32_t *)&config->synth;
1556 if ((sc->config.crc_len == config->crc_len) &&
1557 (sc->config.loop_back == config->loop_back) &&
1558 (sc->config.tx_clk_src == config->tx_clk_src) &&
1559 (sc->config.dte_dce == config->dte_dce) &&
1560 (*old_synth == *new_synth))
1561 return; /* nothing changed */
1562 sc->config.crc_len = config->crc_len;
1563 sc->config.loop_back = config->loop_back;
1564 sc->config.tx_clk_src = config->tx_clk_src;
1565 sc->config.dte_dce = config->dte_dce;
1566 *old_synth = *new_synth;
1567 }
1568
1569 /* Disable the TX clock driver while programming the oscillator. */
1570 gpio_clr_bits(sc, GPIO_SSI_DCE);
1571 gpio_make_output(sc, GPIO_SSI_DCE);
1572
1573 /* Program the synthesized oscillator. */
1574 synth_write(sc, &sc->config.synth);
1575
1576 /* Set DTE/DCE mode. */
1577 /* If DTE mode then DCD & TXC are received. */
1578 /* If DCE mode then DCD & TXC are driven. */
1579 /* Boards with MII rev=4.0 do not drive DCD. */
1580 if (sc->config.dte_dce == CFG_DCE)
1581 gpio_set_bits(sc, GPIO_SSI_DCE);
1582 else
1583 gpio_clr_bits(sc, GPIO_SSI_DCE);
1584 gpio_make_output(sc, GPIO_SSI_DCE);
1585
1586 /* Set CRC length. */
1587 if (sc->config.crc_len == CFG_CRC_32)
1588 mii16_set_bits(sc, MII16_SSI_CRC32);
1589 else
1590 mii16_clr_bits(sc, MII16_SSI_CRC32);
1591
1592 /* Loop towards host thru cable drivers and receivers. */
1593 /* Asserts DCD at the far end of a null modem cable. */
1594 if (sc->config.loop_back == CFG_LOOP_PINS)
1595 mii16_set_bits(sc, MII16_SSI_LOOP);
1596 else
1597 mii16_clr_bits(sc, MII16_SSI_LOOP);
1598
1599 /* Assert pin LL in modem conn: ask modem for local loop. */
1600 /* Asserts TM at the far end of a null modem cable. */
1601 if (sc->config.loop_back == CFG_LOOP_LL)
1602 mii16_set_bits(sc, MII16_SSI_LL);
1603 else
1604 mii16_clr_bits(sc, MII16_SSI_LL);
1605
1606 /* Assert pin RL in modem conn: ask modem for remote loop. */
1607 if (sc->config.loop_back == CFG_LOOP_RL)
1608 mii16_set_bits(sc, MII16_SSI_RL);
1609 else
1610 mii16_clr_bits(sc, MII16_SSI_RL);
1611 }
1612
1613 static void
1614 ssi_detach(softc_t *sc)
1615 {
1616 mii16_clr_bits(sc, (MII16_SSI_DTR | MII16_SSI_RTS | MII16_SSI_DCD));
1617 led_on(sc, MII16_LED_ALL);
1618 }
1619
1620 /* End SSI card code */
1621
1622 /* Begin T1E1 card code */
1623
1624 static struct card t1_card =
1625 {
1626 .ident = t1_ident,
1627 .watchdog = t1_watchdog,
1628 .ioctl = t1_ioctl,
1629 .attach = t1_attach,
1630 .detach = t1_detach,
1631 };
1632
1633 static void
1634 t1_ident(softc_t *sc)
1635 {
1636 printf(", Bt837%x rev %x",
1637 framer_read(sc, Bt8370_DID)>>4,
1638 framer_read(sc, Bt8370_DID)&0x0F);
1639 }
1640
1641 static void /* context: softirq */
1642 t1_watchdog(softc_t *sc)
1643 {
1644 u_int16_t LCV = 0, FERR = 0, CRC = 0, FEBE = 0;
1645 u_int8_t alm1, alm3, loop, isr0;
1646 int i;
1647
1648 sc->status.link_state = STATE_UP;
1649
1650 /* Read the alarm registers */
1651 alm1 = framer_read(sc, Bt8370_ALM1);
1652 alm3 = framer_read(sc, Bt8370_ALM3);
1653 loop = framer_read(sc, Bt8370_LOOP);
1654 isr0 = framer_read(sc, Bt8370_ISR0);
1655
1656 /* Always ignore the SIGFRZ alarm bit, */
1657 alm1 &= ~ALM1_SIGFRZ;
1658 if (FORMAT_T1ANY) /* ignore RYEL in T1 modes */
1659 alm1 &= ~ALM1_RYEL;
1660 else if (FORMAT_E1NONE) /* ignore all alarms except LOS */
1661 alm1 &= ALM1_RLOS;
1662
1663 /* Software is alive. */
1664 led_inv(sc, MII16_T1_LED_GRN);
1665
1666 /* Receiving Alarm Indication Signal (AIS). */
1667 if (alm1 & ALM1_RAIS) /* receiving ais */
1668 led_on(sc, MII16_T1_LED_BLU);
1669 else if (alm1 & ALM1_RLOS) /* sending ais */
1670 led_inv(sc, MII16_T1_LED_BLU);
1671 else
1672 led_off(sc, MII16_T1_LED_BLU);
1673
1674 /* Receiving Remote Alarm Indication (RAI). */
1675 if (alm1 & (ALM1_RMYEL | ALM1_RYEL)) /* receiving rai */
1676 led_on(sc, MII16_T1_LED_YEL);
1677 else if (alm1 & ALM1_RLOF) /* sending rai */
1678 led_inv(sc, MII16_T1_LED_YEL);
1679 else
1680 led_off(sc, MII16_T1_LED_YEL);
1681
1682 /* If any alarm bits are set then the link is 'down'. */
1683 /* The bad bits are: rmyel ryel rais ralos rlos rlof. */
1684 /* Some alarm bits have been masked by this point. */
1685 if (alm1) sc->status.link_state = STATE_DOWN;
1686
1687 /* Declare local Red Alarm if the link is down. */
1688 if (sc->status.link_state == STATE_DOWN)
1689 led_on(sc, MII16_T1_LED_RED);
1690 else if (sc->loop_timer) /* loopback is active */
1691 led_inv(sc, MII16_T1_LED_RED);
1692 else
1693 led_off(sc, MII16_T1_LED_RED);
1694
1695 /* Print latched error bits if they changed. */
1696 if ((sc->config.debug) && (alm1 != sc->last_alm1))
1697 {
1698 const char *on = "ON ", *off = "OFF";
1699 printf("%s: RLOF=%s RLOS=%s RALOS=%s RAIS=%s RYEL=%s RMYEL=%s\n",
1700 NAME_UNIT,
1701 (alm1 & ALM1_RLOF) ? on : off,
1702 (alm1 & ALM1_RLOS) ? on : off,
1703 (alm1 & ALM1_RALOS) ? on : off,
1704 (alm1 & ALM1_RAIS) ? on : off,
1705 (alm1 & ALM1_RYEL) ? on : off,
1706 (alm1 & ALM1_RMYEL) ? on : off);
1707 }
1708
1709 /* Check and print error counters if non-zero. */
1710 LCV = framer_read(sc, Bt8370_LCV_LO) +
1711 (framer_read(sc, Bt8370_LCV_HI)<<8);
1712 if (!FORMAT_E1NONE)
1713 FERR = framer_read(sc, Bt8370_FERR_LO) +
1714 (framer_read(sc, Bt8370_FERR_HI)<<8);
1715 if (FORMAT_E1CRC || FORMAT_T1ESF)
1716 CRC = framer_read(sc, Bt8370_CRC_LO) +
1717 (framer_read(sc, Bt8370_CRC_HI)<<8);
1718 if (FORMAT_E1CRC)
1719 FEBE = framer_read(sc, Bt8370_FEBE_LO) +
1720 (framer_read(sc, Bt8370_FEBE_HI)<<8);
1721 /* Only LCV is valid if Out-Of-Frame */
1722 if (FORMAT_E1NONE) FERR = CRC = FEBE = 0;
1723 if ((sc->config.debug) && (LCV || FERR || CRC || FEBE))
1724 printf("%s: LCV=%u FERR=%u CRC=%u FEBE=%u\n",
1725 NAME_UNIT, LCV, FERR, CRC, FEBE);
1726
1727 /* Driver keeps crude link-level error counters (SNMP is better). */
1728 sc->status.cntrs.lcv_errs += LCV;
1729 sc->status.cntrs.frm_errs += FERR;
1730 sc->status.cntrs.crc_errs += CRC;
1731 sc->status.cntrs.febe_errs += FEBE;
1732
1733 /* Check for BOP messages in the ESF Facility Data Link. */
1734 if ((FORMAT_T1ESF) && (framer_read(sc, Bt8370_ISR1) & 0x80))
1735 {
1736 u_int8_t bop_code = framer_read(sc, Bt8370_RBOP) & 0x3F;
1737
1738 switch (bop_code)
1739 {
1740 case T1BOP_OOF:
1741 {
1742 if ((sc->config.debug) && !(sc->last_alm1 & ALM1_RMYEL))
1743 printf("%s: Receiving a 'yellow alarm' BOP msg\n", NAME_UNIT);
1744 break;
1745 }
1746 case T1BOP_LINE_UP:
1747 {
1748 if (sc->config.debug)
1749 printf("%s: Received a 'line loopback activate' BOP msg\n", NAME_UNIT);
1750 framer_write(sc, Bt8370_LOOP, LOOP_LINE);
1751 sc->loop_timer = 305;
1752 break;
1753 }
1754 case T1BOP_LINE_DOWN:
1755 {
1756 if (sc->config.debug)
1757 printf("%s: Received a 'line loopback deactivate' BOP msg\n", NAME_UNIT);
1758 framer_write(sc, Bt8370_LOOP,
1759 framer_read(sc, Bt8370_LOOP) & ~LOOP_LINE);
1760 sc->loop_timer = 0;
1761 break;
1762 }
1763 case T1BOP_PAY_UP:
1764 {
1765 if (sc->config.debug)
1766 printf("%s: Received a 'payload loopback activate' BOP msg\n", NAME_UNIT);
1767 framer_write(sc, Bt8370_LOOP, LOOP_PAYLOAD);
1768 sc->loop_timer = 305;
1769 break;
1770 }
1771 case T1BOP_PAY_DOWN:
1772 {
1773 if (sc->config.debug)
1774 printf("%s: Received a 'payload loopback deactivate' BOP msg\n", NAME_UNIT);
1775 framer_write(sc, Bt8370_LOOP,
1776 framer_read(sc, Bt8370_LOOP) & ~LOOP_PAYLOAD);
1777 sc->loop_timer = 0;
1778 break;
1779 }
1780 default:
1781 {
1782 if (sc->config.debug)
1783 printf("%s: Received a type 0x%02X BOP msg\n", NAME_UNIT, bop_code);
1784 break;
1785 }
1786 }
1787 }
1788
1789 /* Check for HDLC pkts in the ESF Facility Data Link. */
1790 if ((FORMAT_T1ESF) && (framer_read(sc, Bt8370_ISR2) & 0x70))
1791 {
1792 /* while (not fifo-empty && not start-of-msg) flush fifo */
1793 while ((framer_read(sc, Bt8370_RDL1_STAT) & 0x0C)==0)
1794 framer_read(sc, Bt8370_RDL1);
1795 /* If (not fifo-empty), then begin processing fifo contents. */
1796 if ((framer_read(sc, Bt8370_RDL1_STAT) & 0x0C) == 0x08)
1797 {
1798 u_int8_t msg[64];
1799 u_int8_t stat = framer_read(sc, Bt8370_RDL1);
1800 sc->status.cntrs.fdl_pkts++;
1801 for (i=0; i<(stat & 0x3F); i++)
1802 msg[i] = framer_read(sc, Bt8370_RDL1);
1803 /* Is this FDL message a T1.403 performance report? */
1804 if (((stat & 0x3F)==11) &&
1805 ((msg[0]==0x38) || (msg[0]==0x3A)) &&
1806 (msg[1]==1) && (msg[2]==3))
1807 /* Copy 4 PRs from FDL pkt to SNMP struct. */
1808 memcpy(sc->status.snmp.t1.prm, msg+3, 8);
1809 }
1810 }
1811
1812 /* Check for inband loop up/down commands. */
1813 if (FORMAT_T1ANY)
1814 {
1815 u_int8_t isr6 = framer_read(sc, Bt8370_ISR6);
1816 u_int8_t alarm2 = framer_read(sc, Bt8370_ALM2);
1817 u_int8_t tlb = framer_read(sc, Bt8370_TLB);
1818
1819 /* Inband Code == Loop Up && On Transition && Inband Tx Inactive */
1820 if ((isr6 & 0x40) && (alarm2 & 0x40) && !(tlb & 1))
1821 { /* CSU loop up is 10000 10000 ... */
1822 if (sc->config.debug)
1823 printf("%s: Received a 'CSU Loop Up' inband msg\n", NAME_UNIT);
1824 framer_write(sc, Bt8370_LOOP, LOOP_LINE); /* Loop up */
1825 sc->loop_timer = 305;
1826 }
1827 /* Inband Code == Loop Down && On Transition && Inband Tx Inactive */
1828 if ((isr6 & 0x80) && (alarm2 & 0x80) && !(tlb & 1))
1829 { /* CSU loop down is 100 100 100 ... */
1830 if (sc->config.debug)
1831 printf("%s: Received a 'CSU Loop Down' inband msg\n", NAME_UNIT);
1832 framer_write(sc, Bt8370_LOOP,
1833 framer_read(sc, Bt8370_LOOP) & ~LOOP_LINE); /* loop down */
1834 sc->loop_timer = 0;
1835 }
1836 }
1837
1838 /* Manually send Yellow Alarm BOP msgs. */
1839 if (FORMAT_T1ESF)
1840 {
1841 u_int8_t isr7 = framer_read(sc, Bt8370_ISR7);
1842
1843 if ((isr7 & 0x02) && (alm1 & 0x02)) /* RLOF on-transition */
1844 { /* Start sending continuous Yellow Alarm BOP messages. */
1845 framer_write(sc, Bt8370_BOP, RBOP_25 | TBOP_CONT);
1846 framer_write(sc, Bt8370_TBOP, 0x00); /* send BOP; order matters */
1847 }
1848 else if ((isr7 & 0x02) && !(alm1 & 0x02)) /* RLOF off-transition */
1849 { /* Stop sending continuous Yellow Alarm BOP messages. */
1850 framer_write(sc, Bt8370_BOP, RBOP_25 | TBOP_OFF);
1851 }
1852 }
1853
1854 /* Time out loopback requests. */
1855 if (sc->loop_timer)
1856 if (--sc->loop_timer == 0)
1857 if (loop)
1858 {
1859 if (sc->config.debug)
1860 printf("%s: Timeout: Loop Down after 300 seconds\n", NAME_UNIT);
1861 framer_write(sc, Bt8370_LOOP, loop & ~(LOOP_PAYLOAD | LOOP_LINE));
1862 }
1863
1864 /* RX Test Pattern status */
1865 if ((sc->config.debug) && (isr0 & 0x10))
1866 printf("%s: RX Test Pattern Sync\n", NAME_UNIT);
1867
1868 /* SNMP Error Counters */
1869 sc->status.snmp.t1.lcv = LCV;
1870 sc->status.snmp.t1.fe = FERR;
1871 sc->status.snmp.t1.crc = CRC;
1872 sc->status.snmp.t1.febe = FEBE;
1873
1874 /* SNMP Line Status */
1875 sc->status.snmp.t1.line = 0;
1876 if (alm1 & ALM1_RMYEL) sc->status.snmp.t1.line |= TLINE_RX_RAI;
1877 if (alm1 & ALM1_RYEL) sc->status.snmp.t1.line |= TLINE_RX_RAI;
1878 if (alm1 & ALM1_RLOF) sc->status.snmp.t1.line |= TLINE_TX_RAI;
1879 if (alm1 & ALM1_RAIS) sc->status.snmp.t1.line |= TLINE_RX_AIS;
1880 if (alm1 & ALM1_RLOS) sc->status.snmp.t1.line |= TLINE_TX_AIS;
1881 if (alm1 & ALM1_RLOF) sc->status.snmp.t1.line |= TLINE_LOF;
1882 if (alm1 & ALM1_RLOS) sc->status.snmp.t1.line |= TLINE_LOS;
1883 if (alm3 & ALM3_RMAIS) sc->status.snmp.t1.line |= T1LINE_RX_TS16_AIS;
1884 if (alm3 & ALM3_SRED) sc->status.snmp.t1.line |= T1LINE_TX_TS16_LOMF;
1885 if (alm3 & ALM3_SEF) sc->status.snmp.t1.line |= T1LINE_SEF;
1886 if (isr0 & 0x10) sc->status.snmp.t1.line |= T1LINE_RX_TEST;
1887 if ((alm1 & ALM1_RMYEL) && (FORMAT_E1CAS))
1888 sc->status.snmp.t1.line |= T1LINE_RX_TS16_LOMF;
1889
1890 /* SNMP Loopback Status */
1891 sc->status.snmp.t1.loop &= ~(TLOOP_FAR_LINE | TLOOP_FAR_PAYLOAD);
1892 if (sc->config.loop_back == CFG_LOOP_TULIP)
1893 sc->status.snmp.t1.loop |= TLOOP_NEAR_OTHER;
1894 if (loop & LOOP_PAYLOAD) sc->status.snmp.t1.loop |= TLOOP_NEAR_PAYLOAD;
1895 if (loop & LOOP_LINE) sc->status.snmp.t1.loop |= TLOOP_NEAR_LINE;
1896 if (loop & LOOP_ANALOG) sc->status.snmp.t1.loop |= TLOOP_NEAR_OTHER;
1897 if (loop & LOOP_FRAMER) sc->status.snmp.t1.loop |= TLOOP_NEAR_INWARD;
1898
1899 /* Remember this state until next time. */
1900 sc->last_alm1 = alm1;
1901
1902 /* If an INWARD loopback is in effect, link status is UP */
1903 if (sc->config.loop_back != CFG_LOOP_NONE) /* XXX INWARD ONLY */
1904 sc->status.link_state = STATE_UP;
1905 }
1906
1907 static void /* context: process */
1908 t1_send_bop(softc_t *sc, int bop_code)
1909 {
1910 u_int8_t bop;
1911 int i;
1912
1913 /* The BOP transmitter could be sending a continuous */
1914 /* BOP msg when told to send this BOP_25 message. */
1915 /* So save and restore the state of the BOP machine. */
1916 bop = framer_read(sc, Bt8370_BOP);
1917 framer_write(sc, Bt8370_BOP, RBOP_OFF | TBOP_OFF);
1918 for (i=0; i<40; i++) /* max delay 400 ms. */
1919 if (framer_read(sc, Bt8370_BOP_STAT) & 0x80) SLEEP(10000);
1920 /* send 25 repetitions of bop_code */
1921 framer_write(sc, Bt8370_BOP, RBOP_OFF | TBOP_25);
1922 framer_write(sc, Bt8370_TBOP, bop_code); /* order matters */
1923 /* wait for tx to stop */
1924 for (i=0; i<40; i++) /* max delay 400 ms. */
1925 if (framer_read(sc, Bt8370_BOP_STAT) & 0x80) SLEEP(10000);
1926 /* Restore previous state of the BOP machine. */
1927 framer_write(sc, Bt8370_BOP, bop);
1928 }
1929
1930 static int /* context: process */
1931 t1_ioctl(softc_t *sc, struct ioctl *ioctl)
1932 {
1933 int error = 0;
1934
1935 switch (ioctl->cmd)
1936 {
1937 case IOCTL_SNMP_SEND: /* set opstatus? */
1938 {
1939 switch (ioctl->data)
1940 {
1941 case TSEND_NORMAL:
1942 {
1943 framer_write(sc, Bt8370_TPATT, 0x00); /* tx pattern generator off */
1944 framer_write(sc, Bt8370_RPATT, 0x00); /* rx pattern detector off */
1945 framer_write(sc, Bt8370_TLB, 0x00); /* tx inband generator off */
1946 break;
1947 }
1948 case TSEND_LINE:
1949 {
1950 if (FORMAT_T1ESF)
1951 t1_send_bop(sc, T1BOP_LINE_UP);
1952 else if (FORMAT_T1SF)
1953 {
1954 framer_write(sc, Bt8370_LBP, 0x08); /* 10000 10000 ... */
1955 framer_write(sc, Bt8370_TLB, 0x05); /* 5 bits, framed, start */
1956 }
1957 sc->status.snmp.t1.loop |= TLOOP_FAR_LINE;
1958 break;
1959 }
1960 case TSEND_PAYLOAD:
1961 {
1962 t1_send_bop(sc, T1BOP_PAY_UP);
1963 sc->status.snmp.t1.loop |= TLOOP_FAR_PAYLOAD;
1964 break;
1965 }
1966 case TSEND_RESET:
1967 {
1968 if (sc->status.snmp.t1.loop == TLOOP_FAR_LINE)
1969 {
1970 if (FORMAT_T1ESF)
1971 t1_send_bop(sc, T1BOP_LINE_DOWN);
1972 else if (FORMAT_T1SF)
1973 {
1974 framer_write(sc, Bt8370_LBP, 0x24); /* 100100 100100 ... */
1975 framer_write(sc, Bt8370_TLB, 0x09); /* 6 bits, framed, start */
1976 }
1977 sc->status.snmp.t1.loop &= ~TLOOP_FAR_LINE;
1978 }
1979 if (sc->status.snmp.t1.loop == TLOOP_FAR_PAYLOAD)
1980 {
1981 t1_send_bop(sc, T1BOP_PAY_DOWN);
1982 sc->status.snmp.t1.loop &= ~TLOOP_FAR_PAYLOAD;
1983 }
1984 break;
1985 }
1986 case TSEND_QRS:
1987 {
1988 framer_write(sc, Bt8370_TPATT, 0x1E); /* framed QRSS */
1989 break;
1990 }
1991 default:
1992 {
1993 error = EINVAL;
1994 break;
1995 }
1996 }
1997 break;
1998 }
1999 case IOCTL_SNMP_LOOP: /* set opstatus = test? */
2000 {
2001 u_int8_t new_loop = 0;
2002
2003 if (ioctl->data == CFG_LOOP_NONE)
2004 new_loop = 0;
2005 else if (ioctl->data == CFG_LOOP_PAYLOAD)
2006 new_loop = LOOP_PAYLOAD;
2007 else if (ioctl->data == CFG_LOOP_LINE)
2008 new_loop = LOOP_LINE;
2009 else if (ioctl->data == CFG_LOOP_OTHER)
2010 new_loop = LOOP_ANALOG;
2011 else if (ioctl->data == CFG_LOOP_INWARD)
2012 new_loop = LOOP_FRAMER;
2013 else if (ioctl->data == CFG_LOOP_DUAL)
2014 new_loop = LOOP_DUAL;
2015 else
2016 error = EINVAL;
2017 if (!error)
2018 {
2019 framer_write(sc, Bt8370_LOOP, new_loop);
2020 sc->config.loop_back = ioctl->data;
2021 }
2022 break;
2023 }
2024 case IOCTL_SET_STATUS:
2025 {
2026 #if 0
2027 if (ioctl->data)
2028 mii16_set_bits(sc, MII16_T1_XOE);
2029 else
2030 mii16_clr_bits(sc, MII16_T1_XOE);
2031 #endif
2032 break;
2033 }
2034 default:
2035 error = EINVAL;
2036 break;
2037 }
2038
2039 return error;
2040 }
2041
2042 /* Must not sleep. */
2043 static void
2044 t1_attach(softc_t *sc, struct config *config)
2045 {
2046 int i;
2047 u_int8_t pulse, lbo, gain;
2048
2049 if (config == NULL) /* startup config */
2050 {
2051 /* Disable transmitter output drivers. */
2052 mii16_clr_bits(sc, MII16_T1_XOE);
2053 /* Bt8370 occasionally powers up in a loopback mode. */
2054 /* Data sheet says zero LOOP reg and do a sw-reset. */
2055 framer_write(sc, Bt8370_LOOP, 0x00); /* no loopback */
2056 framer_write(sc, Bt8370_CR0, 0x80); /* sw-reset */
2057 for (i=0; i<10; i++) /* wait for sw-reset to clear; max 10 ms */
2058 if (framer_read(sc, Bt8370_CR0) & 0x80) DELAY(1000);
2059
2060 sc->status.card_type = CSID_LMC_T1E1;
2061 sc->config.crc_len = CFG_CRC_16;
2062 sc->config.loop_back = CFG_LOOP_NONE;
2063 sc->config.tx_clk_src = CFG_CLKMUX_RT; /* loop timed */
2064 #if 1 /* USA */ /* decide using time zone? */
2065 sc->config.format = CFG_FORMAT_T1ESF;
2066 #else /* REST OF PLANET */
2067 sc->config.format = CFG_FORMAT_E1FASCRC;
2068 #endif
2069 sc->config.time_slots = 0xFFFFFFFF;
2070 sc->config.cable_len = 10;
2071 sc->config.tx_pulse = CFG_PULSE_AUTO;
2072 sc->config.rx_gain_max = CFG_GAIN_AUTO;
2073 sc->config.tx_lbo = CFG_LBO_AUTO;
2074 }
2075 else if (config != &sc->config) /* change config */
2076 {
2077 if ((sc->config.crc_len == config->crc_len) &&
2078 (sc->config.loop_back == config->loop_back) &&
2079 (sc->config.tx_clk_src == config->tx_clk_src) &&
2080 (sc->config.format == config->format) &&
2081 (sc->config.time_slots == config->time_slots) &&
2082 (sc->config.cable_len == config->cable_len) &&
2083 (sc->config.tx_pulse == config->tx_pulse) &&
2084 (sc->config.rx_gain_max == config->rx_gain_max) &&
2085 (sc->config.tx_lbo == config->tx_lbo))
2086 return; /* nothing changed */
2087 sc->config.crc_len = config->crc_len;
2088 sc->config.loop_back = config->loop_back;
2089 sc->config.tx_clk_src = config->tx_clk_src;
2090 sc->config.format = config->format;
2091 sc->config.cable_len = config->cable_len;
2092 sc->config.time_slots = config->time_slots;
2093 sc->config.tx_pulse = config->tx_pulse;
2094 sc->config.rx_gain_max = config->rx_gain_max;
2095 sc->config.tx_lbo = config->tx_lbo;
2096 }
2097
2098 /* Set CRC length. */
2099 if (sc->config.crc_len == CFG_CRC_32)
2100 mii16_set_bits(sc, MII16_T1_CRC32);
2101 else
2102 mii16_clr_bits(sc, MII16_T1_CRC32);
2103
2104 /* Invert HDLC payload data in SF/AMI mode. */
2105 /* HDLC stuff bits satisfy T1 pulse density. */
2106 if (FORMAT_T1SF)
2107 mii16_set_bits(sc, MII16_T1_INVERT);
2108 else
2109 mii16_clr_bits(sc, MII16_T1_INVERT);
2110
2111 /* Set the transmitter output impedance. */
2112 if (FORMAT_E1ANY) mii16_set_bits(sc, MII16_T1_Z);
2113
2114 /* 001:CR0 -- Control Register 0 - T1/E1 and frame format */
2115 framer_write(sc, Bt8370_CR0, sc->config.format);
2116
2117 /* 002:JAT_CR -- Jitter Attenuator Control Register */
2118 if (sc->config.tx_clk_src == CFG_CLKMUX_RT) /* loop timing */
2119 framer_write(sc, Bt8370_JAT_CR, 0xA3); /* JAT in RX path */
2120 else
2121 { /* 64-bit elastic store; free-running JCLK and CLADO */
2122 framer_write(sc, Bt8370_JAT_CR, 0x4B); /* assert jcenter */
2123 framer_write(sc, Bt8370_JAT_CR, 0x43); /* release jcenter */
2124 }
2125
2126 /* 00C-013:IERn -- Interrupt Enable Registers */
2127 for (i=Bt8370_IER7; i<=Bt8370_IER0; i++)
2128 framer_write(sc, i, 0); /* no interrupts; polled */
2129
2130 /* 014:LOOP -- loopbacks */
2131 if (sc->config.loop_back == CFG_LOOP_PAYLOAD)
2132 framer_write(sc, Bt8370_LOOP, LOOP_PAYLOAD);
2133 else if (sc->config.loop_back == CFG_LOOP_LINE)
2134 framer_write(sc, Bt8370_LOOP, LOOP_LINE);
2135 else if (sc->config.loop_back == CFG_LOOP_OTHER)
2136 framer_write(sc, Bt8370_LOOP, LOOP_ANALOG);
2137 else if (sc->config.loop_back == CFG_LOOP_INWARD)
2138 framer_write(sc, Bt8370_LOOP, LOOP_FRAMER);
2139 else if (sc->config.loop_back == CFG_LOOP_DUAL)
2140 framer_write(sc, Bt8370_LOOP, LOOP_DUAL);
2141 else
2142 framer_write(sc, Bt8370_LOOP, 0x00); /* no loopback */
2143
2144 /* 015:DL3_TS -- Data Link 3 */
2145 framer_write(sc, Bt8370_DL3_TS, 0x00); /* disabled */
2146
2147 /* 018:PIO -- Programmable I/O */
2148 framer_write(sc, Bt8370_PIO, 0xFF); /* all pins are outputs */
2149
2150 /* 019:POE -- Programmable Output Enable */
2151 framer_write(sc, Bt8370_POE, 0x00); /* all outputs are enabled */
2152
2153 /* 01A;CMUX -- Clock Input Mux */
2154 if (sc->config.tx_clk_src == CFG_CLKMUX_EXT)
2155 framer_write(sc, Bt8370_CMUX, 0x0C); /* external timing */
2156 else
2157 framer_write(sc, Bt8370_CMUX, 0x0F); /* internal timing */
2158
2159 /* 020:LIU_CR -- Line Interface Unit Config Register */
2160 framer_write(sc, Bt8370_LIU_CR, 0xC1); /* reset LIU, squelch */
2161
2162 /* 022:RLIU_CR -- RX Line Interface Unit Config Reg */
2163 /* Errata sheet says do not use freeze-short, but we do anyway! */
2164 framer_write(sc, Bt8370_RLIU_CR, 0xB1); /* AGC=2048, Long Eye */
2165
2166 /* Select Rx sensitivity based on cable length. */
2167 if ((gain = sc->config.rx_gain_max) == CFG_GAIN_AUTO)
2168 {
2169 if (sc->config.cable_len > 2000)
2170 gain = CFG_GAIN_EXTEND;
2171 else if (sc->config.cable_len > 1000)
2172 gain = CFG_GAIN_LONG;
2173 else if (sc->config.cable_len > 100)
2174 gain = CFG_GAIN_MEDIUM;
2175 else
2176 gain = CFG_GAIN_SHORT;
2177 }
2178
2179 /* 024:VGA_MAX -- Variable Gain Amplifier Max gain */
2180 framer_write(sc, Bt8370_VGA_MAX, gain);
2181
2182 /* 028:PRE_EQ -- Pre Equalizer */
2183 if (gain == CFG_GAIN_EXTEND)
2184 framer_write(sc, Bt8370_PRE_EQ, 0xE6); /* ON; thresh 6 */
2185 else
2186 framer_write(sc, Bt8370_PRE_EQ, 0xA6); /* OFF; thresh 6 */
2187
2188 /* 038-03C:GAINn -- RX Equalizer gain thresholds */
2189 framer_write(sc, Bt8370_GAIN0, 0x24);
2190 framer_write(sc, Bt8370_GAIN1, 0x28);
2191 framer_write(sc, Bt8370_GAIN2, 0x2C);
2192 framer_write(sc, Bt8370_GAIN3, 0x30);
2193 framer_write(sc, Bt8370_GAIN4, 0x34);
2194
2195 /* 040:RCR0 -- Receiver Control Register 0 */
2196 if (FORMAT_T1ESF)
2197 framer_write(sc, Bt8370_RCR0, 0x05); /* B8ZS, 2/5 FErrs */
2198 else if (FORMAT_T1SF)
2199 framer_write(sc, Bt8370_RCR0, 0x84); /* AMI, 2/5 FErrs */
2200 else if (FORMAT_E1NONE)
2201 framer_write(sc, Bt8370_RCR0, 0x41); /* HDB3, rabort */
2202 else if (FORMAT_E1CRC)
2203 framer_write(sc, Bt8370_RCR0, 0x09); /* HDB3, 3 FErrs or 915 CErrs */
2204 else /* E1 no CRC */
2205 framer_write(sc, Bt8370_RCR0, 0x19); /* HDB3, 3 FErrs */
2206
2207 /* 041:RPATT -- Receive Test Pattern configuration */
2208 framer_write(sc, Bt8370_RPATT, 0x3E); /* looking for framed QRSS */
2209
2210 /* 042:RLB -- Receive Loop Back code detector config */
2211 framer_write(sc, Bt8370_RLB, 0x09); /* 6 bits down; 5 bits up */
2212
2213 /* 043:LBA -- Loop Back Activate code */
2214 framer_write(sc, Bt8370_LBA, 0x08); /* 10000 10000 10000 ... */
2215
2216 /* 044:LBD -- Loop Back Deactivate code */
2217 framer_write(sc, Bt8370_LBD, 0x24); /* 100100 100100 100100 ... */
2218
2219 /* 045:RALM -- Receive Alarm signal configuration */
2220 framer_write(sc, Bt8370_RALM, 0x0C); /* yel_intg rlof_intg */
2221
2222 /* 046:LATCH -- Alarm/Error/Counter Latch register */
2223 framer_write(sc, Bt8370_LATCH, 0x1F); /* stop_cnt latch_{cnt,err,alm} */
2224
2225 /* Select Pulse Shape based on cable length (T1 only). */
2226 if ((pulse = sc->config.tx_pulse) == CFG_PULSE_AUTO)
2227 {
2228 if (FORMAT_T1ANY)
2229 {
2230 if (sc->config.cable_len > 200)
2231 pulse = CFG_PULSE_T1CSU;
2232 else if (sc->config.cable_len > 160)
2233 pulse = CFG_PULSE_T1DSX4;
2234 else if (sc->config.cable_len > 120)
2235 pulse = CFG_PULSE_T1DSX3;
2236 else if (sc->config.cable_len > 80)
2237 pulse = CFG_PULSE_T1DSX2;
2238 else if (sc->config.cable_len > 40)
2239 pulse = CFG_PULSE_T1DSX1;
2240 else
2241 pulse = CFG_PULSE_T1DSX0;
2242 }
2243 else
2244 pulse = CFG_PULSE_E1TWIST;
2245 }
2246
2247 /* Select Line Build Out based on cable length (T1CSU only). */
2248 if ((lbo = sc->config.tx_lbo) == CFG_LBO_AUTO)
2249 {
2250 if (pulse == CFG_PULSE_T1CSU)
2251 {
2252 if (sc->config.cable_len > 1500)
2253 lbo = CFG_LBO_0DB;
2254 else if (sc->config.cable_len > 1000)
2255 lbo = CFG_LBO_7DB;
2256 else if (sc->config.cable_len > 500)
2257 lbo = CFG_LBO_15DB;
2258 else
2259 lbo = CFG_LBO_22DB;
2260 }
2261 else
2262 lbo = 0;
2263 }
2264
2265 /* 068:TLIU_CR -- Transmit LIU Control Register */
2266 framer_write(sc, Bt8370_TLIU_CR, (0x40 | (lbo & 0x30) | (pulse & 0x0E)));
2267
2268 /* 070:TCR0 -- Transmit Framer Configuration */
2269 framer_write(sc, Bt8370_TCR0, sc->config.format>>1);
2270
2271 /* 071:TCR1 -- Transmitter Configuration */
2272 if (FORMAT_T1SF)
2273 framer_write(sc, Bt8370_TCR1, 0x43); /* tabort, AMI PDV enforced */
2274 else
2275 framer_write(sc, Bt8370_TCR1, 0x41); /* tabort, B8ZS or HDB3 */
2276
2277 /* 072:TFRM -- Transmit Frame format MYEL YEL MF FE CRC FBIT */
2278 if (sc->config.format == CFG_FORMAT_T1ESF)
2279 framer_write(sc, Bt8370_TFRM, 0x0B); /* - YEL MF - CRC FBIT */
2280 else if (sc->config.format == CFG_FORMAT_T1SF)
2281 framer_write(sc, Bt8370_TFRM, 0x19); /* - YEL MF - - FBIT */
2282 else if (sc->config.format == CFG_FORMAT_E1FAS)
2283 framer_write(sc, Bt8370_TFRM, 0x11); /* - YEL - - - FBIT */
2284 else if (sc->config.format == CFG_FORMAT_E1FASCRC)
2285 framer_write(sc, Bt8370_TFRM, 0x1F); /* - YEL MF FE CRC FBIT */
2286 else if (sc->config.format == CFG_FORMAT_E1FASCAS)
2287 framer_write(sc, Bt8370_TFRM, 0x31); /* MYEL YEL - - - FBIT */
2288 else if (sc->config.format == CFG_FORMAT_E1FASCRCCAS)
2289 framer_write(sc, Bt8370_TFRM, 0x3F); /* MYEL YEL MF FE CRC FBIT */
2290 else if (sc->config.format == CFG_FORMAT_E1NONE)
2291 framer_write(sc, Bt8370_TFRM, 0x00); /* NO FRAMING BITS AT ALL! */
2292
2293 /* 073:TERROR -- Transmit Error Insert */
2294 framer_write(sc, Bt8370_TERROR, 0x00); /* no errors, please! */
2295
2296 /* 074:TMAN -- Transmit Manual Sa-byte/FEBE configuration */
2297 framer_write(sc, Bt8370_TMAN, 0x00); /* none */
2298
2299 /* 075:TALM -- Transmit Alarm Signal Configuration */
2300 if (FORMAT_E1ANY)
2301 framer_write(sc, Bt8370_TALM, 0x38); /* auto_myel auto_yel auto_ais */
2302 else if (FORMAT_T1ANY)
2303 framer_write(sc, Bt8370_TALM, 0x18); /* auto_yel auto_ais */
2304
2305 /* 076:TPATT -- Transmit Test Pattern Configuration */
2306 framer_write(sc, Bt8370_TPATT, 0x00); /* disabled */
2307
2308 /* 077:TLB -- Transmit Inband Loopback Code Configuration */
2309 framer_write(sc, Bt8370_TLB, 0x00); /* disabled */
2310
2311 /* 090:CLAD_CR -- Clack Rate Adapter Configuration */
2312 if (FORMAT_T1ANY)
2313 framer_write(sc, Bt8370_CLAD_CR, 0x06); /* loop filter gain 1/2^6 */
2314 else
2315 framer_write(sc, Bt8370_CLAD_CR, 0x08); /* loop filter gain 1/2^8 */
2316
2317 /* 091:CSEL -- CLAD frequency Select */
2318 if (FORMAT_T1ANY)
2319 framer_write(sc, Bt8370_CSEL, 0x55); /* 1544 kHz */
2320 else
2321 framer_write(sc, Bt8370_CSEL, 0x11); /* 2048 kHz */
2322
2323 /* 092:CPHASE -- CLAD Phase detector */
2324 if (FORMAT_T1ANY)
2325 framer_write(sc, Bt8370_CPHASE, 0x22); /* phase compare @ 386 kHz */
2326 else
2327 framer_write(sc, Bt8370_CPHASE, 0x00); /* phase compare @ 2048 kHz */
2328
2329 if (FORMAT_T1ESF) /* BOP & PRM are enabled in T1ESF mode only. */
2330 {
2331 /* 0A0:BOP -- Bit Oriented Protocol messages */
2332 framer_write(sc, Bt8370_BOP, RBOP_25 | TBOP_OFF);
2333 /* 0A4:DL1_TS -- Data Link 1 Time Slot Enable */
2334 framer_write(sc, Bt8370_DL1_TS, 0x40); /* FDL bits in odd frames */
2335 /* 0A6:DL1_CTL -- Data Link 1 Control */
2336 framer_write(sc, Bt8370_DL1_CTL, 0x03); /* FCS mode, TX on, RX on */
2337 /* 0A7:RDL1_FFC -- Rx Data Link 1 Fifo Fill Control */
2338 framer_write(sc, Bt8370_RDL1_FFC, 0x30); /* assert "near full" at 48 */
2339 /* 0AA:PRM -- Performance Report Messages */
2340 framer_write(sc, Bt8370_PRM, 0x80);
2341 }
2342
2343 /* 0D0:SBI_CR -- System Bus Interface Configuration Register */
2344 if (FORMAT_T1ANY)
2345 framer_write(sc, Bt8370_SBI_CR, 0x47); /* 1.544 with 24 TS +Fbits */
2346 else
2347 framer_write(sc, Bt8370_SBI_CR, 0x46); /* 2.048 with 32 TS */
2348
2349 /* 0D1:RSB_CR -- Receive System Bus Configuration Register */
2350 /* Change RINDO & RFSYNC on falling edge of RSBCLKI. */
2351 framer_write(sc, Bt8370_RSB_CR, 0x70);
2352
2353 /* 0D2,0D3:RSYNC_{TS,BIT} -- Receive frame Sync offset */
2354 framer_write(sc, Bt8370_RSYNC_BIT, 0x00);
2355 framer_write(sc, Bt8370_RSYNC_TS, 0x00);
2356
2357 /* 0D4:TSB_CR -- Transmit System Bus Configuration Register */
2358 /* Change TINDO & TFSYNC on falling edge of TSBCLKI. */
2359 framer_write(sc, Bt8370_TSB_CR, 0x30);
2360
2361 /* 0D5,0D6:TSYNC_{TS,BIT} -- Transmit frame Sync offset */
2362 framer_write(sc, Bt8370_TSYNC_BIT, 0x00);
2363 framer_write(sc, Bt8370_TSYNC_TS, 0x00);
2364
2365 /* 0D7:RSIG_CR -- Receive SIGnalling Configuration Register */
2366 framer_write(sc, Bt8370_RSIG_CR, 0x00);
2367
2368 /* Assign and configure 64Kb TIME SLOTS. */
2369 /* TS24..TS1 must be assigned for T1, TS31..TS0 for E1. */
2370 /* Timeslots with no user data have RINDO and TINDO off. */
2371 for (sc->status.time_slots = 0, i=0; i<32; i++)
2372 {
2373 /* 0E0-0FF:SBCn -- System Bus Per-Channel Control */
2374 if (FORMAT_T1ANY && (i==0 || i>24))
2375 framer_write(sc, Bt8370_SBCn +i, 0x00); /* not assigned in T1 mode */
2376 else if (FORMAT_E1ANY && (i==0) && !FORMAT_E1NONE)
2377 framer_write(sc, Bt8370_SBCn +i, 0x01); /* assigned, TS0 o/h bits */
2378 else if (FORMAT_E1CAS && (i==16) && !FORMAT_E1NONE)
2379 framer_write(sc, Bt8370_SBCn +i, 0x01); /* assigned, TS16 o/h bits */
2380 else if ((sc->status.time_slots |= (sc->config.time_slots & (1<<i))))
2381 framer_write(sc, Bt8370_SBCn +i, 0x0D); /* assigned, RINDO, TINDO */
2382 else
2383 framer_write(sc, Bt8370_SBCn +i, 0x01); /* assigned, idle */
2384
2385 /* 100-11F:TPCn -- Transmit Per-Channel Control */
2386 if (FORMAT_E1CAS && (i==0))
2387 framer_write(sc, Bt8370_TPCn +i, 0x30); /* tidle, sig=0000 (MAS) */
2388 else if (FORMAT_E1CAS && (i==16))
2389 framer_write(sc, Bt8370_TPCn +i, 0x3B); /* tidle, sig=1011 (XYXX) */
2390 else if ((sc->config.time_slots & (1<<i)) == 0)
2391 framer_write(sc, Bt8370_TPCn +i, 0x20); /* tidle: use TSLIP_LOn */
2392 else
2393 framer_write(sc, Bt8370_TPCn +i, 0x00); /* nothing special */
2394
2395 /* 140-15F:TSLIP_LOn -- Transmit PCM Slip Buffer */
2396 framer_write(sc, Bt8370_TSLIP_LOn +i, 0x7F); /* idle chan data */
2397 /* 180-19F:RPCn -- Receive Per-Channel Control */
2398 framer_write(sc, Bt8370_RPCn +i, 0x00); /* nothing special */
2399 }
2400
2401 /* Enable transmitter output drivers. */
2402 mii16_set_bits(sc, MII16_T1_XOE);
2403 }
2404
2405 static void
2406 t1_detach(softc_t *sc)
2407 {
2408 led_on(sc, MII16_LED_ALL);
2409 }
2410
2411 /* End T1E1 card code */
2412
2413
2414 #if SYNC_PPP /* Linux */
2415
2416 static struct stack sync_ppp_stack =
2417 {
2418 .ioctl = sync_ppp_ioctl,
2419 .type = sync_ppp_type,
2420 .mtu = sync_ppp_mtu,
2421 .watchdog = sync_ppp_watchdog,
2422 .open = sync_ppp_open,
2423 .attach = sync_ppp_attach,
2424 .detach = sync_ppp_detach,
2425 };
2426
2427 static int /* context: process */
2428 sync_ppp_ioctl(softc_t *sc, struct ifreq *ifr, int cmd)
2429 {
2430 return sppp_do_ioctl(sc->netdev, ifr, cmd);
2431 }
2432
2433 static int /* context: interrupt */
2434 sync_ppp_type(softc_t *sc, struct sk_buff *skb)
2435 {
2436 return htons(ETH_P_WAN_PPP);
2437 }
2438
2439 static int /* context: process */
2440 sync_ppp_mtu(softc_t *sc, int mtu)
2441 {
2442 return ((mtu < 128) || (mtu > PPP_MTU)) ? -EINVAL : 0;
2443 }
2444
2445 static void /* context: softirq */
2446 sync_ppp_watchdog(softc_t *sc)
2447 {
2448 /* Notice when the link comes up. */
2449 if ((sc->last_link_state != STATE_UP) &&
2450 (sc->status.link_state == STATE_UP))
2451 sppp_reopen(sc->netdev);
2452
2453 /* Notice when the link goes down. */
2454 if ((sc->last_link_state == STATE_UP) &&
2455 (sc->status.link_state != STATE_UP))
2456 sppp_close(sc->netdev);
2457
2458 /* Report current line protocol. */
2459 sc->status.stack = STACK_SYNC_PPP;
2460 if (sc->sppp->pp_flags & PP_CISCO)
2461 sc->status.proto = PROTO_C_HDLC;
2462 else
2463 sc->status.proto = PROTO_PPP;
2464
2465 /* Report keep-alive status. */
2466 sc->status.keep_alive = sc->sppp->pp_flags & PP_KEEPALIVE;
2467 }
2468
2469 static int /* never fails */
2470 sync_ppp_open(softc_t *sc, struct config *config)
2471 {
2472 /* Refresh the keep_alive flag. */
2473 if (config->keep_alive)
2474 sc->sppp->pp_flags |= PP_KEEPALIVE;
2475 else
2476 sc->sppp->pp_flags &= ~PP_KEEPALIVE;
2477 sc->config.keep_alive = config->keep_alive;
2478
2479 /* Done if proto is not changing. */
2480 if (config->proto == sc->config.proto)
2481 return 0;
2482
2483 /* Close */
2484 sppp_close(sc->netdev);
2485
2486 /* Change line protocol. */
2487 switch (config->proto)
2488 {
2489 case PROTO_PPP:
2490 sc->sppp->pp_flags &= ~PP_CISCO;
2491 sc->netdev->type = ARPHRD_PPP;
2492 sc->config.proto = PROTO_PPP;
2493 break;
2494 default:
2495 case PROTO_C_HDLC:
2496 sc->sppp->pp_flags |= PP_CISCO;
2497 sc->netdev->type = ARPHRD_CISCO;
2498 sc->config.proto = PROTO_C_HDLC;
2499 break;
2500 }
2501
2502 /* Open */
2503 sppp_open(sc->netdev);
2504
2505 return 0;
2506 }
2507
2508 static int /* never fails */
2509 sync_ppp_attach(softc_t *sc, struct config *config)
2510 {
2511 sc->ppd = &sc->ppp_dev; /* struct ppp_device* */
2512 sc->netdev->priv = &sc->ppd; /* struct ppp_device** */
2513 sc->ppp_dev.dev = sc->netdev;
2514 sc->sppp = &sc->ppp_dev.sppp;
2515
2516 sppp_attach(&sc->ppp_dev);
2517 sc->netdev->do_ioctl = netdev_ioctl;
2518 config->keep_alive = 1;
2519
2520 sc->config.stack = STACK_SYNC_PPP;
2521 sc->stack = &sync_ppp_stack;
2522
2523 return 0;
2524 }
2525
2526 static int /* never fails */
2527 sync_ppp_detach(softc_t *sc)
2528 {
2529 sppp_close(sc->netdev);
2530 sppp_detach(sc->netdev);
2531
2532 netdev_setup(sc->netdev);
2533 sc->config.stack = STACK_NONE;
2534 sc->config.proto = PROTO_NONE;
2535 sc->stack = NULL;
2536
2537 return 0;
2538 }
2539
2540 #endif /* SYNC_PPP */
2541
2542 #if GEN_HDLC /* Linux only */
2543
2544 static struct stack gen_hdlc_stack =
2545 {
2546 .ioctl = gen_hdlc_ioctl,
2547 .type = gen_hdlc_type,
2548 .mtu = gen_hdlc_mtu,
2549 .watchdog = gen_hdlc_watchdog,
2550 .open = gen_hdlc_open,
2551 .attach = gen_hdlc_attach,
2552 .detach = gen_hdlc_detach,
2553 };
2554
2555 static int /* context: process */
2556 gen_hdlc_ioctl(softc_t *sc, struct ifreq *ifr, int cmd)
2557 {
2558 te1_settings settings;
2559 int error = 0;
2560
2561 if (cmd == SIOCWANDEV)
2562 switch (ifr->ifr_settings.type)
2563 {
2564 case IF_GET_IFACE: /* get interface config */
2565 {
2566 unsigned int size;
2567
2568 /* NOTE: This assumes struct sync_serial_settings has the */
2569 /* same layout as the first part of struct te1_settings. */
2570 if (sc->status.card_type == CSID_LMC_T1E1)
2571 {
2572 if (FORMAT_T1ANY) ifr->ifr_settings.type = IF_IFACE_T1;
2573 if (FORMAT_E1ANY) ifr->ifr_settings.type = IF_IFACE_E1;
2574 size = sizeof(te1_settings);
2575 }
2576 else
2577 {
2578 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
2579 size = sizeof(sync_serial_settings);
2580 }
2581 if (ifr->ifr_settings.size < size)
2582 {
2583 ifr->ifr_settings.size = size;
2584 return -ENOBUFS;
2585 }
2586 ifr->ifr_settings.size = size;
2587
2588 if (sc->config.tx_clk_src == CFG_CLKMUX_ST)
2589 settings.clock_type = CLOCK_EXT;
2590 if (sc->config.tx_clk_src == CFG_CLKMUX_INT)
2591 settings.clock_type = CLOCK_TXINT;
2592 if (sc->config.tx_clk_src == CFG_CLKMUX_RT)
2593 settings.clock_type = CLOCK_TXFROMRX;
2594 settings.loopback = (sc->config.loop_back != CFG_LOOP_NONE) ? 1:0;
2595 settings.clock_rate = sc->status.tx_speed;
2596 if (sc->status.card_type == CSID_LMC_T1E1)
2597 settings.slot_map = sc->status.time_slots;
2598
2599 error = copy_to_user(ifr->ifr_settings.ifs_ifsu.te1,
2600 &settings, size);
2601 break;
2602 }
2603 case IF_IFACE_SYNC_SERIAL: /* set interface config */
2604 case IF_IFACE_T1:
2605 case IF_IFACE_E1:
2606 {
2607 struct config config = sc->config;
2608
2609 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2610 if (ifr->ifr_settings.size > sizeof(te1_settings))
2611 return -ENOBUFS;
2612 error = copy_from_user(&settings,
2613 ifr->ifr_settings.ifs_ifsu.te1, sizeof(te1_settings));
2614
2615 if (settings.clock_type == CLOCK_EXT)
2616 config.tx_clk_src = CFG_CLKMUX_ST;
2617 else if (settings.clock_type == CLOCK_TXINT)
2618 config.tx_clk_src = CFG_CLKMUX_INT;
2619 else if (settings.clock_type == CLOCK_TXFROMRX)
2620 config.tx_clk_src = CFG_CLKMUX_RT;
2621
2622 if (settings.loopback)
2623 config.loop_back = CFG_LOOP_TULIP;
2624 else
2625 config.loop_back = CFG_LOOP_NONE;
2626
2627 tulip_loop(sc, &config);
2628 sc->card->attach(sc, &config);
2629 break;
2630 }
2631 default: /* Pass the rest to the line pkg. */
2632 {
2633 error = hdlc_ioctl(sc->netdev, ifr, cmd);
2634 break;
2635 }
2636 }
2637 else
2638 error = -EINVAL;
2639
2640 return error;
2641 }
2642
2643 static int /* context: interrupt */
2644 gen_hdlc_type(softc_t *sc, struct sk_buff *skb)
2645 {
2646 return hdlc_type_trans(skb, sc->netdev);
2647 }
2648
2649 static int /* context: process */
2650 gen_hdlc_mtu(softc_t *sc, int mtu)
2651 {
2652 return ((mtu < 68) || (mtu > HDLC_MAX_MTU)) ? -EINVAL : 0;
2653 }
2654
2655 static void /* context: softirq */
2656 gen_hdlc_watchdog(softc_t *sc)
2657 {
2658 /* Notice when the link comes up. */
2659 if ((sc->last_link_state != STATE_UP) &&
2660 (sc->status.link_state == STATE_UP))
2661 hdlc_set_carrier(1, sc->netdev);
2662
2663 /* Notice when the link goes down. */
2664 if ((sc->last_link_state == STATE_UP) &&
2665 (sc->status.link_state != STATE_UP))
2666 hdlc_set_carrier(0, sc->netdev);
2667
2668 /* Report current line protocol. */
2669 sc->status.stack = STACK_GEN_HDLC;
2670 switch (sc->hdlcdev->proto.id)
2671 {
2672 case IF_PROTO_PPP:
2673 {
2674 struct sppp* sppp = &sc->hdlcdev->state.ppp.pppdev.sppp;
2675 sc->status.keep_alive = sppp->pp_flags & PP_KEEPALIVE;
2676 sc->status.proto = PROTO_PPP;
2677 break;
2678 }
2679 case IF_PROTO_CISCO:
2680 sc->status.proto = PROTO_C_HDLC;
2681 break;
2682 case IF_PROTO_FR:
2683 sc->status.proto = PROTO_FRM_RLY;
2684 break;
2685 case IF_PROTO_HDLC:
2686 sc->status.proto = PROTO_IP_HDLC;
2687 break;
2688 case IF_PROTO_X25:
2689 sc->status.proto = PROTO_X25;
2690 break;
2691 case IF_PROTO_HDLC_ETH:
2692 sc->status.proto = PROTO_ETH_HDLC;
2693 break;
2694 default:
2695 sc->status.proto = PROTO_NONE;
2696 break;
2697 }
2698 }
2699
2700 static int
2701 gen_hdlc_open(softc_t *sc, struct config *config)
2702 {
2703 int error = 0;
2704
2705 /* Refresh the keep_alive flag. */
2706 if (sc->hdlcdev->proto.id == IF_PROTO_PPP)
2707 {
2708 struct sppp* sppp = &sc->hdlcdev->state.ppp.pppdev.sppp;
2709 if (config->keep_alive)
2710 sppp->pp_flags |= PP_KEEPALIVE;
2711 else
2712 sppp->pp_flags &= ~PP_KEEPALIVE;
2713 sc->config.keep_alive = config->keep_alive;
2714 }
2715
2716 /* Done if proto is not changing. */
2717 if (config->proto == sc->config.proto)
2718 return 0;
2719
2720 /* Close */
2721 hdlc_close(sc->netdev);
2722
2723 /* Generic-HDLC gets protocol params using copy_from_user().
2724 * This is a problem for a kernel-resident device driver.
2725 * Luckily, PPP does not need any params so no copy_from_user().
2726 */
2727
2728 /* Change line protocol. */
2729 if (config->proto == PROTO_PPP)
2730 {
2731 struct ifreq ifr;
2732 ifr.ifr_settings.size = 0;
2733 ifr.ifr_settings.type = IF_PROTO_PPP;
2734 hdlc_ioctl(sc->netdev, &ifr, SIOCWANDEV);
2735 }
2736 /* Changing to any protocol other than PPP */
2737 /* requires using the 'sethdlc' program. */
2738
2739 /* Open */
2740 if ((error = hdlc_open(sc->netdev)))
2741 {
2742 if (sc->config.debug)
2743 printk("%s: hdlc_open(): error %d\n", NAME_UNIT, error);
2744 if (error == -ENOSYS)
2745 printk("%s: Try 'sethdlc %s hdlc|ppp|cisco|fr'\n",
2746 NAME_UNIT, NAME_UNIT);
2747 sc->config.proto = PROTO_NONE;
2748 }
2749 else
2750 sc->config.proto = config->proto;
2751
2752 return error;
2753 }
2754
2755 static int /* never fails */
2756 gen_hdlc_attach(softc_t *sc, struct config *config)
2757 {
2758 sc->netdev->priv = sc->hdlcdev;
2759
2760 /* hdlc_attach(sc->netdev); */
2761 sc->netdev->mtu = HDLC_MAX_MTU;
2762 sc->hdlcdev->attach = gen_hdlc_card_params;
2763 sc->hdlcdev->xmit = netdev_start;
2764 config->keep_alive = 1;
2765
2766 sc->config.stack = STACK_GEN_HDLC;
2767 sc->stack = &gen_hdlc_stack;
2768
2769 return 0;
2770 }
2771
2772 static int /* never fails */
2773 gen_hdlc_detach(softc_t *sc)
2774 {
2775 hdlc_close(sc->netdev);
2776 /* hdlc_detach(sc->netdev); */
2777 hdlc_proto_detach(sc->hdlcdev);
2778 memset(&sc->hdlcdev->proto, 0, sizeof sc->hdlcdev->proto);
2779
2780 netdev_setup(sc->netdev);
2781 sc->config.stack = STACK_NONE;
2782 sc->config.proto = PROTO_NONE;
2783 sc->stack = NULL;
2784
2785 return 0;
2786 }
2787
2788 static int
2789 gen_hdlc_card_params(struct net_device *netdev,
2790 unsigned short encoding, unsigned short parity)
2791 {
2792 softc_t *sc = NETDEV2SC(netdev);
2793 struct config config = sc->config;
2794
2795 /* Encoding does not seem to apply to synchronous interfaces, */
2796 /* but Parity seems to be generic-HDLC's name for CRC. */
2797 if (parity == PARITY_CRC32_PR1_CCITT)
2798 config.crc_len = CFG_CRC_32;
2799 if (parity == PARITY_CRC16_PR1_CCITT)
2800 config.crc_len = CFG_CRC_16;
2801 sc->card->attach(sc, &config);
2802
2803 return 0;
2804 }
2805
2806 #endif /* GEN_HDLC */
2807
2808 #if P2P /* BSD/OS */
2809
2810 static struct stack p2p_stack =
2811 {
2812 .ioctl = p2p_stack_ioctl,
2813 .input = p2p_stack_input,
2814 .output = p2p_stack_output,
2815 .watchdog = p2p_stack_watchdog,
2816 .open = p2p_stack_open,
2817 .attach = p2p_stack_attach,
2818 .detach = p2p_stack_detach,
2819 };
2820
2821 static int /* context: process */
2822 p2p_stack_ioctl(softc_t *sc, u_long cmd, void *data)
2823 {
2824 return p2p_ioctl(sc->ifp, cmd, data);
2825 }
2826
2827 static void /* context: interrupt */
2828 p2p_stack_input(softc_t *sc, struct mbuf *mbuf)
2829 {
2830 struct mbuf *new_mbuf = mbuf;
2831
2832 while (new_mbuf)
2833 {
2834 sc->p2p->p2p_hdrinput(sc->p2p, new_mbuf->m_data, new_mbuf->m_len);
2835 new_mbuf = new_mbuf->m_next;
2836 }
2837 sc->p2p->p2p_input(sc->p2p, NULL);
2838 m_freem(mbuf);
2839 }
2840
2841 static void /* context: interrupt */
2842 p2p_stack_output(softc_t *sc)
2843 {
2844 if (!IFQ_IS_EMPTY(&sc->p2p->p2p_isnd))
2845 IFQ_DEQUEUE(&sc->p2p->p2p_isnd, sc->tx_mbuf);
2846 else
2847 IFQ_DEQUEUE(&sc->ifp->if_snd, sc->tx_mbuf);
2848 }
2849
2850 static void /* context: softirq */
2851 p2p_stack_watchdog(softc_t *sc)
2852 {
2853 /* Notice change in link status. */
2854 if ((sc->last_link_state != sc->status.link_state) &&
2855 /* if_slowtimo() can run before raw_init() has inited rawcb. */
2856 (sc->p2p->p2p_modem != NULL) && (rawcb.rcb_next != NULL))
2857 (*sc->p2p->p2p_modem)(sc->p2p, sc->status.link_state==STATE_UP);
2858
2859 /* Report current line protocol. */
2860 sc->status.stack = STACK_P2P;
2861 switch (sc->ifp->if_type)
2862 {
2863 case IFT_PPP:
2864 sc->status.proto = PROTO_PPP;
2865 break;
2866 case IFT_PTPSERIAL:
2867 sc->status.proto = PROTO_C_HDLC;
2868 break;
2869 case IFT_FRELAY:
2870 sc->status.proto = PROTO_FRM_RLY;
2871 break;
2872 default:
2873 sc->status.proto = PROTO_NONE;
2874 break;
2875 }
2876 }
2877
2878 static int
2879 p2p_stack_open(softc_t *sc, struct config *config)
2880 {
2881 int error = 0;
2882
2883 /* Done if proto is not changing. */
2884 if (config->proto == sc->config.proto)
2885 return 0;
2886
2887 if (error = p2p_stack_detach(sc))
2888 return error;
2889
2890 /* Change line protocol. */
2891 switch (config->proto)
2892 {
2893 case PROTO_PPP:
2894 sc->ifp->if_type = IFT_PPP;
2895 sc->config.proto = PROTO_PPP;
2896 break;
2897 case PROTO_C_HDLC:
2898 sc->ifp->if_type = IFT_PTPSERIAL;
2899 sc->config.proto = PROTO_C_HDLC;
2900 break;
2901 case PROTO_FRM_RLY:
2902 sc->ifp->if_type = IFT_FRELAY;
2903 sc->config.proto = PROTO_FRM_RLY;
2904 break;
2905 default:
2906 case PROTO_NONE:
2907 sc->ifp->if_type = IFT_NONE;
2908 sc->config.proto = PROTO_NONE;
2909 return 0;
2910 }
2911
2912 error = p2p_stack_attach(sc, config);
2913
2914 return error;
2915 }
2916
2917 static int
2918 p2p_stack_attach(softc_t *sc, struct config *config)
2919 {
2920 int error;
2921
2922 sc->p2p = &sc->p2pcom;
2923 sc->p2p->p2p_proto = 0; /* force p2p_attach to re-init */
2924
2925 if ((error = p2p_attach(sc->p2p))) /* calls bpfattach() */
2926 {
2927 if (sc->config.debug)
2928 printf("%s: p2p_attach(): error %d\n", NAME_UNIT, error);
2929 if (error == EPFNOSUPPORT)
2930 printf("%s: Try 'ifconfig %s linktype ppp|frelay|chdlc'\n",
2931 NAME_UNIT, NAME_UNIT);
2932 sc->config.stack = STACK_NONE; /* not attached to P2P */
2933 return error;
2934 }
2935 sc->p2p->p2p_mdmctl = p2p_mdmctl;
2936 sc->p2p->p2p_getmdm = p2p_getmdm;
2937
2938 sc->config.stack = STACK_P2P;
2939 sc->stack = &p2p_stack;
2940
2941 return 0;
2942 }
2943
2944 static int
2945 p2p_stack_detach(softc_t *sc)
2946 {
2947 int error = 0;
2948
2949 if ((error = p2p_detach(sc->p2p))) /* calls bfpdetach() */
2950 {
2951 if (sc->config.debug)
2952 printf("%s: p2p_detach(): error %d\n", NAME_UNIT, error);
2953 if (error == EBUSY)
2954 printf("%s: Try 'ifconfig %s down -remove'\n",
2955 NAME_UNIT, NAME_UNIT);
2956 sc->config.stack = STACK_P2P; /* still attached to P2P */
2957 return error;
2958 }
2959
2960 ifnet_setup(sc->ifp);
2961 sc->config.stack = STACK_NONE;
2962 sc->config.proto = PROTO_NONE;
2963 sc->stack = NULL;
2964
2965 return error;
2966 }
2967
2968 /* Callout from P2P: */
2969 /* Get the state of DCD (Data Carrier Detect). */
2970 static int /* never fails */
2971 p2p_getmdm(struct p2pcom *p2p, void *result)
2972 {
2973 softc_t *sc = IFP2SC(&p2p->p2p_if);
2974
2975 /* Non-zero is not good enough; TIOCM_CAR is 0x40. */
2976 *(int *)result = (sc->status.link_state==STATE_UP) ? TIOCM_CAR : 0;
2977
2978 return 0;
2979 }
2980
2981 /* Callout from P2P: */
2982 /* Set the state of DTR (Data Terminal Ready). */
2983 static int /* never fails */
2984 p2p_mdmctl(struct p2pcom *p2p, int flag)
2985 {
2986 softc_t *sc = IFP2SC(&p2p->p2p_if);
2987
2988 set_ready(sc, flag);
2989
2990 return 0;
2991 }
2992
2993 #endif /* P2P */
2994
2995 #if SPPP /* FreeBSD, NetBSD, OpenBSD */
2996
2997 static struct stack sppp_stack =
2998 {
2999 .ioctl = sppp_stack_ioctl,
3000 .input = sppp_stack_input,
3001 .output = sppp_stack_output,
3002 .watchdog = sppp_stack_watchdog,
3003 .open = sppp_stack_open,
3004 .attach = sppp_stack_attach,
3005 .detach = sppp_stack_detach,
3006 };
3007
3008 # if !defined(PP_FR)
3009 # define PP_FR 0
3010 # endif
3011 # if !defined(DLT_C_HDLC)
3012 # define DLT_C_HDLC DLT_PPP
3013 # endif
3014 # if !defined(DLT_FRELAY)
3015 # define DLT_FRELAY DLT_PPP
3016 # endif
3017
3018 static int /* context: process */
3019 sppp_stack_ioctl(softc_t *sc, u_long cmd, void *data)
3020 {
3021 return sppp_ioctl(sc->ifp, cmd, data);
3022 }
3023
3024 static void /* context: interrupt */
3025 sppp_stack_input(softc_t *sc, struct mbuf *mbuf)
3026 {
3027 sppp_input(sc->ifp, mbuf);
3028 }
3029
3030 static void /* context: interrupt */
3031 sppp_stack_output(softc_t *sc)
3032 {
3033 sc->tx_mbuf = sppp_dequeue(sc->ifp);
3034 }
3035
3036 static void /* context: softirq */
3037 sppp_stack_watchdog(softc_t *sc)
3038 {
3039 /* Notice when the link comes up. */
3040 if ((sc->last_link_state != STATE_UP) &&
3041 (sc->status.link_state == STATE_UP))
3042 sppp_tls(sc->sppp);
3043
3044 /* Notice when the link goes down. */
3045 if ((sc->last_link_state == STATE_UP) &&
3046 (sc->status.link_state != STATE_UP))
3047 sppp_tlf(sc->sppp);
3048
3049 /* Report current line protocol. */
3050 sc->status.stack = STACK_SPPP;
3051 if (sc->sppp->pp_flags & PP_CISCO)
3052 sc->status.proto = PROTO_C_HDLC;
3053 else
3054 sc->status.proto = PROTO_PPP;
3055
3056 /* Report keep-alive status. */
3057 sc->status.keep_alive = sc->sppp->pp_flags & PP_KEEPALIVE;
3058 }
3059
3060 static int /* never fails */
3061 sppp_stack_open(softc_t *sc, struct config *config)
3062 {
3063 /* Refresh the keep_alive flag. */
3064 if (config->keep_alive)
3065 sc->sppp->pp_flags |= PP_KEEPALIVE;
3066 else
3067 sc->sppp->pp_flags &= ~PP_KEEPALIVE;
3068 sc->config.keep_alive = config->keep_alive;
3069
3070 /* Done if proto is not changing. */
3071 if (config->proto == sc->config.proto)
3072 return 0;
3073
3074 /* Close */
3075 sc->ifp->if_flags &= ~IFF_UP; /* down */
3076 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL);
3077
3078 /* Change line protocol. */
3079 LMC_BPF_DETACH(sc);
3080 switch (config->proto)
3081 {
3082 case PROTO_PPP:
3083 {
3084 sc->sppp->pp_flags &= ~PP_CISCO;
3085 LMC_BPF_ATTACH(sc, DLT_PPP, 4);
3086 sc->config.proto = PROTO_PPP;
3087 break;
3088 }
3089
3090 default:
3091 case PROTO_C_HDLC:
3092 {
3093 sc->sppp->pp_flags |= PP_CISCO;
3094 LMC_BPF_ATTACH(sc, DLT_C_HDLC, 4);
3095 sc->config.proto = PROTO_C_HDLC;
3096 break;
3097 }
3098
3099 } /* switch(config->proto) */
3100
3101 /* Open */
3102 sc->ifp->if_flags |= IFF_UP; /* up and not running */
3103 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL);
3104
3105 return 0;
3106 }
3107
3108 static int /* never fails */
3109 sppp_stack_attach(softc_t *sc, struct config *config)
3110 {
3111 sc->sppp = &sc->spppcom;
3112
3113 LMC_BPF_ATTACH(sc, DLT_RAW, 0);
3114 sppp_attach(sc->ifp);
3115 sc->sppp->pp_tls = sppp_tls;
3116 sc->sppp->pp_tlf = sppp_tlf;
3117 config->keep_alive = 1;
3118
3119 sc->config.stack = STACK_SPPP;
3120 sc->stack = &sppp_stack;
3121
3122 return 0;
3123 }
3124
3125 static int /* never fails */
3126 sppp_stack_detach(softc_t *sc)
3127 {
3128 sc->ifp->if_flags &= ~IFF_UP; /* down */
3129 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL); /* close() */
3130 sppp_detach(sc->ifp);
3131 LMC_BPF_DETACH(sc);
3132
3133 ifnet_setup(sc->ifp);
3134 sc->config.stack = STACK_NONE;
3135 sc->config.proto = PROTO_NONE;
3136 sc->stack = NULL;
3137
3138 return 0;
3139 }
3140
3141 /* Callout from SPPP: */
3142 static void
3143 sppp_tls(struct sppp *sppp)
3144 {
3145 /* Calling pp_up/down() required by PPP mode in OpenBSD. */
3146 /* Calling pp_up/down() panics PPP mode in NetBSD. */
3147 /* Calling pp_up/down() breaks Cisco mode in FreeBSD. */
3148 if (!(sppp->pp_flags & PP_CISCO)) /* not Cisco */
3149 sppp->pp_up(sppp);
3150 }
3151
3152 /* Callout from SPPP: */
3153 static void
3154 sppp_tlf(struct sppp *sppp)
3155 {
3156 /* Calling pp_up/down() required by PPP mode in OpenBSD. */
3157 /* Calling pp_up/down() panics PPP mode in NetBSD. */
3158 /* Calling pp_up/down() breaks Cisco mode in FreeBSD. */
3159 if (!(sppp->pp_flags & PP_CISCO)) /* not Cisco */
3160 sppp->pp_down(sppp);
3161 }
3162
3163 #endif /* SPPP */
3164
3165 /* RawIP is built into the driver. */
3166
3167 static struct stack rawip_stack =
3168 {
3169 #if IFNET
3170 .ioctl = rawip_ioctl,
3171 .input = rawip_input,
3172 .output = rawip_output,
3173 #elif NETDEV
3174 .ioctl = rawip_ioctl,
3175 .type = rawip_type,
3176 .mtu = rawip_mtu,
3177 #endif
3178 .watchdog = rawip_watchdog,
3179 .open = rawip_open,
3180 .attach = rawip_attach,
3181 .detach = rawip_detach,
3182 };
3183
3184 #if IFNET
3185
3186 static int /* context: process */
3187 rawip_ioctl(softc_t *sc, u_long cmd, void *data)
3188 {
3189 struct ifreq *ifr = (struct ifreq *) data;
3190 int error = 0;
3191
3192 switch (cmd)
3193 {
3194 case SIOCADDMULTI:
3195 case SIOCDELMULTI:
3196 if (sc->config.debug)
3197 printf("%s: rawip_ioctl: SIOCADD/DELMULTI\n", NAME_UNIT);
3198 case SIOCSIFFLAGS:
3199 error = ifioctl_common(sc->ifp, cmd, data);
3200 break;
3201 case SIOCAIFADDR:
3202 case SIOCSIFDSTADDR:
3203 break;
3204 case SIOCINITIFADDR:
3205 sc->ifp->if_flags |= IFF_UP; /* a Unix tradition */
3206 break;
3207 case SIOCSIFMTU:
3208 if ((ifr->ifr_mtu < 72) || (ifr->ifr_mtu > 65535))
3209 error = EINVAL;
3210 else if ((error = ifioctl_common(sc->ifp, cmd, data)) == ENETRESET)
3211 error = 0;
3212 break;
3213 default:
3214 error = EINVAL;
3215 break;
3216 }
3217
3218 return error;
3219 }
3220
3221 static void /* context: interrupt */
3222 rawip_input(softc_t *sc, struct mbuf *mbuf)
3223 {
3224 ifnet_input(sc->ifp, mbuf);
3225 }
3226
3227 static void /* context: interrupt */
3228 rawip_output(softc_t *sc)
3229 {
3230 IFQ_DEQUEUE(&sc->ifp->if_snd, sc->tx_mbuf);
3231 }
3232
3233 #elif NETDEV
3234
3235 static int /* context: process */
3236 rawip_ioctl(softc_t *sc, struct ifreq *ifr, int cmd)
3237 {
3238 if (sc->config.debug)
3239 printk("%s: rawip_ioctl; cmd=0x%08x\n", NAME_UNIT, cmd);
3240 return -EINVAL;
3241 }
3242
3243 static int /* context: interrupt */
3244 rawip_type(softc_t *sc, struct sk_buff *skb)
3245 {
3246 if (skb->data[0]>>4 == 4)
3247 return htons(ETH_P_IP);
3248 else if (skb->data[0]>>4 == 6)
3249 return htons(ETH_P_IPV6);
3250 else
3251 return htons(ETH_P_HDLC);
3252 }
3253
3254 static int /* Process Context */
3255 rawip_mtu(softc_t *sc, int mtu)
3256 {
3257 return ((mtu < 72) || (mtu > 65535)) ? -EINVAL : 0;
3258 }
3259
3260 #endif /* IFNET */
3261
3262 static void /* context: softirq */
3263 rawip_watchdog(softc_t *sc)
3264 {
3265 #if IFNET
3266 if ((sc->status.link_state == STATE_UP) &&
3267 (sc->ifp->if_flags & IFF_UP))
3268 sc->ifp->if_flags |= IFF_RUNNING;
3269 if ((sc->status.link_state != STATE_UP) ||
3270 !(sc->ifp->if_flags & IFF_UP))
3271 sc->ifp->if_flags &= ~IFF_RUNNING;
3272 #endif /* IFNET */
3273
3274 /* Report current line protocol. */
3275 sc->status.stack = STACK_RAWIP;
3276 sc->status.proto = PROTO_IP_HDLC;
3277 }
3278
3279 static int
3280 rawip_open(softc_t *sc, struct config *config)
3281 {
3282 sc->config.proto = PROTO_IP_HDLC;
3283
3284 return 0;
3285 }
3286
3287 static int
3288 rawip_attach(softc_t *sc, struct config *config)
3289 {
3290 #if IFNET
3291 LMC_BPF_ATTACH(sc, DLT_RAW, 0);
3292 #endif
3293
3294 sc->config.stack = STACK_RAWIP;
3295 sc->stack = &rawip_stack;
3296
3297 return 0;
3298 }
3299
3300 static int
3301 rawip_detach(softc_t *sc)
3302 {
3303 #if IFNET
3304 LMC_BPF_DETACH(sc);
3305 ifnet_setup(sc->ifp);
3306 #elif NETDEV
3307 netdev_setup(sc->netdev);
3308 #endif
3309
3310 sc->config.stack = STACK_NONE;
3311 sc->config.proto = PROTO_NONE;
3312 sc->stack = NULL;
3313
3314 return 0;
3315 }
3316
3317 #if IFNET
3318
3319 /* Called to give a newly arrived pkt to higher levels. */
3320 /* Called from rxintr_cleanup() with bottom_lock held. */
3321 /* This is only used with rawip_stack on a BSD. */
3322 static void
3323 ifnet_input(struct ifnet *ifp, struct mbuf *mbuf)
3324 {
3325 softc_t *sc = IFP2SC(ifp);
3326 struct ifqueue *intrq;
3327 int isr = 0;
3328
3329 intrq = NULL; /* surpress compiler warning */
3330 # if INET
3331 if (mbuf->m_data[0]>>4 == 4)
3332 {
3333 isr = NETISR_IP;
3334 intrq = &ipintrq;
3335 }
3336 # endif /* INET */
3337
3338 # if INET6
3339 if (mbuf->m_data[0]>>4 == 6)
3340 {
3341 isr = NETISR_IPV6;
3342 intrq = &ip6intrq;
3343 }
3344 # endif /* INET6 */
3345
3346 if (isr)
3347 {
3348 if (!IF_QFULL(intrq))
3349 {
3350 /* ifnet_input() ENQUEUES in a hard interrupt. */
3351 /* ip_input() DEQUEUES in a soft interrupt. */
3352 /* Some BSD QUEUE routines are not interrupt-safe. */
3353 DISABLE_INTR; /* noop in FreeBSD */
3354 IF_ENQUEUE(intrq, mbuf);
3355 ENABLE_INTR; /* noop in FreeBSD */
3356 schednetisr(isr); /* wake up the network code */
3357 }
3358 else /* intrq is full */
3359 {
3360 m_freem(mbuf);
3361 sc->status.cntrs.idrops++;
3362 if (sc->config.debug)
3363 printf("%s: ifnet_input: rx pkt dropped: intrq full\n", NAME_UNIT);
3364 }
3365 }
3366 else /* isr is zero */
3367 {
3368 m_freem(mbuf);
3369 sc->status.cntrs.idrops++;
3370 if (sc->config.debug)
3371 printf("%s: ifnet_input: rx pkt dropped: not IPv4 or IPv6\n", NAME_UNIT);
3372 }
3373 }
3374
3375 /* sppp and p2p replace this with their own proc.
3376 * This is only used with rawip_stack on a BSD.
3377 * This procedure is very similar to ng_rcvdata().
3378 */
3379 static int /* context: process */
3380 ifnet_output(struct ifnet *ifp, struct mbuf *m,
3381 const struct sockaddr *dst, struct rtentry *rt)
3382 {
3383 softc_t *sc = IFP2SC(ifp);
3384 int error = 0;
3385
3386 /* Fail if the link is down. */
3387 if (sc->status.link_state != STATE_UP)
3388 {
3389 m_freem(m);
3390 sc->status.cntrs.odrops++;
3391 if (sc->config.debug)
3392 printf("%s: ifnet_output: tx pkt dropped: link down\n", NAME_UNIT);
3393 return ENETDOWN;
3394 }
3395
3396 /* ifnet_output() ENQUEUEs in a syscall or softirq. */
3397 /* txintr_setup() DEQUEUEs in a hard interrupt. */
3398 /* Some BSD QUEUE routines are not interrupt-safe. */
3399 {
3400 DISABLE_INTR; /* noop in FreeBSD */
3401 IFQ_ENQUEUE(&ifp->if_snd, m, NULL, error);
3402 ENABLE_INTR; /* noop in FreeBSD */
3403 }
3404
3405 if (error)
3406 {
3407 sc->status.cntrs.odrops++;
3408 if (sc->config.debug)
3409 printf("%s: ifnet_output: tx pkt dropped: IFQ_ENQUEUE(): error %d\n",
3410 NAME_UNIT, error);
3411 }
3412 else
3413 /* Process tx pkts; do not process rx pkts. */
3414 lmc_interrupt(sc, 0, 0);
3415
3416 return error;
3417 }
3418
3419 static int /* context: process */
3420 ifnet_ioctl(struct ifnet *ifp, u_long cmd, void *data)
3421 {
3422 softc_t *sc = IFP2SC(ifp);
3423 struct ifreq *ifr = (struct ifreq *) data;
3424 int error = 0;
3425
3426 /* Aquire ioctl/watchdog interlock. */
3427 if ((error = TOP_LOCK(sc))) return error;
3428
3429 switch (cmd)
3430 {
3431 /* Catch the IOCTLs used by lmcconfig. */
3432 case LMCIOCGSTAT:
3433 case LMCIOCGCFG:
3434 case LMCIOCSCFG:
3435 case LMCIOCREAD:
3436 case LMCIOCWRITE:
3437 case LMCIOCTL:
3438 error = lmc_ioctl(sc, cmd, data);
3439 break;
3440
3441 case SIOCSIFCAP:
3442 # if DEVICE_POLLING
3443 if ((ifr->ifr_reqcap & IFCAP_POLLING) &&
3444 !(ifp->if_capenable & IFCAP_POLLING) &&
3445 !(error = ether_poll_register(bsd_poll, ifp)))
3446 { /* enable polling */
3447 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_DISABLE);
3448 ifp->if_capenable |= IFCAP_POLLING;
3449 }
3450 else if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3451 (ifp->if_capenable & IFCAP_POLLING) &&
3452 !(error = ether_poll_deregister(ifp)))
3453 { /* disable polling */
3454 ifp->if_capenable &= ~IFCAP_POLLING;
3455 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_TXRX);
3456 }
3457 else
3458 error = EINVAL;
3459 # endif /* DEVICE_POLLING */
3460 break;
3461
3462 case SIOCSIFMEDIA: /* calls lmc_ifmedia_change() */
3463 case SIOCGIFMEDIA: /* calls ifmedia_status() */
3464 error = ifmedia_ioctl(ifp, ifr, &sc->ifm, cmd);
3465 break;
3466
3467
3468 /* Pass the rest to the line protocol. */
3469 default:
3470 if (sc->stack)
3471 error = sc->stack->ioctl(sc, cmd, data);
3472 else
3473 error = ENOSYS;
3474 break;
3475 }
3476
3477 /* release ioctl/watchdog interlock */
3478 TOP_UNLOCK(sc);
3479
3480 if (error && sc->config.debug)
3481 printf("%s: ifnet_ioctl: op=IO%s%s len=%3lu grp='%c' num=%3lu err=%d\n",
3482 NAME_UNIT, cmd&IOC_IN ? "W":"", cmd&IOC_OUT ? "R":"",
3483 IOCPARM_LEN(cmd), (char)IOCGROUP(cmd), cmd&0xFF, error);
3484
3485 return error;
3486 }
3487
3488 static void /* context: process */
3489 ifnet_start(struct ifnet *ifp)
3490 {
3491 softc_t *sc = IFP2SC(ifp);
3492
3493 /* Process tx pkts; do not process rx pkts. */
3494 lmc_interrupt(sc, 0, 0);
3495 }
3496
3497 static void /* context: softirq */
3498 ifnet_watchdog(struct ifnet *ifp)
3499 {
3500 softc_t *sc = IFP2SC(ifp);
3501 struct cntrs *cntrs = &sc->status.cntrs;
3502
3503 lmc_watchdog(sc); /* updates link_state */
3504
3505 if (sc->status.link_state == STATE_UP)
3506 ifp->if_link_state = LINK_STATE_UP;
3507 else
3508 ifp->if_link_state = LINK_STATE_DOWN;
3509
3510 /* Copy statistics from sc to ifp. */
3511 ifp->if_baudrate = sc->status.tx_speed;
3512 ifp->if_ibytes = cntrs->ibytes;
3513 ifp->if_obytes = cntrs->obytes;
3514 ifp->if_ipackets = cntrs->ipackets;
3515 ifp->if_opackets = cntrs->opackets;
3516 ifp->if_ierrors = cntrs->ierrors;
3517 ifp->if_oerrors = cntrs->oerrors;
3518 ifp->if_iqdrops = cntrs->idrops;
3519
3520 /* If the interface debug flag is set, set the driver debug flag. */
3521 if (sc->ifp->if_flags & IFF_DEBUG)
3522 sc->config.debug = 1;
3523
3524 /* Call this procedure again after one second. */
3525 ifp->if_timer = 1;
3526 }
3527
3528 /* This setup is for RawIP; SPPP and P2P change many items. */
3529 /* Note the similarity to linux's netdev_setup(). */
3530 static void
3531 ifnet_setup(struct ifnet *ifp)
3532 {
3533 ifp->if_flags = IFF_POINTOPOINT;
3534 ifp->if_flags |= IFF_SIMPLEX;
3535 ifp->if_flags |= IFF_NOARP;
3536 ifp->if_input = ifnet_input;
3537 ifp->if_output = ifnet_output;
3538 ifp->if_start = ifnet_start;
3539 ifp->if_ioctl = ifnet_ioctl;
3540 ifp->if_watchdog = ifnet_watchdog;
3541 ifp->if_timer = 1;
3542 ifp->if_type = IFT_PTPSERIAL;
3543 ifp->if_addrlen = 0;
3544 ifp->if_hdrlen = 0;
3545 ifp->if_mtu = MAX_DESC_LEN;
3546 }
3547
3548 /* Attach the ifnet kernel interface. */
3549 /* context: kernel (boot) or process (syscall) */
3550 static int
3551 ifnet_attach(softc_t *sc)
3552 {
3553 # if SPPP
3554 sc->ifp = &sc->spppcom.pp_if;
3555 # elif P2P
3556 sc->ifp = &sc->p2pcom.p2p_if;
3557 # else
3558 sc->ifp = &sc->ifnet;
3559 # endif
3560
3561 sc->ifp->if_softc = sc;
3562 ifnet_setup(sc->ifp);
3563
3564 # if DEVICE_POLLING
3565 sc->ifp->if_capabilities |= IFCAP_POLLING;
3566 # endif
3567
3568 /* Every OS does it differently! */
3569 strlcpy(sc->ifp->if_xname, device_xname(&sc->dev), IFNAMSIZ);
3570
3571 IFQ_SET_MAXLEN(&sc->ifp->if_snd, SNDQ_MAXLEN);
3572 IFQ_SET_READY(&sc->ifp->if_snd);
3573
3574 if_attach(sc->ifp);
3575
3576 if_alloc_sadl(sc->ifp);
3577
3578 ifmedia_setup(sc);
3579
3580 return 0;
3581 }
3582
3583 /* Detach the ifnet kernel interface. */
3584 /* context: kernel (boot) or process (syscall). */
3585 static void
3586 ifnet_detach(softc_t *sc)
3587 {
3588 ifmedia_delete_instance(&sc->ifm, IFM_INST_ANY);
3589
3590 # if DEVICE_POLLING
3591 if (sc->ifp->if_capenable & IFCAP_POLLING)
3592 ether_poll_deregister(sc->ifp);
3593 # endif
3594
3595 IFQ_PURGE(&sc->ifp->if_snd);
3596
3597 if_free_sadl(sc->ifp);
3598
3599 if_detach(sc->ifp);
3600
3601 }
3602
3603 static void
3604 ifmedia_setup(softc_t *sc)
3605 {
3606 /* Initialize ifmedia mechanism. */
3607 ifmedia_init(&sc->ifm, IFM_OMASK | IFM_GMASK | IFM_IMASK,
3608 lmc_ifmedia_change, ifmedia_status);
3609
3610 ifmedia_add(&sc->ifm, IFM_ETHER | IFM_NONE, 0, NULL);
3611 ifmedia_set(&sc->ifm, IFM_ETHER | IFM_NONE);
3612 }
3613
3614 /* SIOCSIFMEDIA: context: process. */
3615 static int
3616 lmc_ifmedia_change(struct ifnet *ifp)
3617 {
3618 softc_t *sc = IFP2SC(ifp);
3619 struct config config = sc->config;
3620 int media = sc->ifm.ifm_media;
3621 int error;
3622
3623
3624 /* ifconfig lmc0 mediaopt loopback */
3625 if (media & IFM_LOOP)
3626 config.loop_back = CFG_LOOP_TULIP;
3627 else
3628 config.loop_back = CFG_LOOP_NONE;
3629
3630 error = open_proto(sc, &config);
3631 tulip_loop(sc, &config);
3632 sc->card->attach(sc, &config);
3633
3634 return error;
3635 }
3636
3637 /* SIOCGIFMEDIA: context: process. */
3638 static void
3639 ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
3640 {
3641 softc_t *sc = IFP2SC(ifp);
3642
3643 ifmr->ifm_status = IFM_AVALID;
3644 if (sc->status.link_state == STATE_UP)
3645 ifmr->ifm_status |= IFM_ACTIVE;
3646
3647 if (sc->config.loop_back != CFG_LOOP_NONE)
3648 ifmr->ifm_active |= IFM_LOOP;
3649
3650 }
3651
3652 #endif /* IFNET */
3653
3654 #if NETDEV
3655
3656 /* This net_device method is called when IFF_UP goes true. */
3657 static int /* context: process */
3658 netdev_open(struct net_device *netdev)
3659 {
3660 softc_t *sc = NETDEV2SC(netdev);
3661
3662 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_TXRX);
3663 netif_start_queue(sc->netdev);
3664 set_ready(sc, 1);
3665
3666 return 0;
3667 }
3668
3669 /* This net_device method is called when IFF_UP goes false. */
3670 static int /* context: process */
3671 netdev_stop(struct net_device *netdev)
3672 {
3673 softc_t *sc = NETDEV2SC(netdev);
3674
3675 set_ready(sc, 0);
3676 netif_stop_queue(sc->netdev);
3677 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_DISABLE);
3678
3679 return 0;
3680 }
3681
3682 /* This net_device method hands outgoing packets to the transmitter. */
3683 /* With txintr_setup(), it implements output flow control. */
3684 static int /* context: netdev->xmit_lock held; BHs disabled */
3685 netdev_start(struct sk_buff *skb, struct net_device *netdev)
3686 {
3687 softc_t *sc = NETDEV2SC(netdev);
3688
3689 if (sc->tx_skb == NULL)
3690 {
3691 /* Put this skb where the transmitter will see it. */
3692 sc->tx_skb = skb;
3693
3694 /* Process tx pkts; do not process rx pkts. */
3695 lmc_interrupt(sc, 0, 0);
3696
3697 return NETDEV_TX_OK;
3698 }
3699 else
3700 {
3701 /* txintr_setup() calls netif_wake_queue(). */
3702 netif_stop_queue(netdev);
3703 return NETDEV_TX_BUSY;
3704 }
3705 }
3706
3707 # if NAPI
3708
3709 /* This net_device method services the card without interrupts. */
3710 /* With rxintr_cleanup(), it implements input flow control. */
3711 static int /* context: softirq */
3712 netdev_poll(struct net_device *netdev, int *budget)
3713 {
3714 softc_t *sc = NETDEV2SC(netdev);
3715 int received;
3716
3717 /* Handle the card interrupt with kernel ints enabled. */
3718 /* Allow processing up to netdev->quota incoming packets. */
3719 /* This is the ONLY time lmc_interrupt() may process rx pkts. */
3720 /* Otherwise (sc->quota == 0) and rxintr_cleanup() is a NOOP. */
3721 lmc_interrupt(sc, min(netdev->quota, *budget), 0);
3722
3723 /* Report number of rx packets processed. */
3724 received = netdev->quota - sc->quota;
3725 netdev->quota -= received;
3726 *budget -= received;
3727
3728 /* If quota prevented processing all rx pkts, leave rx ints disabled. */
3729 if (sc->quota == 0) /* this is off by one...but harmless */
3730 {
3731 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_TX);
3732 return 1; /* more pkts to handle -- reschedule */
3733 }
3734
3735 /* Remove self from poll list. */
3736 netif_rx_complete(netdev);
3737
3738 /* Enable card interrupts. */
3739 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_TXRX);
3740
3741 return 0; /* all pkts handled -- success */
3742 }
3743
3744 # endif /* NAPI */
3745
3746 /* This net_device method handles IOCTL syscalls. */
3747 static int /* context: process */
3748 netdev_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3749 {
3750 softc_t *sc = NETDEV2SC(netdev);
3751 int error = 0;
3752
3753 /* Aquire ioctl/watchdog interlock. */
3754 if ((error = TOP_LOCK(sc))) return error;
3755
3756 if ((cmd >= SIOCDEVPRIVATE) && (cmd <= SIOCDEVPRIVATE+15))
3757 {
3758 struct iohdr *iohdr = (struct iohdr *)ifr;
3759 u_int16_t direction = iohdr->direction;
3760 u_int16_t length = iohdr->length;
3761 char *user_addr = (char *)iohdr->iohdr;
3762 char *kern_addr = NULL;
3763
3764 if (iohdr->cookie != NGM_LMC_COOKIE)
3765 error = -EINVAL;
3766
3767 /* Emulate a BSD-style IOCTL syscall. */
3768 if (!error)
3769 error = (kern_addr = kmalloc(length, GFP_KERNEL)) ? 0: -ENOMEM;
3770 if (!error && (direction & DIR_IOW))
3771 error = copy_from_user(kern_addr, user_addr, length);
3772 if (!error)
3773 error = -lmc_ioctl(sc, (unsigned long)cmd, kern_addr);
3774 if (!error && (direction & DIR_IOR))
3775 error = copy_to_user(user_addr, kern_addr, length);
3776 kfree(kern_addr);
3777 }
3778 else if (sc->stack)
3779 error = sc->stack->ioctl(sc, ifr, cmd);
3780 else
3781 error = -ENOSYS;
3782 # if GEN_HDLC
3783 /* If generic-HDLC is present but not the currently-attached
3784 * stack, call hdlc_ioctl() anyway because proto must
3785 * be set using SIOCWANDEV or hdlc_open() will fail.
3786 */
3787 if (sc->stack != &gen_hdlc_stack)
3788 hdlc_ioctl(sc->netdev, ifr, cmd); /* ignore error result */
3789 # endif
3790
3791 /* Release ioctl/watchdog interlock. */
3792 TOP_UNLOCK(sc);
3793
3794 if (error && sc->config.debug)
3795 printk("%s: netdev_ioctl; cmd=0x%08x error=%d\n",
3796 NAME_UNIT, cmd, error);
3797
3798 return error;
3799 }
3800
3801 /* This net_device method sets the Maximum Tranmit Unit. */
3802 /* This driver does not limit MTU; stacks and protos do. */
3803 static int
3804 netdev_mtu(struct net_device *netdev, int mtu)
3805 {
3806 softc_t *sc = NETDEV2SC(netdev);
3807 int error = 0;
3808
3809 if (sc->stack)
3810 error = sc->stack->mtu(sc, mtu);
3811 else
3812 error = -ENOSYS;
3813
3814 if (!error)
3815 netdev->mtu = mtu;
3816
3817 return error;
3818 }
3819
3820 /* This net_device method restarts the transmitter if it hangs. */
3821 static void /* BHs disabled */
3822 netdev_timeout(struct net_device *netdev)
3823 {
3824 softc_t *sc = NETDEV2SC(netdev);
3825
3826 /* Process tx pkts; do not process rx pkts. */
3827 lmc_interrupt(sc, 0, 0);
3828 }
3829
3830 /* This net_device method returns a pointer to device statistics. */
3831 static struct net_device_stats * /* context: process */
3832 netdev_stats(struct net_device *netdev)
3833 {
3834 softc_t *sc = NETDEV2SC(netdev);
3835
3836 # if GEN_HDLC
3837 return &sc->hdlcdev->stats;
3838 # else
3839 return &sc->netdev_stats;
3840 # endif
3841 }
3842
3843 static void /* context: softirq */
3844 netdev_watchdog(unsigned long softc)
3845 {
3846 softc_t *sc = (softc_t *)softc;
3847 struct cntrs *cntrs = &sc->status.cntrs;
3848 struct net_device_stats *stats = netdev_stats(sc->netdev);
3849
3850 lmc_watchdog(sc); /* updates link_state */
3851
3852 /* Notice when the link comes up. */
3853 if ((sc->last_link_state != STATE_UP) &&
3854 (sc->status.link_state == STATE_UP))
3855 {
3856 netif_wake_queue(sc->netdev);
3857 netif_carrier_on(sc->netdev);
3858 }
3859
3860 /* Notice when the link goes down. */
3861 if ((sc->last_link_state == STATE_UP) &&
3862 (sc->status.link_state != STATE_UP))
3863 {
3864 netif_tx_disable(sc->netdev);
3865 netif_carrier_off(sc->netdev);
3866 }
3867
3868 /* Copy statistics from sc to netdev. */
3869 stats->rx_bytes = cntrs->ibytes;
3870 stats->tx_bytes = cntrs->obytes;
3871 stats->rx_packets = cntrs->ipackets;
3872 stats->tx_packets = cntrs->opackets;
3873 stats->rx_errors = cntrs->ierrors;
3874 stats->tx_errors = cntrs->oerrors;
3875 stats->rx_dropped = cntrs->idrops;
3876 stats->rx_missed_errors = cntrs->missed;
3877 stats->tx_dropped = cntrs->odrops;
3878 stats->rx_fifo_errors = cntrs->fifo_over;
3879 stats->rx_over_errors = cntrs->overruns;
3880 stats->tx_fifo_errors = cntrs->fifo_under;
3881 /*stats->tx_under_errors = cntrs=>underruns; */
3882
3883 /* If the interface debug flag is set, set the driver debug flag. */
3884 if (sc->netdev->flags & IFF_DEBUG)
3885 sc->config.debug = 1;
3886
3887 /* Call this procedure again after one second. */
3888 sc->wd_timer.expires = jiffies + HZ -8; /* -8 is a FUDGE factor */
3889 add_timer(&sc->wd_timer);
3890 }
3891
3892 /* This setup is for RawIP; Generic-HDLC changes many items. */
3893 /* Note the similarity to BSD's ifnet_setup(). */
3894 static void
3895 netdev_setup(struct net_device *netdev)
3896 {
3897 netdev->flags = IFF_POINTOPOINT;
3898 netdev->flags |= IFF_NOARP;
3899 netdev->open = netdev_open;
3900 netdev->stop = netdev_stop;
3901 netdev->hard_start_xmit = netdev_start;
3902 # if NAPI
3903 netdev->poll = netdev_poll;
3904 netdev->weight = 32; /* sc->rxring.num_descs; */
3905 # endif
3906 netdev->rebuild_header = NULL; /* no arp */
3907 netdev->hard_header = NULL; /* no arp */
3908 netdev->do_ioctl = netdev_ioctl;
3909 netdev->change_mtu = netdev_mtu;
3910 netdev->tx_timeout = netdev_timeout;
3911 netdev->get_stats = netdev_stats;
3912 netdev->watchdog_timeo = 1 * HZ;
3913 netdev->mtu = MAX_DESC_LEN;
3914 netdev->type = ARPHRD_HDLC;
3915 netdev->hard_header_len = 16;
3916 netdev->addr_len = 0;
3917 netdev->tx_queue_len = SNDQ_MAXLEN;
3918 /* The receiver generates frag-lists for packets >4032 bytes. */
3919 /* The transmitter accepts scatter/gather lists and frag-lists. */
3920 /* However Linux linearizes outgoing packets since our hardware */
3921 /* does not compute soft checksums. All that work for nothing! */
3922 /*netdev->features |= NETIF_F_SG; */
3923 /*netdev->features |= NETIF_F_FRAGLIST; */
3924 }
3925
3926 /* Attach the netdevice kernel interface. */
3927 /* context: kernel (boot) or process (syscall). */
3928 static int
3929 netdev_attach(softc_t *sc)
3930 {
3931 int error;
3932
3933 # if GEN_HDLC /* generic-hdlc line protocol pkg configured */
3934
3935 /* Allocate space for the HDLC network device struct. */
3936 /* Allocating a netdev and attaching to generic-HDLC should be separate. */
3937 if ((sc->netdev = alloc_hdlcdev(sc)) == NULL)
3938 {
3939 printk("%s: netdev_attach: alloc_hdlcdev() failed\n", DEVICE_NAME);
3940 return -ENOMEM;
3941 }
3942
3943 /* Initialize the basic network device struct. */
3944 /* This clobbers some netdev stuff set by alloc_hdlcdev(). */
3945 /* Our get_stats() and change_mtu() do the right thing. */
3946 netdev_setup(sc->netdev);
3947
3948 /* HACK: make the private eco-net pointer -> struct softc. */
3949 sc->netdev->ec_ptr = sc;
3950
3951 /* Cross-link pcidev and netdev. */
3952 SET_NETDEV_DEV(sc->netdev, &sc->pcidev->dev);
3953 sc->netdev->mem_end = pci_resource_end(sc->pcidev, 1);
3954 sc->netdev->mem_start = pci_resource_start(sc->pcidev, 1);
3955 sc->netdev->base_addr = pci_resource_start(sc->pcidev, 0);
3956 sc->netdev->irq = sc->pcidev->irq;
3957
3958 /* Initialize the HDLC extension to the network device. */
3959 sc->hdlcdev = sc->netdev->priv;
3960 sc->hdlcdev->attach = gen_hdlc_card_params;
3961 sc->hdlcdev->xmit = netdev_start; /* the REAL hard_start_xmit() */
3962
3963 if ((error = register_hdlc_device(sc->netdev)))
3964 {
3965 printk("%s: register_hdlc_device(): error %d\n", DEVICE_NAME, error);
3966 free_netdev(sc->netdev);
3967 return error;
3968 }
3969
3970 # else
3971
3972 /* Allocate and initialize the basic network device struct. */
3973 if ((sc->netdev = alloc_netdev(0, DEVICE_NAME"%d", netdev_setup)) == NULL)
3974 {
3975 printk("%s: netdev_attach: alloc_netdev() failed\n", DEVICE_NAME);
3976 return -ENOMEM;
3977 }
3978
3979 /* HACK: make the private eco-net pointer -> struct softc. */
3980 sc->netdev->ec_ptr = sc;
3981
3982 /* Cross-link pcidev and netdev. */
3983 SET_NETDEV_DEV(sc->netdev, &sc->pcidev->dev);
3984 sc->netdev->mem_end = pci_resource_end(sc->pcidev, 1);
3985 sc->netdev->mem_start = pci_resource_start(sc->pcidev, 1);
3986 sc->netdev->base_addr = pci_resource_start(sc->pcidev, 0);
3987 sc->netdev->irq = sc->pcidev->irq;
3988
3989 if ((error = register_netdev(sc->netdev)))
3990 {
3991 printk("%s: register_netdev(): error %d\n", DEVICE_NAME, error);
3992 free_netdev(sc->netdev);
3993 return error;
3994 }
3995
3996 # endif /* GEN_HDLC */
3997
3998 /* Arrange to call netdev_watchdog() once a second. */
3999 init_timer(&sc->wd_timer);
4000 sc->wd_timer.expires = jiffies + HZ; /* now plus one second */
4001 sc->wd_timer.function = &netdev_watchdog;
4002 sc->wd_timer.data = (unsigned long) sc;
4003 add_timer(&sc->wd_timer);
4004
4005 return 0; /* success */
4006 }
4007
4008 /* Detach the netdevice kernel interface. */
4009 /* context: kernel (boot) or process (syscall). */
4010 static void
4011 netdev_detach(softc_t *sc)
4012 {
4013 if (sc->pcidev == NULL) return;
4014 if (sc->netdev == NULL) return;
4015
4016 netdev_stop(sc->netdev); /* check for not inited */
4017 del_timer(&sc->wd_timer);
4018
4019 # if GEN_HDLC
4020 unregister_hdlc_device(sc->netdev);
4021 # else
4022 unregister_netdev(sc->netdev);
4023 # endif
4024
4025 free_netdev(sc->netdev);
4026 }
4027
4028 #endif /* NETDEV */
4029
4030
4031 #if BSD
4032
4033 /* There are TWO VERSIONS of interrupt/DMA code: Linux & BSD.
4034 * Handling Linux and the BSDs with CPP directives would
4035 * make the code unreadable, so there are two versions.
4036 * Conceptually, the two versions do the same thing and
4037 * lmc_interrupt() does not know they are different.
4038 *
4039 * We are "standing on the head of a pin" in these routines.
4040 * Tulip CSRs can be accessed, but nothing else is interrupt-safe!
4041 * Do NOT access: MII, GPIO, SROM, BIOSROM, XILINX, SYNTH, or DAC.
4042 */
4043
4044 /* Initialize a DMA descriptor ring. */
4045 /* context: kernel (boot) or process (syscall) */
4046 static int /* BSD version */
4047 create_ring(softc_t *sc, struct desc_ring *ring, int num_descs)
4048 {
4049 struct dma_desc *descs;
4050 int size_descs = sizeof(struct dma_desc)*num_descs;
4051 int i, error = 0;
4052
4053 /* The DMA descriptor array must not cross a page boundary. */
4054 if (size_descs > PAGE_SIZE)
4055 {
4056 printf("%s: DMA descriptor array > PAGE_SIZE (%d)\n", NAME_UNIT,
4057 (u_int)PAGE_SIZE);
4058 return EINVAL;
4059 }
4060
4061
4062 /* Use the DMA tag passed to attach() for descriptors and buffers. */
4063 ring->tag = sc->pa_dmat;
4064
4065 /* Allocate wired physical memory for DMA descriptor array. */
4066 if ((error = bus_dmamem_alloc(ring->tag, size_descs, PAGE_SIZE, 0,
4067 ring->segs, 1, &ring->nsegs, BUS_DMA_NOWAIT)))
4068 {
4069 printf("%s: bus_dmamem_alloc(): error %d\n", NAME_UNIT, error);
4070 return error;
4071 }
4072
4073 /* Map physical address to kernel virtual address. */
4074 if ((error = bus_dmamem_map(ring->tag, ring->segs, ring->nsegs,
4075 size_descs, (void **)&ring->first, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)))
4076 {
4077 printf("%s: bus_dmamem_map(): error %d\n", NAME_UNIT, error);
4078 return error;
4079 }
4080 descs = ring->first; /* suppress compiler warning about aliasing */
4081 memset(descs, 0, size_descs);
4082
4083 /* Allocate dmamap for PCI access to DMA descriptor array. */
4084 if ((error = bus_dmamap_create(ring->tag, size_descs, 1,
4085 size_descs, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ring->map)))
4086 {
4087 printf("%s: bus_dmamap_create(): error %d\n", NAME_UNIT, error);
4088 return error;
4089 }
4090
4091 /* Map kernel virt addr to PCI bus addr for DMA descriptor array. */
4092 if ((error = bus_dmamap_load(ring->tag, ring->map, descs, size_descs,
4093 0, BUS_DMA_NOWAIT)))
4094 {
4095 printf("%s: bus_dmamap_load(): error %d\n", NAME_UNIT, error);
4096 return error;
4097 }
4098 ring->dma_addr = ring->map->dm_segs[0].ds_addr;
4099
4100 /* Allocate dmamaps for each DMA descriptor. */
4101 for (i=0; i<num_descs; i++)
4102 if ((error = bus_dmamap_create(ring->tag, MAX_DESC_LEN, 2,
4103 MAX_CHUNK_LEN, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &descs[i].map)))
4104 {
4105 printf("%s: bus_dmamap_create(): error %d\n", NAME_UNIT, error);
4106 return error;
4107 }
4108
4109
4110 ring->read = descs;
4111 ring->write = descs;
4112 ring->first = descs;
4113 ring->last = descs + num_descs -1;
4114 ring->last->control = TLP_DCTL_END_RING;
4115 ring->num_descs = num_descs;
4116 ring->size_descs = size_descs;
4117 ring->head = NULL;
4118 ring->tail = NULL;
4119
4120 return 0;
4121 }
4122
4123 /* Destroy a DMA descriptor ring */
4124 /* context: kernel (boot) or process (syscall) */
4125 static void /* BSD version */
4126 destroy_ring(softc_t *sc, struct desc_ring *ring)
4127 {
4128 struct dma_desc *desc;
4129 struct mbuf *m;
4130
4131 /* Free queued mbufs. */
4132 while ((m = mbuf_dequeue(ring)))
4133 m_freem(m);
4134
4135 /* TX may have one pkt that is not on any queue. */
4136 if (sc->tx_mbuf)
4137 {
4138 m_freem(sc->tx_mbuf);
4139 sc->tx_mbuf = NULL;
4140 }
4141
4142 /* Unmap active DMA descriptors. */
4143 while (ring->read != ring->write)
4144 {
4145 bus_dmamap_unload(ring->tag, ring->read->map);
4146 if (ring->read++ == ring->last) ring->read = ring->first;
4147 }
4148
4149
4150 /* Free the dmamaps of all DMA descriptors. */
4151 for (desc=ring->first; desc!=ring->last+1; desc++)
4152 if (desc->map)
4153 bus_dmamap_destroy(ring->tag, desc->map);
4154 /* Unmap PCI address for DMA descriptor array. */
4155 if (ring->dma_addr)
4156 bus_dmamap_unload(ring->tag, ring->map);
4157 /* Free dmamap for DMA descriptor array. */
4158 if (ring->map)
4159 bus_dmamap_destroy(ring->tag, ring->map);
4160 /* Unmap kernel address for DMA descriptor array. */
4161 if (ring->first)
4162 bus_dmamem_unmap(ring->tag, (void *)ring->first, ring->size_descs);
4163 /* Free kernel memory for DMA descriptor array. */
4164 if (ring->segs[0].ds_addr)
4165 bus_dmamem_free(ring->tag, ring->segs, ring->nsegs);
4166
4167 }
4168
4169 /* Singly-linked tail-queues hold mbufs with active DMA.
4170 * For RX, single mbuf clusters; for TX, mbuf chains are queued.
4171 * NB: mbufs are linked through their m_nextpkt field.
4172 * Callers must hold sc->bottom_lock; not otherwise locked.
4173 */
4174
4175 /* Put an mbuf (chain) on the tail of the descriptor ring queue. */
4176 static void /* BSD version */
4177 mbuf_enqueue(struct desc_ring *ring, struct mbuf *m)
4178 {
4179 m->m_nextpkt = NULL;
4180 if (ring->tail == NULL)
4181 ring->head = m;
4182 else
4183 ring->tail->m_nextpkt = m;
4184 ring->tail = m;
4185 }
4186
4187 /* Get an mbuf (chain) from the head of the descriptor ring queue. */
4188 static struct mbuf* /* BSD version */
4189 mbuf_dequeue(struct desc_ring *ring)
4190 {
4191 struct mbuf *m = ring->head;
4192 if (m)
4193 if ((ring->head = m->m_nextpkt) == NULL)
4194 ring->tail = NULL;
4195 return m;
4196 }
4197
4198 /* Clean up after a packet has been received. */
4199 static int /* BSD version */
4200 rxintr_cleanup(softc_t *sc)
4201 {
4202 struct desc_ring *ring = &sc->rxring;
4203 struct dma_desc *first_desc, *last_desc;
4204 struct mbuf *first_mbuf=NULL, *last_mbuf=NULL;
4205 struct mbuf *new_mbuf;
4206 int pkt_len, desc_len;
4207
4208 /* Input packet flow control (livelock prevention): */
4209 /* Give pkts to higher levels only if quota is > 0. */
4210 if (sc->quota <= 0) return 0;
4211
4212 /* This looks complicated, but remember: typically packets up */
4213 /* to 2048 bytes long fit in one mbuf and use one descriptor. */
4214
4215 first_desc = last_desc = ring->read;
4216
4217 /* ASSERTION: If there is a descriptor in the ring and the hardware has */
4218 /* finished with it, then that descriptor will have RX_FIRST_DESC set. */
4219 if ((ring->read != ring->write) && /* descriptor ring not empty */
4220 !(ring->read->status & TLP_DSTS_OWNER) && /* hardware done */
4221 !(ring->read->status & TLP_DSTS_RX_FIRST_DESC)) /* should be set */
4222 panic("%s: rxintr_cleanup: rx-first-descriptor not set.\n", NAME_UNIT);
4223
4224 /* First decide if a complete packet has arrived. */
4225 /* Run down DMA descriptors looking for one marked "last". */
4226 /* Bail out if an active descriptor is encountered. */
4227 /* Accumulate most significant bits of packet length. */
4228 pkt_len = 0;
4229 for (;;)
4230 {
4231 if (last_desc == ring->write) return 0; /* no more descs */
4232 if (last_desc->status & TLP_DSTS_OWNER) return 0; /* still active */
4233 if (last_desc->status & TLP_DSTS_RX_LAST_DESC) break; /* end of packet */
4234 pkt_len += last_desc->length1 + last_desc->length2; /* entire desc filled */
4235 if (last_desc++->control & TLP_DCTL_END_RING) last_desc = ring->first; /* ring wrap */
4236 }
4237
4238 /* A complete packet has arrived; how long is it? */
4239 /* H/w ref man shows RX pkt length as a 14-bit field. */
4240 /* An experiment found that only the 12 LSBs work. */
4241 if (((last_desc->status>>16)&0xFFF) == 0) pkt_len += 4096; /* carry-bit */
4242 pkt_len = (pkt_len & 0xF000) + ((last_desc->status>>16) & 0x0FFF);
4243 /* Subtract the CRC length unless doing so would underflow. */
4244 if (pkt_len >= sc->config.crc_len) pkt_len -= sc->config.crc_len;
4245
4246 /* Run down DMA descriptors again doing the following:
4247 * 1) put pkt info in pkthdr of first mbuf,
4248 * 2) link mbufs,
4249 * 3) set mbuf lengths.
4250 */
4251 first_desc = ring->read;
4252 do
4253 {
4254 /* Read a DMA descriptor from the ring. */
4255 last_desc = ring->read;
4256 /* Advance the ring read pointer. */
4257 if (ring->read++ == ring->last) ring->read = ring->first;
4258
4259 /* Dequeue the corresponding cluster mbuf. */
4260 new_mbuf = mbuf_dequeue(ring);
4261 if (new_mbuf == NULL)
4262 panic("%s: rxintr_cleanup: expected an mbuf\n", NAME_UNIT);
4263
4264 desc_len = last_desc->length1 + last_desc->length2;
4265 /* If bouncing, copy bounce buf to mbuf. */
4266 DMA_SYNC(last_desc->map, desc_len, BUS_DMASYNC_POSTREAD);
4267 /* Unmap kernel virtual address to PCI bus address. */
4268 bus_dmamap_unload(ring->tag, last_desc->map);
4269
4270 /* 1) Put pkt info in pkthdr of first mbuf. */
4271 if (last_desc == first_desc)
4272 {
4273 first_mbuf = new_mbuf;
4274 first_mbuf->m_pkthdr.len = pkt_len; /* total pkt length */
4275 # if IFNET
4276 first_mbuf->m_pkthdr.rcvif = sc->ifp; /* how it got here */
4277 # else
4278 first_mbuf->m_pkthdr.rcvif = NULL;
4279 # endif
4280 }
4281 else /* 2) link mbufs. */
4282 {
4283 KASSERT(last_mbuf != NULL);
4284 last_mbuf->m_next = new_mbuf;
4285 /* M_PKTHDR should be set in the first mbuf only. */
4286 new_mbuf->m_flags &= ~M_PKTHDR;
4287 }
4288 last_mbuf = new_mbuf;
4289
4290 /* 3) Set mbuf lengths. */
4291 new_mbuf->m_len = (pkt_len >= desc_len) ? desc_len : pkt_len;
4292 pkt_len -= new_mbuf->m_len;
4293 } while ((last_desc->status & TLP_DSTS_RX_LAST_DESC)==0);
4294
4295 /* Decide whether to accept or to drop this packet. */
4296 /* RxHDLC sets MIIERR for bad CRC, abort and partial byte at pkt end. */
4297 if (!(last_desc->status & TLP_DSTS_RX_BAD) &&
4298 (sc->status.link_state == STATE_UP) &&
4299 (first_mbuf->m_pkthdr.len > 0))
4300 {
4301 /* Optimization: copy a small pkt into a small mbuf. */
4302 if (first_mbuf->m_pkthdr.len <= COPY_BREAK)
4303 {
4304 MGETHDR(new_mbuf, M_DONTWAIT, MT_DATA);
4305 if (new_mbuf)
4306 {
4307 new_mbuf->m_pkthdr.rcvif = first_mbuf->m_pkthdr.rcvif;
4308 new_mbuf->m_pkthdr.len = first_mbuf->m_pkthdr.len;
4309 new_mbuf->m_len = first_mbuf->m_len;
4310 memcpy(new_mbuf->m_data, first_mbuf->m_data,
4311 first_mbuf->m_pkthdr.len);
4312 m_freem(first_mbuf);
4313 first_mbuf = new_mbuf;
4314 }
4315 }
4316
4317 /* Include CRC and one flag byte in input byte count. */
4318 sc->status.cntrs.ibytes += first_mbuf->m_pkthdr.len + sc->config.crc_len +1;
4319 sc->status.cntrs.ipackets++;
4320
4321 /* Berkeley Packet Filter */
4322 LMC_BPF_MTAP(sc, first_mbuf);
4323
4324 /* Give this good packet to the network stacks. */
4325 sc->quota--;
4326 if (sc->stack)
4327 sc->stack->input(sc, first_mbuf);
4328 else
4329 {
4330 m_freem(first_mbuf);
4331 sc->status.cntrs.idrops++;
4332 }
4333 }
4334 else if (sc->status.link_state != STATE_UP)
4335 {
4336 /* If the link is down, this packet is probably noise. */
4337 m_freem(first_mbuf);
4338 sc->status.cntrs.idrops++;
4339 if (sc->config.debug)
4340 printf("%s: rxintr_cleanup: rx pkt dropped: link down\n", NAME_UNIT);
4341 }
4342 else /* Log and drop this bad packet. */
4343 {
4344 if (sc->config.debug)
4345 printf("%s: RX bad pkt; len=%d %s%s%s%s\n",
4346 NAME_UNIT, first_mbuf->m_pkthdr.len,
4347 (last_desc->status & TLP_DSTS_RX_MII_ERR) ? " miierr" : "",
4348 (last_desc->status & TLP_DSTS_RX_DRIBBLE) ? " dribble" : "",
4349 (last_desc->status & TLP_DSTS_RX_DESC_ERR) ? " descerr" : "",
4350 (last_desc->status & TLP_DSTS_RX_OVERRUN) ? " overrun" : "");
4351 if (last_desc->status & TLP_DSTS_RX_OVERRUN)
4352 sc->status.cntrs.fifo_over++;
4353 else
4354 sc->status.cntrs.ierrors++;
4355 m_freem(first_mbuf);
4356 }
4357
4358 return 1; /* did something */
4359 }
4360
4361 /* Setup (prepare) to receive a packet. */
4362 /* Try to keep the RX descriptor ring full of empty buffers. */
4363 static int /* BSD version */
4364 rxintr_setup(softc_t *sc)
4365 {
4366 struct desc_ring *ring = &sc->rxring;
4367 struct dma_desc *desc;
4368 struct mbuf *m;
4369 int desc_len;
4370 int error;
4371
4372 /* Ring is full if (wrap(write+1)==read) */
4373 if (((ring->write == ring->last) ? ring->first : ring->write+1) == ring->read)
4374 return 0; /* ring is full; nothing to do */
4375
4376 /* Allocate a small mbuf and attach an mbuf cluster. */
4377 MGETHDR(m, M_DONTWAIT, MT_DATA);
4378 if (m == NULL)
4379 {
4380 sc->status.cntrs.rxbuf++;
4381 if (sc->config.debug)
4382 printf("%s: rxintr_setup: MGETHDR() failed\n", NAME_UNIT);
4383 return 0;
4384 }
4385 MCLGET(m, M_DONTWAIT);
4386 if ((m->m_flags & M_EXT)==0)
4387 {
4388 m_freem(m);
4389 sc->status.cntrs.rxbuf++;
4390 if (sc->config.debug)
4391 printf("%s: rxintr_setup: MCLGET() failed\n", NAME_UNIT);
4392 return 0;
4393 }
4394
4395 /* Queue the mbuf for later processing by rxintr_cleanup. */
4396 mbuf_enqueue(ring, m);
4397
4398 /* Write a DMA descriptor into the ring. */
4399 /* Hardware will not see it until the OWNER bit is set. */
4400 desc = ring->write;
4401 /* Advance the ring write pointer. */
4402 if (ring->write++ == ring->last) ring->write = ring->first;
4403
4404 desc_len = (MCLBYTES < MAX_DESC_LEN) ? MCLBYTES : MAX_DESC_LEN;
4405 /* Map kernel virt addr to PCI bus addr. */
4406 if ((error = DMA_LOAD(desc->map, m->m_data, desc_len)))
4407 printf("%s: bus_dmamap_load(rx): error %d\n", NAME_UNIT, error);
4408 /* Invalidate the cache for this mbuf. */
4409 DMA_SYNC(desc->map, desc_len, BUS_DMASYNC_PREREAD);
4410
4411 /* Set up the DMA descriptor. */
4412 desc->address1 = desc->map->dm_segs[0].ds_addr;
4413 desc->length1 = desc_len>>1;
4414 desc->address2 = desc->address1 + desc->length1;
4415 desc->length2 = desc_len>>1;
4416
4417 /* Before setting the OWNER bit, flush cache backing DMA descriptors. */
4418 DMA_SYNC(ring->map, ring->size_descs, BUS_DMASYNC_PREWRITE);
4419
4420 /* Commit the DMA descriptor to the hardware. */
4421 desc->status = TLP_DSTS_OWNER;
4422
4423 /* Notify the receiver that there is another buffer available. */
4424 WRITE_CSR(sc, TLP_RX_POLL, 1);
4425
4426 return 1; /* did something */
4427 }
4428
4429 /* Clean up after a packet has been transmitted. */
4430 /* Free the mbuf chain and update the DMA descriptor ring. */
4431 static int /* BSD version */
4432 txintr_cleanup(softc_t *sc)
4433 {
4434 struct desc_ring *ring = &sc->txring;
4435 struct dma_desc *desc;
4436
4437 while ((ring->read != ring->write) && /* while ring is not empty */
4438 !(ring->read->status & TLP_DSTS_OWNER))
4439 {
4440 /* Read a DMA descriptor from the ring. */
4441 desc = ring->read;
4442 /* Advance the ring read pointer. */
4443 if (ring->read++ == ring->last) ring->read = ring->first;
4444
4445 /* This is a no-op on most architectures. */
4446 DMA_SYNC(desc->map, desc->length1 + desc->length2, BUS_DMASYNC_POSTWRITE);
4447 /* Unmap kernel virtual address to PCI bus address. */
4448 bus_dmamap_unload(ring->tag, desc->map);
4449
4450 /* If this descriptor is the last segment of a packet, */
4451 /* then dequeue and free the corresponding mbuf chain. */
4452 if (desc->control & TLP_DCTL_TX_LAST_SEG)
4453 {
4454 struct mbuf *m;
4455
4456 if ((m = mbuf_dequeue(ring)) == NULL)
4457 panic("%s: txintr_cleanup: expected an mbuf\n", NAME_UNIT);
4458
4459 /* The only bad TX status is fifo underrun. */
4460 if (desc->status & TLP_DSTS_TX_UNDERRUN)
4461 {
4462 if (sc->config.debug)
4463 printf("%s: txintr_cleanup: tx fifo underrun\n", NAME_UNIT);
4464 sc->status.cntrs.fifo_under++;
4465 sc->status.cntrs.oerrors++;
4466 }
4467 else
4468 {
4469 /* Include CRC and one flag byte in output byte count. */
4470 sc->status.cntrs.obytes += m->m_pkthdr.len + sc->config.crc_len +1;
4471 sc->status.cntrs.opackets++;
4472
4473 /* Berkeley Packet Filter */
4474 LMC_BPF_MTAP(sc, m);
4475 }
4476
4477 m_freem(m);
4478 return 1; /* did something */
4479 }
4480 }
4481
4482 return 0;
4483 }
4484
4485 /* Build DMA descriptors for a transmit packet mbuf chain. */
4486 static int /* 0=success; 1=error */ /* BSD version */
4487 txintr_setup_mbuf(softc_t *sc, struct mbuf *m)
4488 {
4489 struct desc_ring *ring = &sc->txring;
4490 struct dma_desc *desc;
4491 unsigned int desc_len;
4492
4493 /* build DMA descriptors for a chain of mbufs. */
4494 while (m)
4495 {
4496 char *data = m->m_data;
4497 int length = m->m_len; /* zero length mbufs happen! */
4498
4499 /* Build DMA descriptors for one mbuf. */
4500 while (length > 0)
4501 {
4502 int error;
4503
4504 /* Ring is full if (wrap(write+1)==read) */
4505 if (((ring->temp==ring->last) ? ring->first : ring->temp+1) == ring->read)
4506 { /* Not enough DMA descriptors; try later. */
4507 for (; ring->temp!=ring->write;
4508 ring->temp = (ring->temp==ring->first)? ring->last : ring->temp-1)
4509 bus_dmamap_unload(ring->tag, ring->temp->map);
4510 sc->status.cntrs.txdma++; /* IFF_OACTIVE? */
4511 return 1;
4512 }
4513
4514 /* Provisionally, write a descriptor into the ring. */
4515 /* But do not change the REAL ring write pointer. */
4516 /* Hardware will not see it until the OWNER bit is set. */
4517 desc = ring->temp;
4518 /* Advance the temporary ring write pointer. */
4519 if (ring->temp++ == ring->last) ring->temp = ring->first;
4520
4521 /* Clear all control bits except the END_RING bit. */
4522 desc->control &= TLP_DCTL_END_RING;
4523 /* Do not pad short packets up to 64 bytes. */
4524 desc->control |= TLP_DCTL_TX_NO_PAD;
4525 /* Use Tulip's CRC-32 generator, if appropriate. */
4526 if (sc->config.crc_len != CFG_CRC_32)
4527 desc->control |= TLP_DCTL_TX_NO_CRC;
4528 /* Set the OWNER bit, except in the first descriptor. */
4529 if (desc != ring->write)
4530 desc->status = TLP_DSTS_OWNER;
4531
4532 desc_len = (length > MAX_CHUNK_LEN) ? MAX_CHUNK_LEN : length;
4533 /* Map kernel virt addr to PCI bus addr. */
4534 if ((error = DMA_LOAD(desc->map, data, desc_len)))
4535 printf("%s: bus_dmamap_load(tx): error %d\n", NAME_UNIT, error);
4536 /* Flush the cache and if bouncing, copy mbuf to bounce buf. */
4537 DMA_SYNC(desc->map, desc_len, BUS_DMASYNC_PREWRITE);
4538
4539 /* Prevent wild fetches if mapping fails (nsegs==0). */
4540 desc->length1 = desc->length2 = 0;
4541 desc->address1 = desc->address2 = 0;
4542 {
4543 bus_dma_segment_t *segs = desc->map->dm_segs;
4544 int nsegs = desc->map->dm_nsegs;
4545 if (nsegs >= 1)
4546 {
4547 desc->address1 = segs[0].ds_addr;
4548 desc->length1 = segs[0].ds_len;
4549 }
4550 if (nsegs == 2)
4551 {
4552 desc->address2 = segs[1].ds_addr;
4553 desc->length2 = segs[1].ds_len;
4554 }
4555 }
4556
4557 data += desc_len;
4558 length -= desc_len;
4559 } /* while (length > 0) */
4560
4561 m = m->m_next;
4562 } /* while (m) */
4563
4564 return 0; /* success */
4565 }
4566
4567 /* Setup (prepare) to transmit a packet. */
4568 /* Select a packet, build DMA descriptors and give packet to hardware. */
4569 /* If DMA descriptors run out, abandon the attempt and return 0. */
4570 static int /* BSD version */
4571 txintr_setup(softc_t *sc)
4572 {
4573 struct desc_ring *ring = &sc->txring;
4574 struct dma_desc *first_desc, *last_desc;
4575
4576 /* Protect against half-up links: Do not transmit */
4577 /* if the receiver can not hear the far end. */
4578 if (sc->status.link_state != STATE_UP) return 0;
4579
4580 /* Pick a packet to transmit. */
4581 if ((sc->tx_mbuf == NULL) && sc->stack)
4582 sc->stack->output(sc);
4583 if (sc->tx_mbuf == NULL) return 0; /* no pkt to transmit */
4584
4585 /* Build DMA descriptors for an outgoing mbuf chain. */
4586 ring->temp = ring->write; /* temporary ring write pointer */
4587 if (txintr_setup_mbuf(sc, sc->tx_mbuf)) return 0;
4588
4589 /* Enqueue the mbuf; txintr_cleanup will free it. */
4590 mbuf_enqueue(ring, sc->tx_mbuf);
4591
4592 /* The transmitter has room for another packet. */
4593 sc->tx_mbuf = NULL;
4594
4595 /* Set first & last segment bits. */
4596 /* last_desc is the desc BEFORE the one pointed to by ring->temp. */
4597 first_desc = ring->write;
4598 first_desc->control |= TLP_DCTL_TX_FIRST_SEG;
4599 last_desc = (ring->temp==ring->first)? ring->last : ring->temp-1;
4600 last_desc->control |= TLP_DCTL_TX_LAST_SEG;
4601 /* Interrupt at end-of-transmission? Why bother the poor computer! */
4602 /* last_desc->control |= TLP_DCTL_TX_INTERRUPT; */
4603
4604 /* Make sure the OWNER bit is not set in the next descriptor. */
4605 /* The OWNER bit may have been set if a previous call aborted. */
4606 ring->temp->status = 0;
4607
4608 /* Commit the DMA descriptors to the software. */
4609 ring->write = ring->temp;
4610
4611 /* Before setting the OWNER bit, flush cache backing DMA descriptors. */
4612 DMA_SYNC(ring->map, ring->size_descs, BUS_DMASYNC_PREWRITE);
4613
4614 /* Commit the DMA descriptors to the hardware. */
4615 first_desc->status = TLP_DSTS_OWNER;
4616
4617 /* Notify the transmitter that there is another packet to send. */
4618 WRITE_CSR(sc, TLP_TX_POLL, 1);
4619
4620 return 1; /* did something */
4621 }
4622
4623 /* BSD kernels call this when a hardware interrupt happens. */
4624 static intr_return_t /* context: interrupt */
4625 bsd_interrupt(void *arg)
4626 {
4627 softc_t *sc = arg;
4628
4629 # if DEVICE_POLLING
4630 if (sc->ifp->if_capenable & IFCAP_POLLING)
4631 return IRQ_NONE;
4632 # endif
4633
4634 /* Cut losses early if this is not our interrupt. */
4635 if ((READ_CSR(sc, TLP_STATUS) & TLP_INT_TXRX)==0)
4636 return IRQ_NONE;
4637
4638 /* Process tx and rx pkts. */
4639 lmc_interrupt(sc, sc->rxring.num_descs, 0);
4640
4641 return IRQ_HANDLED;
4642 }
4643
4644 #endif /* BSD */
4645
4646 # if DEVICE_POLLING
4647
4648 /* This procedure services the card without interrupts. */
4649 /* With rxintr_cleanup(), it implements input flow control. */
4650 static void /* context: softirq */
4651 bsd_poll(struct ifnet *ifp, enum poll_cmd cmd, int quota)
4652 {
4653 softc_t *sc = IFP2SC(ifp);
4654
4655 /* Cut losses early if this is not our interrupt. */
4656 if ((READ_CSR(sc, TLP_STATUS) & TLP_INT_TXRX)==0)
4657 return;
4658
4659 /* Process all tx pkts and up to quota rx pkts. */
4660 lmc_interrupt(sc, quota, (cmd==POLL_AND_CHECK_STATUS));
4661 }
4662
4663 # endif /* DEVICE_POLLING */
4664
4665
4666 /* Open a line protocol. */
4667 /* context: kernel (boot) or process (syscall) */
4668 static int
4669 open_proto(softc_t *sc, struct config *config)
4670 {
4671 int error = 0;
4672
4673 if (sc->stack)
4674 error = sc->stack->open(sc, config);
4675 else
4676 error = BSD ? ENOSYS : -ENOSYS;
4677
4678 return error;
4679 }
4680
4681 /* Attach a line protocol stack. */
4682 /* context: kernel (boot) or process (syscall) */
4683 static int
4684 attach_stack(softc_t *sc, struct config *config)
4685 {
4686 int error = 0;
4687 struct stack *stack = NULL;
4688
4689 /* Done if stack is not changing. */
4690 if (sc->config.stack == config->stack)
4691 return 0;
4692
4693 /* Detach the current stack. */
4694 if (sc->stack && ((error = sc->stack->detach(sc))))
4695 return error;
4696
4697 switch (config->stack)
4698 {
4699 case STACK_RAWIP: /* built-in */
4700 stack = &rawip_stack;
4701 break;
4702
4703 #if SPPP
4704 case STACK_SPPP:
4705 stack = &sppp_stack;
4706 break;
4707 #endif
4708
4709 #if P2P
4710 case STACK_P2P:
4711 stack = &p2p_stack;
4712 break;
4713 #endif
4714
4715 #if GEN_HDLC
4716 case STACK_GEN_HDLC:
4717 stack = &gen_hdlc_stack;
4718 break;
4719 #endif
4720
4721 #if SYNC_PPP
4722 case STACK_SYNC_PPP:
4723 stack = &sync_ppp_stack;
4724 break;
4725 #endif
4726
4727
4728 default:
4729 stack = NULL;
4730 break;
4731 }
4732
4733 if (stack)
4734 error = stack->attach(sc, config);
4735 else
4736 error = BSD ? ENOSYS : -ENOSYS;
4737
4738 return error;
4739 }
4740
4741
4742 /*
4743 * This handles IOCTLs from lmcconfig(8).
4744 * Must not run when card watchdogs run.
4745 * Always called with top_lock held.
4746 */
4747 static int /* context: process */
4748 lmc_ioctl(softc_t *sc, u_long cmd, void *data)
4749 {
4750 struct iohdr *iohdr = (struct iohdr *) data;
4751 struct ioctl *ioctl = (struct ioctl *) data;
4752 struct status *status = (struct status *) data;
4753 struct config *config = (struct config *) data;
4754 int error = 0;
4755
4756 /* All structs start with a string and a cookie. */
4757 if (iohdr->cookie != NGM_LMC_COOKIE)
4758 return EINVAL;
4759
4760 switch (cmd)
4761 {
4762 case LMCIOCGSTAT:
4763 {
4764 *status = sc->status;
4765 iohdr->cookie = NGM_LMC_COOKIE;
4766 break;
4767 }
4768 case LMCIOCGCFG:
4769 {
4770 *config = sc->config;
4771 iohdr->cookie = NGM_LMC_COOKIE;
4772 break;
4773 }
4774 case LMCIOCSCFG:
4775 {
4776 if ((error = CHECK_CAP)) break;
4777 if ((error = attach_stack(sc, config)));
4778 else error = open_proto(sc, config);
4779 tulip_loop(sc, config);
4780 sc->card->attach(sc, config);
4781 sc->config.debug = config->debug;
4782 break;
4783 }
4784 case LMCIOCREAD:
4785 {
4786 if (ioctl->cmd == IOCTL_RW_PCI)
4787 {
4788 if (ioctl->address > 252) { error = EFAULT; break; }
4789 ioctl->data = READ_PCI_CFG(sc, ioctl->address);
4790 }
4791 else if (ioctl->cmd == IOCTL_RW_CSR)
4792 {
4793 if (ioctl->address > 15) { error = EFAULT; break; }
4794 ioctl->data = READ_CSR(sc, ioctl->address*TLP_CSR_STRIDE);
4795 }
4796 else if (ioctl->cmd == IOCTL_RW_SROM)
4797 {
4798 if (ioctl->address > 63) { error = EFAULT; break; }
4799 ioctl->data = srom_read(sc, ioctl->address);
4800 }
4801 else if (ioctl->cmd == IOCTL_RW_BIOS)
4802 ioctl->data = bios_read(sc, ioctl->address);
4803 else if (ioctl->cmd == IOCTL_RW_MII)
4804 ioctl->data = mii_read(sc, ioctl->address);
4805 else if (ioctl->cmd == IOCTL_RW_FRAME)
4806 ioctl->data = framer_read(sc, ioctl->address);
4807 else
4808 error = EINVAL;
4809 break;
4810 }
4811 case LMCIOCWRITE:
4812 {
4813 if ((error = CHECK_CAP)) break;
4814 if (ioctl->cmd == IOCTL_RW_PCI)
4815 {
4816 if (ioctl->address > 252) { error = EFAULT; break; }
4817 WRITE_PCI_CFG(sc, ioctl->address, ioctl->data);
4818 }
4819 else if (ioctl->cmd == IOCTL_RW_CSR)
4820 {
4821 if (ioctl->address > 15) { error = EFAULT; break; }
4822 WRITE_CSR(sc, ioctl->address*TLP_CSR_STRIDE, ioctl->data);
4823 }
4824 else if (ioctl->cmd == IOCTL_RW_SROM)
4825 {
4826 if (ioctl->address > 63) { error = EFAULT; break; }
4827 srom_write(sc, ioctl->address, ioctl->data); /* can sleep */
4828 }
4829 else if (ioctl->cmd == IOCTL_RW_BIOS)
4830 {
4831 if (ioctl->address == 0) bios_erase(sc);
4832 bios_write(sc, ioctl->address, ioctl->data); /* can sleep */
4833 }
4834 else if (ioctl->cmd == IOCTL_RW_MII)
4835 mii_write(sc, ioctl->address, ioctl->data);
4836 else if (ioctl->cmd == IOCTL_RW_FRAME)
4837 framer_write(sc, ioctl->address, ioctl->data);
4838 else if (ioctl->cmd == IOCTL_WO_SYNTH)
4839 synth_write(sc, (struct synth *)&ioctl->data);
4840 else if (ioctl->cmd == IOCTL_WO_DAC)
4841 {
4842 dac_write(sc, 0x9002); /* set Vref = 2.048 volts */
4843 dac_write(sc, ioctl->data & 0xFFF);
4844 }
4845 else
4846 error = EINVAL;
4847 break;
4848 }
4849 case LMCIOCTL:
4850 {
4851 if ((error = CHECK_CAP)) break;
4852 if (ioctl->cmd == IOCTL_XILINX_RESET)
4853 {
4854 xilinx_reset(sc);
4855 sc->card->attach(sc, &sc->config);
4856 }
4857 else if (ioctl->cmd == IOCTL_XILINX_ROM)
4858 {
4859 xilinx_load_from_rom(sc);
4860 sc->card->attach(sc, &sc->config);
4861 }
4862 else if (ioctl->cmd == IOCTL_XILINX_FILE)
4863 {
4864 error = xilinx_load_from_file(sc, ioctl->ucode, ioctl->data);
4865 if (error) xilinx_load_from_rom(sc); /* try the rom */
4866 sc->card->attach(sc, &sc->config);
4867 }
4868 else if (ioctl->cmd == IOCTL_RESET_CNTRS)
4869 reset_cntrs(sc);
4870 else
4871 error = sc->card->ioctl(sc, ioctl);
4872 break;
4873 }
4874 default:
4875 error = EINVAL;
4876 break;
4877 }
4878
4879 return error;
4880 }
4881
4882 /* This is the core watchdog procedure.
4883 * ioctl syscalls and card watchdog routines must be interlocked.
4884 * Called by ng_watchdog(), ifnet_watchdog() and netdev_watchdog().
4885 */
4886 static void /* context: softirq */
4887 lmc_watchdog(softc_t *sc)
4888 {
4889 /* Read and restart the Tulip timer. */
4890 u_int32_t tx_speed = READ_CSR(sc, TLP_TIMER);
4891 WRITE_CSR(sc, TLP_TIMER, 0xFFFF);
4892
4893 /* Measure MII clock using a timer in the Tulip chip.
4894 * This timer counts transmitter bits divided by 4096.
4895 * Since this is called once a second the math is easy.
4896 * This is only correct when the link is NOT sending pkts.
4897 * On a fully-loaded link, answer will be HALF actual rate.
4898 * Clock rate during pkt is HALF clk rate between pkts.
4899 * Measuring clock rate really measures link utilization!
4900 */
4901 sc->status.tx_speed = (0xFFFF - (tx_speed & 0xFFFF)) << 12;
4902
4903 /* Call the card-specific watchdog routine. */
4904 if (TOP_TRYLOCK(sc))
4905 {
4906 /* Remember link_state before updating it. */
4907 sc->last_link_state = sc->status.link_state;
4908 /* Update status.link_state. */
4909 sc->card->watchdog(sc);
4910
4911 /* Increment a counter which tells user-land */
4912 /* observers that SNMP state has been updated. */
4913 sc->status.ticks++;
4914
4915 TOP_UNLOCK(sc);
4916 }
4917 else
4918 sc->status.cntrs.lck_watch++;
4919
4920 /* Kernel date/time can take up to 5 seconds to start running. */
4921 if ((sc->status.ticks > 3) && /* h/w should be stable by now */
4922 (sc->status.cntrs.reset_time.tv_sec < 1000))
4923 {
4924 microtime(&sc->status.cntrs.reset_time);
4925 if (sc->status.cntrs.reset_time.tv_sec > 1000)
4926 reset_cntrs(sc);
4927 }
4928
4929 /* Call the stack-specific watchdog routine. */
4930 if (sc->stack)
4931 sc->stack->watchdog(sc);
4932
4933 /* In case an interrupt gets lost, process tx and rx pkts */
4934 lmc_interrupt(sc, sc->rxring.num_descs, 1);
4935 }
4936
4937 /* Administrative status of the driver (UP or DOWN) has changed.
4938 * A card-specific action is taken:
4939 * HSSI: drop TA.
4940 * (T3: send T3 idle ckt signal. )
4941 * SSI: drop RTS, DTR and DCD
4942 * (T1: disable line interface tx; )
4943 */
4944 static void
4945 set_ready(softc_t *sc, int status)
4946 {
4947 struct ioctl ioctl;
4948
4949 ioctl.cmd = IOCTL_SET_STATUS;
4950 ioctl.data = status;
4951
4952 sc->card->ioctl(sc, &ioctl);
4953 }
4954
4955 static void
4956 reset_cntrs(softc_t *sc)
4957 {
4958 memset(&sc->status.cntrs, 0, sizeof(struct cntrs));
4959 microtime(&sc->status.cntrs.reset_time);
4960 }
4961
4962 static void /* context: process, softirq, interrupt! */
4963 lmc_interrupt(void *arg, int quota, int check_status)
4964 {
4965 softc_t *sc = arg;
4966 int activity;
4967
4968 /* Do this FIRST! Otherwise UPs deadlock and MPs spin. */
4969 WRITE_CSR(sc, TLP_STATUS, READ_CSR(sc, TLP_STATUS));
4970
4971 /* If any CPU is inside this critical section, then */
4972 /* other CPUs should go away without doing anything. */
4973 if (BOTTOM_TRYLOCK(sc) == 0)
4974 {
4975 sc->status.cntrs.lck_intr++;
4976 return;
4977 }
4978
4979 /* In Linux, pci_alloc_consistent() means DMA */
4980 /* descriptors do not need explicit syncing? */
4981 #if BSD
4982 {
4983 struct desc_ring *ring = &sc->txring;
4984 DMA_SYNC(sc->txring.map, sc->txring.size_descs,
4985 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4986 ring = &sc->rxring;
4987 DMA_SYNC(sc->rxring.map, sc->rxring.size_descs,
4988 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4989 }
4990 #endif
4991
4992 /* This is the main loop for interrupt processing. */
4993 sc->quota = quota;
4994 do
4995 {
4996 activity = txintr_cleanup(sc);
4997 activity += txintr_setup(sc);
4998 activity += rxintr_cleanup(sc);
4999 activity += rxintr_setup(sc);
5000 } while (activity);
5001
5002 #if BSD
5003 {
5004 struct desc_ring *ring = &sc->txring;
5005 DMA_SYNC(sc->txring.map, sc->txring.size_descs,
5006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5007 ring = &sc->rxring;
5008 DMA_SYNC(sc->rxring.map, sc->rxring.size_descs,
5009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5010 }
5011 #endif
5012
5013 /* As the interrupt is dismissed, check for four unusual events. */
5014 if (check_status) check_intr_status(sc);
5015
5016 BOTTOM_UNLOCK(sc);
5017 }
5018
5019 /* Check for four unusual events:
5020 * 1) fatal PCI bus errors - some are recoverable
5021 * 2) transmitter FIFO underruns - increase fifo threshold
5022 * 3) receiver FIFO overruns - clear potential hangup
5023 * 4) no receive descs or bufs - count missed packets
5024 */
5025 static void
5026 check_intr_status(softc_t *sc)
5027 {
5028 u_int32_t status, cfcs, op_mode;
5029 u_int32_t missed, overruns;
5030
5031 /* 1) A fatal bus error causes a Tulip to stop initiating bus cycles.
5032 * Module unload/load or boot are the only fixes for Parity Errors.
5033 * Master and Target Aborts can be cleared and life may continue.
5034 */
5035 status = READ_CSR(sc, TLP_STATUS);
5036 if (status & TLP_STAT_FATAL_ERROR)
5037 {
5038 u_int32_t fatal = (status & TLP_STAT_FATAL_BITS)>>TLP_STAT_FATAL_SHIFT;
5039 printf("%s: FATAL PCI BUS ERROR: %s%s%s%s\n", NAME_UNIT,
5040 (fatal == 0) ? "PARITY ERROR" : "",
5041 (fatal == 1) ? "MASTER ABORT" : "",
5042 (fatal == 2) ? "TARGET ABORT" : "",
5043 (fatal >= 3) ? "RESERVED (?)" : "");
5044 cfcs = READ_PCI_CFG(sc, TLP_CFCS); /* try to clear it */
5045 cfcs &= ~(TLP_CFCS_MSTR_ABORT | TLP_CFCS_TARG_ABORT);
5046 WRITE_PCI_CFG(sc, TLP_CFCS, cfcs);
5047 }
5048
5049 /* 2) If the transmitter fifo underruns, increase the transmit fifo
5050 * threshold: the number of bytes required to be in the fifo
5051 * before starting the transmitter (cost: increased tx delay).
5052 * The TX_FSM must be stopped to change this parameter.
5053 */
5054 if (status & TLP_STAT_TX_UNDERRUN)
5055 {
5056 op_mode = READ_CSR(sc, TLP_OP_MODE);
5057 /* enable store-and-forward mode if tx_threshold tops out? */
5058 if ((op_mode & TLP_OP_TX_THRESH) < TLP_OP_TX_THRESH)
5059 {
5060 op_mode += 0x4000; /* increment TX_THRESH field; can not overflow */
5061 WRITE_CSR(sc, TLP_OP_MODE, op_mode & ~TLP_OP_TX_RUN);
5062 /* Wait for the TX FSM to stop; it might be processing a pkt. */
5063 while (READ_CSR(sc, TLP_STATUS) & TLP_STAT_TX_FSM); /* XXX HANG */
5064 WRITE_CSR(sc, TLP_OP_MODE, op_mode); /* restart tx */
5065
5066 if (sc->config.debug)
5067 printf("%s: tx fifo underrun; threshold now %d bytes\n",
5068 NAME_UNIT, 128<<((op_mode>>TLP_OP_TR_SHIFT)&3));
5069 sc->status.cntrs.underruns++;
5070 }
5071 }
5072
5073 /* 3) Errata memo from Digital Equipment Corp warns that 21140A
5074 * receivers through rev 2.2 can hang if the fifo overruns.
5075 * Recommended fix: stop and start the RX FSM after an overrun.
5076 */
5077 missed = READ_CSR(sc, TLP_MISSED);
5078 if ((overruns = ((missed & TLP_MISS_OVERRUN)>>TLP_OVERRUN_SHIFT)))
5079 {
5080 if ((READ_PCI_CFG(sc, TLP_CFRV) & 0xFF) <= 0x22)
5081 {
5082 op_mode = READ_CSR(sc, TLP_OP_MODE);
5083 WRITE_CSR(sc, TLP_OP_MODE, op_mode & ~TLP_OP_RX_RUN);
5084 /* Wait for the RX FSM to stop; it might be processing a pkt. */
5085 while (READ_CSR(sc, TLP_STATUS) & TLP_STAT_RX_FSM); /* XXX HANG */
5086 WRITE_CSR(sc, TLP_OP_MODE, op_mode); /* restart rx */
5087 }
5088 if (sc->config.debug)
5089 printf("%s: rx fifo overruns=%d\n", NAME_UNIT, overruns);
5090 sc->status.cntrs.overruns += overruns;
5091 }
5092
5093 /* 4) When the receiver is enabled and a packet arrives, but no DMA
5094 * descriptor is available, the packet is counted as 'missed'.
5095 * The receiver should never miss packets; warn if it happens.
5096 */
5097 if ((missed = (missed & TLP_MISS_MISSED)))
5098 {
5099 if (sc->config.debug)
5100 printf("%s: rx missed %d pkts\n", NAME_UNIT, missed);
5101 sc->status.cntrs.missed += missed;
5102 }
5103 }
5104
5105 /* Initialize the driver. */
5106 /* context: kernel (boot) or process (syscall) */
5107 static int
5108 lmc_attach(softc_t *sc)
5109 {
5110 int error = 0;
5111 struct config config;
5112
5113 /* Attach the Tulip PCI bus interface. */
5114 if ((error = tulip_attach(sc))) return error;
5115
5116 /* Reset the Xilinx Field Programmable Gate Array. */
5117 xilinx_reset(sc); /* side effect: turns on all four LEDs */
5118
5119 /* Attach card-specific stuff. */
5120 sc->card->attach(sc, NULL); /* changes sc->config */
5121
5122 /* Reset the FIFOs between Gate array and Tulip chip. */
5123 mii16_set_bits(sc, MII16_FIFO);
5124 mii16_clr_bits(sc, MII16_FIFO);
5125
5126 #if IFNET
5127 /* Attach the ifnet kernel interface. */
5128 if ((error = ifnet_attach(sc))) return error;
5129 #endif
5130
5131 #if NETDEV
5132 /* Attach the netdevice kernel interface. */
5133 if ((error = netdev_attach(sc))) return error;
5134 #endif
5135
5136 /* Attach a protocol stack and open a line protocol. */
5137 config = sc->config;
5138 config.stack = STACK_RAWIP;
5139 attach_stack(sc, &config);
5140 config.proto = PROTO_IP_HDLC;
5141 open_proto(sc, &config);
5142
5143 /* Print obscure card information. */
5144 if (BOOT_VERBOSE)
5145 {
5146 u_int32_t cfrv = READ_PCI_CFG(sc, TLP_CFRV);
5147 u_int16_t mii3 = mii_read(sc, 3);
5148 u_int16_t srom[3];
5149 u_int8_t *ieee = (u_int8_t *)srom;
5150 int i;
5151
5152 printf("%s", NAME_UNIT);
5153 printf(": PCI rev %d.%d", (cfrv>>4) & 0xF, cfrv & 0xF);
5154 printf(", MII rev %d.%d", (mii3>>4) & 0xF, mii3 & 0xF);
5155 for (i=0; i<3; i++) srom[i] = srom_read(sc, 10+i);
5156 printf(", IEEE addr %02x:%02x:%02x:%02x:%02x:%02x",
5157 ieee[0], ieee[1], ieee[2], ieee[3], ieee[4], ieee[5]);
5158 sc->card->ident(sc);
5159 }
5160
5161 /* BSDs enable card interrupts and appear "ready" here. */
5162 /* Linux does this in netdev_open(). */
5163 #if BSD
5164 set_ready(sc, 1);
5165 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_TXRX);
5166 #endif
5167
5168 return 0;
5169 }
5170
5171 /* context: kernel (boot) or process (syscall) */
5172 static void
5173 lmc_detach(softc_t *sc)
5174 {
5175 /* Disable card interrupts and appear "not ready". */
5176 set_ready(sc, 0);
5177 WRITE_CSR(sc, TLP_INT_ENBL, TLP_INT_DISABLE);
5178
5179 /* Detach the line protocol package. */
5180 if (sc->stack)
5181 sc->stack->detach(sc);
5182
5183 #if IFNET
5184 /* Detach the ifnet kernel interface. */
5185 ifnet_detach(sc);
5186 #endif
5187
5188 #if NETDEV
5189 /* Detach the netdevice kernel interface. */
5190 netdev_detach(sc);
5191 #endif
5192
5193 /* Detach framers, line interfaces, etc. on the card. */
5194 sc->card->detach(sc);
5195
5196 /* Detach the Tulip PCI bus interface. */
5197 tulip_detach(sc);
5198 }
5199
5200 /* Loop back through the TULIP Ethernet chip; (no CRC).
5201 * Data sheet says stop DMA before changing OPMODE register.
5202 * But that's not as simple as it sounds; works anyway.
5203 */
5204 static void
5205 tulip_loop(softc_t *sc, struct config *config)
5206 {
5207 /* Check for enabling loopback thru Tulip chip. */
5208 if ((sc->config.loop_back != CFG_LOOP_TULIP) &&
5209 (config->loop_back == CFG_LOOP_TULIP))
5210 {
5211 u_int32_t op_mode = READ_CSR(sc, TLP_OP_MODE);
5212 op_mode |= TLP_OP_INT_LOOP;
5213 WRITE_CSR(sc, TLP_OP_MODE, op_mode);
5214 config->crc_len = CFG_CRC_0;
5215 }
5216
5217 /* Check for disabling loopback thru Tulip chip. */
5218 if ((sc->config.loop_back == CFG_LOOP_TULIP) &&
5219 (config->loop_back != CFG_LOOP_TULIP))
5220 {
5221 u_int32_t op_mode = READ_CSR(sc, TLP_OP_MODE);
5222 op_mode &= ~TLP_OP_LOOP_MODE;
5223 WRITE_CSR(sc, TLP_OP_MODE, op_mode);
5224 config->crc_len = CFG_CRC_16;
5225 }
5226
5227 sc->config.loop_back = config->loop_back;
5228 }
5229
5230 /* Attach the Tulip PCI bus interface.
5231 * Allocate DMA descriptors and enable DMA.
5232 * Returns 0 on success; error code on failure.
5233 * context: kernel (boot) or process (syscall)
5234 */
5235 static int
5236 tulip_attach(softc_t *sc)
5237 {
5238 int num_rx_descs, error = 0;
5239 u_int32_t bus_pbl, bus_cal, op_tr;
5240 u_int32_t cfdd, cfcs, cflt, csid, cfit;
5241
5242 /* Make sure the COMMAND bits are reasonable. */
5243 cfcs = READ_PCI_CFG(sc, TLP_CFCS);
5244 cfcs &= ~TLP_CFCS_MWI_ENABLE;
5245 cfcs |= TLP_CFCS_BUS_MASTER;
5246 cfcs |= TLP_CFCS_MEM_ENABLE;
5247 cfcs |= TLP_CFCS_IO_ENABLE;
5248 cfcs |= TLP_CFCS_PAR_ERROR;
5249 cfcs |= TLP_CFCS_SYS_ERROR;
5250 WRITE_PCI_CFG(sc, TLP_CFCS, cfcs);
5251
5252 /* Set the LATENCY TIMER to the recommended value, */
5253 /* and make sure the CACHE LINE SIZE is reasonable. */
5254 cfit = READ_PCI_CFG(sc, TLP_CFIT);
5255 cflt = READ_PCI_CFG(sc, TLP_CFLT);
5256 cflt &= ~TLP_CFLT_LATENCY;
5257 cflt |= (cfit & TLP_CFIT_MAX_LAT)>>16;
5258 /* "prgmbl burst length" and "cache alignment" used below. */
5259 switch(cflt & TLP_CFLT_CACHE)
5260 {
5261 case 8: /* 8 bytes per cache line */
5262 { bus_pbl = 32; bus_cal = 1; break; }
5263 case 16:
5264 { bus_pbl = 32; bus_cal = 2; break; }
5265 case 32:
5266 { bus_pbl = 32; bus_cal = 3; break; }
5267 default:
5268 {
5269 bus_pbl = 32; bus_cal = 1;
5270 cflt &= ~TLP_CFLT_CACHE;
5271 cflt |= 8;
5272 break;
5273 }
5274 }
5275 WRITE_PCI_CFG(sc, TLP_CFLT, cflt);
5276
5277 /* Make sure SNOOZE and SLEEP modes are disabled. */
5278 cfdd = READ_PCI_CFG(sc, TLP_CFDD);
5279 cfdd &= ~TLP_CFDD_SLEEP;
5280 cfdd &= ~TLP_CFDD_SNOOZE;
5281 WRITE_PCI_CFG(sc, TLP_CFDD, cfdd);
5282 DELAY(11*1000); /* Tulip wakes up in 10 ms max */
5283
5284 /* Software Reset the Tulip chip; stops DMA and Interrupts. */
5285 /* This does not change the PCI config regs just set above. */
5286 WRITE_CSR(sc, TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */
5287 DELAY(5); /* Tulip is dead for 50 PCI cycles after reset. */
5288
5289 /* Initialize the PCI busmode register. */
5290 /* The PCI bus cycle type "Memory Write and Invalidate" does NOT */
5291 /* work cleanly in any version of the 21140A, so do not enable it! */
5292 WRITE_CSR(sc, TLP_BUS_MODE,
5293 (bus_cal ? TLP_BUS_READ_LINE : 0) |
5294 (bus_cal ? TLP_BUS_READ_MULT : 0) |
5295 (bus_pbl<<TLP_BUS_PBL_SHIFT) |
5296 (bus_cal<<TLP_BUS_CAL_SHIFT) |
5297 ((BYTE_ORDER == BIG_ENDIAN) ? TLP_BUS_DESC_BIGEND : 0) |
5298 ((BYTE_ORDER == BIG_ENDIAN) ? TLP_BUS_DATA_BIGEND : 0) |
5299 TLP_BUS_DSL_VAL |
5300 TLP_BUS_ARB);
5301
5302 /* Pick number of RX descriptors and TX fifo threshold. */
5303 /* tx_threshold in bytes: 0=128, 1=256, 2=512, 3=1024 */
5304 csid = READ_PCI_CFG(sc, TLP_CSID);
5305 switch(csid)
5306 {
5307 case CSID_LMC_HSSI: /* 52 Mb/s */
5308 case CSID_LMC_HSSIc: /* 52 Mb/s */
5309 case CSID_LMC_T3: /* 45 Mb/s */
5310 { num_rx_descs = 48; op_tr = 2; break; }
5311 case CSID_LMC_SSI: /* 10 Mb/s */
5312 { num_rx_descs = 32; op_tr = 1; break; }
5313 case CSID_LMC_T1E1: /* 2 Mb/s */
5314 { num_rx_descs = 16; op_tr = 0; break; }
5315 default:
5316 { num_rx_descs = 16; op_tr = 0; break; }
5317 }
5318
5319 /* Create DMA descriptors and initialize list head registers. */
5320 if ((error = create_ring(sc, &sc->txring, NUM_TX_DESCS))) return error;
5321 WRITE_CSR(sc, TLP_TX_LIST, sc->txring.dma_addr);
5322 if ((error = create_ring(sc, &sc->rxring, num_rx_descs))) return error;
5323 WRITE_CSR(sc, TLP_RX_LIST, sc->rxring.dma_addr);
5324
5325 /* Initialize the operating mode register. */
5326 WRITE_CSR(sc, TLP_OP_MODE, TLP_OP_INIT | (op_tr<<TLP_OP_TR_SHIFT));
5327
5328 /* Read the missed frame register (result ignored) to zero it. */
5329 error = READ_CSR(sc, TLP_MISSED); /* error is used as a bit-dump */
5330
5331 /* Disable rx watchdog and tx jabber features. */
5332 WRITE_CSR(sc, TLP_WDOG, TLP_WDOG_INIT);
5333
5334 return 0;
5335 }
5336
5337 /* Detach the Tulip PCI bus interface. */
5338 /* Disable DMA and free DMA descriptors. */
5339 /* context: kernel (boot) or process (syscall) */
5340 static void
5341 tulip_detach(void *arg)
5342 {
5343 softc_t *sc = arg;
5344
5345 /* Software reset the Tulip chip; stops DMA and Interrupts. */
5346 WRITE_CSR(sc, TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */
5347 DELAY(5); /* Tulip is dead for 50 PCI cycles after reset. */
5348
5349 /* Disconnect from the PCI bus except for config cycles. */
5350 /* Hmmm; Linux syslogs a warning that IO and MEM are disabled. */
5351 WRITE_PCI_CFG(sc, TLP_CFCS, TLP_CFCS_MEM_ENABLE | TLP_CFCS_IO_ENABLE);
5352
5353 /* Free the DMA descriptor rings. */
5354 destroy_ring(sc, &sc->txring);
5355 destroy_ring(sc, &sc->rxring);
5356 }
5357
5358 /* Called during config probing -- softc does not yet exist. */
5359 static void
5360 print_driver_info(void)
5361 {
5362 /* Print driver information once only. */
5363 if (driver_announced++ == 0)
5364 {
5365 printf("LMC driver version %d/%d/%d; options",
5366 VER_YEAR, VER_MONTH, VER_DAY);
5367 if (ALTQ) printf(" ALTQ");
5368 if (NBPFILTER) printf(" BPF");
5369 if (NAPI) printf(" NAPI");
5370 if (DEVICE_POLLING) printf(" POLL");
5371 if (P2P) printf(" P2P");
5372 if (SPPP) printf(" SPPP");
5373 if (GEN_HDLC) printf(" GEN_HDLC");
5374 if (SYNC_PPP) printf(" SYNC_PPP");
5375 if (NETGRAPH) printf(" NETGRAPH");
5376 printf(".\n");
5377 }
5378 }
5379
5380
5381
5382 /* This is the I/O configuration interface for NetBSD. */
5383
5384 /* Looking for a DEC 21140A chip on any Lan Media Corp card. */
5385 /* context: kernel (boot) or process (syscall) */
5386 static int
5387 nbsd_match(struct device *parent, cfdata_t match,
5388 void *aux)
5389 {
5390 struct pci_attach_args *pa = aux;
5391 u_int32_t cfid = pci_conf_read(pa->pa_pc, pa->pa_tag, TLP_CFID);
5392 u_int32_t csid = pci_conf_read(pa->pa_pc, pa->pa_tag, TLP_CSID);
5393
5394 if (cfid != TLP_CFID_TULIP) return 0;
5395 switch (csid)
5396 {
5397 case CSID_LMC_HSSI:
5398 case CSID_LMC_HSSIc:
5399 case CSID_LMC_T3:
5400 case CSID_LMC_SSI:
5401 case CSID_LMC_T1E1:
5402 print_driver_info();
5403 return 100;
5404 default:
5405 return 0;
5406 }
5407 }
5408
5409 /* NetBSD bottom-half initialization. */
5410 /* context: kernel (boot) or process (syscall) */
5411 static void
5412 nbsd_attach(struct device *parent, struct device *self, void *aux)
5413 {
5414 softc_t *sc = (softc_t *)self; /* device is first in softc */
5415 struct pci_attach_args *pa = aux;
5416 const char *intrstr;
5417 bus_addr_t csr_addr;
5418 int error;
5419
5420 /* for READ/WRITE_PCI_CFG() */
5421 sc->pa_pc = pa->pa_pc;
5422 sc->pa_tag = pa->pa_tag;
5423 sc->pa_dmat = pa->pa_dmat;
5424
5425 /* What kind of card are we driving? */
5426 switch (READ_PCI_CFG(sc, TLP_CSID))
5427 {
5428 case CSID_LMC_HSSI:
5429 case CSID_LMC_HSSIc:
5430 sc->dev_desc = HSSI_DESC;
5431 sc->card = &hssi_card;
5432 break;
5433 case CSID_LMC_T3:
5434 sc->dev_desc = T3_DESC;
5435 sc->card = &t3_card;
5436 break;
5437 case CSID_LMC_SSI:
5438 sc->dev_desc = SSI_DESC;
5439 sc->card = &ssi_card;
5440 break;
5441 case CSID_LMC_T1E1:
5442 sc->dev_desc = T1E1_DESC;
5443 sc->card = &t1_card;
5444 break;
5445 default:
5446 return;
5447 }
5448
5449 /* Allocate PCI resources to access the Tulip chip CSRs. */
5450 # if IOREF_CSR
5451 csr_addr = (bus_addr_t)READ_PCI_CFG(sc, TLP_CBIO) & -2;
5452 sc->csr_tag = pa->pa_iot; /* bus_space tag for IO refs */
5453 # else
5454 csr_addr = (bus_addr_t)READ_PCI_CFG(sc, TLP_CBMA);
5455 sc->csr_tag = pa->pa_memt; /* bus_space tag for MEM refs */
5456 # endif
5457 if ((error = bus_space_map(sc->csr_tag, csr_addr,
5458 TLP_CSR_SIZE, 0, &sc->csr_handle)))
5459 {
5460 aprint_error("%s: bus_space_map(): error %d\n", NAME_UNIT, error);
5461 return;
5462 }
5463
5464 /* Allocate PCI interrupt resources. */
5465 if (pci_intr_map(pa, &sc->intr_handle))
5466 {
5467 aprint_error("%s: pci_intr_map() failed\n", NAME_UNIT);
5468 nbsd_detach(self, 0);
5469 return;
5470 }
5471 if ((sc->irq_cookie = pci_intr_establish(pa->pa_pc, sc->intr_handle,
5472 IPL_NET, bsd_interrupt, sc)) == NULL)
5473 {
5474 aprint_error("%s: pci_intr_establish() failed\n", NAME_UNIT);
5475 nbsd_detach(self, 0);
5476 return;
5477 }
5478 intrstr = pci_intr_string(pa->pa_pc, sc->intr_handle);
5479 aprint_normal(" %s: %s\n", intrstr, sc->dev_desc);
5480 aprint_naive(": %s\n", sc->dev_desc);
5481
5482 /* Install a shutdown hook. */
5483 if ((sc->sdh_cookie = shutdownhook_establish(tulip_detach, sc)) == NULL)
5484 {
5485 aprint_error("%s: shutdown_hook_establish() failed\n", NAME_UNIT);
5486 nbsd_detach(self, 0);
5487 return;
5488 }
5489
5490 /* Initialize the top-half and bottom-half locks. */
5491 mutex_init(&sc->top_lock, MUTEX_DEFAULT, IPL_VM);
5492 __cpu_simple_lock_init(&sc->bottom_lock);
5493
5494 /* Initialize the driver. */
5495 if ((error = lmc_attach(sc))) nbsd_detach(self, 0);
5496 }
5497
5498 /* context: kernel (boot) or process (syscall) */
5499 static int
5500 nbsd_detach(struct device *self, int flags)
5501 {
5502 softc_t *sc = (softc_t *)self; /* device is first in softc */
5503
5504 /* Detach from the bus and the kernel. */
5505 lmc_detach(sc);
5506
5507 /* Release resources. */
5508 if (sc->sdh_cookie)
5509 shutdownhook_disestablish(sc->sdh_cookie);
5510 if (sc->irq_cookie)
5511 pci_intr_disestablish(sc->pa_pc, sc->irq_cookie);
5512 if (sc->csr_handle)
5513 bus_space_unmap(sc->csr_tag, sc->csr_handle, TLP_CSR_SIZE);
5514
5515 /* Destroy locks. */
5516 mutex_destroy(&sc->top_lock);
5517
5518 return 0;
5519 }
5520
5521 CFATTACH_DECL(lmc, sizeof(softc_t), /* lmc_ca */
5522 nbsd_match, nbsd_attach, nbsd_detach, NULL);
5523
5524
5525
5526
NetBSD on the FriendlyARM MINI2440