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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_lmc.h
blob6e0ff788cbfd4cdde22735e0d16f50d44e0bd4a2
1 /*-
2 * $NetBSD: if_lmc.h,v 1.16 2009/05/06 09:25:15 cegger Exp $
3 *
4 * Copyright (c) 2002-2006 David Boggs. (boggs@boggs.palo-alto.ca.us)
5 * All rights reserved.
6 *
7 * BSD LICENSE:
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * GNU GENERAL PUBLIC LICENSE:
31 *
32 * This program is free software; you can redistribute it and/or modify it
33 * under the terms of the GNU General Public License as published by the Free
34 * Software Foundation; either version 2 of the License, or (at your option)
35 * any later version.
36 *
37 * This program is distributed in the hope that it will be useful, but WITHOUT
38 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
39 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
40 * more details.
41 *
42 * You should have received a copy of the GNU General Public License along with
43 * this program; if not, write to the Free Software Foundation, Inc., 59
44 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
45 */
46
47 #ifndef IF_LMC_H
48 #define IF_LMC_H
49
50 #define DEVICE_NAME "lmc"
51
52 #define VER_YEAR 2006
53 #define VER_MONTH 4
54 #define VER_DAY 11
55
56 /* netgraph stuff */
57 #define NG_LMC_NODE_TYPE "if_"DEVICE_NAME
58 #define NGM_LMC_COOKIE 1144752198 /* date -u +'%s' */
59
60 /* Tulip PCI configuration registers */
61 #define TLP_CFID 0x00 /* 0: CFg ID register */
62 #define TLP_CFCS 0x04 /* 1: CFg Command/Status */
63 #define TLP_CFRV 0x08 /* 2: CFg ReVision */
64 #define TLP_CFLT 0x0C /* 3: CFg Latency Timer */
65 #define TLP_CBIO 0x10 /* 4: Cfg Base IO address */
66 #define TLP_CBMA 0x14 /* 5: Cfg Base Mem Addr */
67 #define TLP_CSID 0x2C /* 11: Cfg Subsys ID reg */
68 #define TLP_CFIT 0x3C /* 15: CFg InTerrupt */
69 #define TLP_CFDD 0x40 /* 16: CFg Driver Data */
70
71 #define TLP_CFID_TULIP 0x00091011 /* DEC 21140A Ethernet chip */
72
73 #define TLP_CFCS_MSTR_ABORT 0x20000000
74 #define TLP_CFCS_TARG_ABORT 0x10000000
75 #define TLP_CFCS_SYS_ERROR 0x00000100
76 #define TLP_CFCS_PAR_ERROR 0x00000040
77 #define TLP_CFCS_MWI_ENABLE 0x00000010
78 #define TLP_CFCS_BUS_MASTER 0x00000004
79 #define TLP_CFCS_MEM_ENABLE 0x00000002
80 #define TLP_CFCS_IO_ENABLE 0x00000001
81
82 #define TLP_CFLT_LATENCY 0x0000FF00
83 #define TLP_CFLT_CACHE 0x000000FF
84
85 #define CSID_LMC_HSSI 0x00031376 /* LMC 5200 HSSI card */
86 #define CSID_LMC_T3 0x00041376 /* LMC 5245 T3 card */
87 #define CSID_LMC_SSI 0x00051376 /* LMC 1000 SSI card */
88 #define CSID_LMC_T1E1 0x00061376 /* LMC 1200 T1E1 card */
89 #define CSID_LMC_HSSIc 0x00071376 /* LMC 5200 HSSI cPCI */
90 #define CSID_LMC_SDSL 0x00081376 /* LMC 1168 SDSL card */
91
92 #define TLP_CFIT_MAX_LAT 0xFF000000
93
94 #define TLP_CFDD_SLEEP 0x80000000
95 #define TLP_CFDD_SNOOZE 0x40000000
96
97 /* Tulip Control and Status Registers */
98 #define TLP_CSR_STRIDE 8 /* 64 bits */
99 #define TLP_BUS_MODE 0 * TLP_CSR_STRIDE
100 #define TLP_TX_POLL 1 * TLP_CSR_STRIDE
101 #define TLP_RX_POLL 2 * TLP_CSR_STRIDE
102 #define TLP_RX_LIST 3 * TLP_CSR_STRIDE
103 #define TLP_TX_LIST 4 * TLP_CSR_STRIDE
104 #define TLP_STATUS 5 * TLP_CSR_STRIDE
105 #define TLP_OP_MODE 6 * TLP_CSR_STRIDE
106 #define TLP_INT_ENBL 7 * TLP_CSR_STRIDE
107 #define TLP_MISSED 8 * TLP_CSR_STRIDE
108 #define TLP_SROM_MII 9 * TLP_CSR_STRIDE
109 #define TLP_BIOS_ROM 10 * TLP_CSR_STRIDE
110 #define TLP_TIMER 11 * TLP_CSR_STRIDE
111 #define TLP_GPIO 12 * TLP_CSR_STRIDE
112 #define TLP_CSR13 13 * TLP_CSR_STRIDE
113 #define TLP_CSR14 14 * TLP_CSR_STRIDE
114 #define TLP_WDOG 15 * TLP_CSR_STRIDE
115 #define TLP_CSR_SIZE 128 /* IO bus space size */
116
117 /* CSR 0 - PCI Bus Mode Register */
118 #define TLP_BUS_WRITE_INVAL 0x01000000 /* DONT USE! */
119 #define TLP_BUS_READ_LINE 0x00800000
120 #define TLP_BUS_READ_MULT 0x00200000
121 #define TLP_BUS_DESC_BIGEND 0x00100000
122 #define TLP_BUS_TAP 0x000E0000
123 #define TLP_BUS_CAL 0x0000C000
124 #define TLP_BUS_PBL 0x00003F00
125 #define TLP_BUS_DATA_BIGEND 0x00000080
126 #define TLP_BUS_DSL 0x0000007C
127 #define TLP_BUS_ARB 0x00000002
128 #define TLP_BUS_RESET 0x00000001
129 #define TLP_BUS_CAL_SHIFT 14
130 #define TLP_BUS_PBL_SHIFT 8
131
132 /* CSR 5 - Status Register */
133 #define TLP_STAT_FATAL_BITS 0x03800000
134 #define TLP_STAT_TX_FSM 0x00700000
135 #define TLP_STAT_RX_FSM 0x000E0000
136 #define TLP_STAT_FATAL_ERROR 0x00002000
137 #define TLP_STAT_TX_UNDERRUN 0x00000020
138 #define TLP_STAT_FATAL_SHIFT 23
139
140 /* CSR 6 - Operating Mode Register */
141 #define TLP_OP_RECEIVE_ALL 0x40000000
142 #define TLP_OP_MUST_BE_ONE 0x02000000
143 #define TLP_OP_NO_HEART_BEAT 0x00080000
144 #define TLP_OP_PORT_SELECT 0x00040000
145 #define TLP_OP_TX_THRESH 0x0000C000
146 #define TLP_OP_TX_RUN 0x00002000
147 #define TLP_OP_LOOP_MODE 0x00000C00
148 #define TLP_OP_EXT_LOOP 0x00000800
149 #define TLP_OP_INT_LOOP 0x00000400
150 #define TLP_OP_FULL_DUPLEX 0x00000200
151 #define TLP_OP_PROMISCUOUS 0x00000040
152 #define TLP_OP_PASS_BAD_PKT 0x00000008
153 #define TLP_OP_RX_RUN 0x00000002
154 #define TLP_OP_TR_SHIFT 14
155 #define TLP_OP_INIT (TLP_OP_PORT_SELECT | \
156 TLP_OP_FULL_DUPLEX | \
157 TLP_OP_MUST_BE_ONE | \
158 TLP_OP_NO_HEART_BEAT | \
159 TLP_OP_RECEIVE_ALL | \
160 TLP_OP_PROMISCUOUS | \
161 TLP_OP_PASS_BAD_PKT | \
162 TLP_OP_RX_RUN | \
163 TLP_OP_TX_RUN)
164
165 /* CSR 7 - Interrupt Enable Register */
166 #define TLP_INT_NORMAL_INTR 0x00010000
167 #define TLP_INT_ABNRML_INTR 0x00008000
168 #define TLP_INT_FATAL_ERROR 0x00002000
169 #define TLP_INT_RX_NO_BUFS 0x00000080
170 #define TLP_INT_RX_INTR 0x00000040
171 #define TLP_INT_TX_UNDERRUN 0x00000020
172 #define TLP_INT_TX_INTR 0x00000001
173 #define TLP_INT_DISABLE 0
174 #define TLP_INT_TX (TLP_INT_NORMAL_INTR | \
175 TLP_INT_ABNRML_INTR | \
176 TLP_INT_FATAL_ERROR | \
177 TLP_INT_TX_UNDERRUN | \
178 TLP_INT_TX_INTR)
179 #define TLP_INT_RX (TLP_INT_NORMAL_INTR | \
180 TLP_INT_ABNRML_INTR | \
181 TLP_INT_FATAL_ERROR | \
182 TLP_INT_RX_NO_BUFS | \
183 TLP_INT_RX_INTR)
184 #define TLP_INT_TXRX (TLP_INT_TX | TLP_INT_RX)
185
186 /* CSR 8 - RX Missed Frames & Overrun Register */
187 #define TLP_MISS_OCO 0x10000000
188 #define TLP_MISS_OVERRUN 0x0FFE0000
189 #define TLP_MISS_MFO 0x00010000
190 #define TLP_MISS_MISSED 0x0000FFFF
191 #define TLP_OVERRUN_SHIFT 17
192
193 /* CSR 9 - SROM & MII & Boot ROM Register */
194 #define TLP_MII_MDIN 0x00080000
195 #define TLP_MII_MDOE 0x00040000
196 #define TLP_MII_MDOUT 0x00020000
197 #define TLP_MII_MDC 0x00010000
198
199 #define TLP_BIOS_RD 0x00004000
200 #define TLP_BIOS_WR 0x00002000
201 #define TLP_BIOS_SEL 0x00001000
202
203 #define TLP_SROM_RD 0x00004000
204 #define TLP_SROM_SEL 0x00000800
205 #define TLP_SROM_DOUT 0x00000008
206 #define TLP_SROM_DIN 0x00000004
207 #define TLP_SROM_CLK 0x00000002
208 #define TLP_SROM_CS 0x00000001
209
210 /* CSR 12 - General Purpose IO register */
211 #define TLP_GPIO_DIR 0x00000100
212
213 /* CSR 15 - Watchdog Timer Register */
214 #define TLP_WDOG_RX_OFF 0x00000010
215 #define TLP_WDOG_TX_OFF 0x00000001
216 #define TLP_WDOG_INIT (TLP_WDOG_TX_OFF | \
217 TLP_WDOG_RX_OFF)
218
219 /* GPIO bits common to all cards */
220 #define GPIO_INIT 0x01 /* from Xilinx */
221 #define GPIO_RESET 0x02 /* to Xilinx */
222 /* bits 2 and 3 vary with card type -- see below */
223 #define GPIO_MODE 0x10 /* to Xilinx */
224 #define GPIO_DP 0x20 /* to/from Xilinx */
225 #define GPIO_DATA 0x40 /* serial data */
226 #define GPIO_CLK 0x80 /* serial clock */
227
228 /* HSSI GPIO bits */
229 #define GPIO_HSSI_ST 0x04 /* send timing sense (deprecated) */
230 #define GPIO_HSSI_TXCLK 0x08 /* clock source */
231
232 /* HSSIc GPIO bits */
233 #define GPIO_HSSI_SYNTH 0x04 /* Synth osc chip select */
234 #define GPIO_HSSI_DCE 0x08 /* provide clock on TXCLOCK output */
235
236 /* T3 GPIO bits */
237 #define GPIO_T3_DAC 0x04 /* DAC chip select */
238 #define GPIO_T3_INTEN 0x08 /* Framer Interupt enable */
239
240 /* SSI GPIO bits */
241 #define GPIO_SSI_SYNTH 0x04 /* Synth osc chip select */
242 #define GPIO_SSI_DCE 0x08 /* provide clock on TXCLOCK output */
243
244 /* T1E1 GPIO bits */
245 #define GPIO_T1_INTEN 0x08 /* Framer Interupt enable */
246
247 /* MII register 16 bits common to all cards */
248 /* NB: LEDs for HSSI & SSI are in DIFFERENT bits than for T1E1 & T3; oops */
249 /* NB: CRC32 for HSSI & SSI is in DIFFERENT bit than for T1E1 & T3; oops */
250 #define MII16_LED_ALL 0x0780 /* RW: LED bit mask */
251 #define MII16_FIFO 0x0800 /* RW: 1=reset, 0=not reset */
252
253 /* MII register 16 bits for HSSI */
254 #define MII16_HSSI_TA 0x0001 /* RW: host ready; host->modem */
255 #define MII16_HSSI_CA 0x0002 /* RO: modem ready; modem->host */
256 #define MII16_HSSI_LA 0x0004 /* RW: loopback A; host->modem */
257 #define MII16_HSSI_LB 0x0008 /* RW: loopback B; host->modem */
258 #define MII16_HSSI_LC 0x0010 /* RO: loopback C; modem->host */
259 #define MII16_HSSI_TM 0x0020 /* RO: test mode; modem->host */
260 #define MII16_HSSI_CRC32 0x0040 /* RW: CRC length 16/32 */
261 #define MII16_HSSI_LED_LL 0x0080 /* RW: lower left - green */
262 #define MII16_HSSI_LED_LR 0x0100 /* RW: lower right - green */
263 #define MII16_HSSI_LED_UL 0x0200 /* RW: upper left - green */
264 #define MII16_HSSI_LED_UR 0x0400 /* RW: upper right - red */
265 #define MII16_HSSI_FIFO 0x0800 /* RW: reset fifos */
266 #define MII16_HSSI_FORCECA 0x1000 /* RW: [cPCI] force CA on */
267 #define MII16_HSSI_CLKMUX 0x6000 /* RW: [cPCI] TX clock selection */
268 #define MII16_HSSI_LOOP 0x8000 /* RW: [cPCI] LOOP TX into RX */
269 #define MII16_HSSI_MODEM 0x003F /* TA+CA+LA+LB+LC+TM */
270
271 /* MII register 16 bits for DS3 */
272 #define MII16_DS3_ZERO 0x0001 /* RW: short/long cables */
273 #define MII16_DS3_TRLBK 0x0002 /* RW: loop towards host */
274 #define MII16_DS3_LNLBK 0x0004 /* RW: loop towards net */
275 #define MII16_DS3_RAIS 0x0008 /* RO: LIU receive AIS (depr) */
276 #define MII16_DS3_TAIS 0x0010 /* RW: LIU transmit AIS (depr) */
277 #define MII16_DS3_BIST 0x0020 /* RO: LIU QRSS patt match (depr) */
278 #define MII16_DS3_DLOS 0x0040 /* RO: LIU Digital LOS (depr) */
279 #define MII16_DS3_LED_BLU 0x0080 /* RW: lower right - blue */
280 #define MII16_DS3_LED_YEL 0x0100 /* RW: lower left - yellow */
281 #define MII16_DS3_LED_RED 0x0200 /* RW: upper right - red */
282 #define MII16_DS3_LED_GRN 0x0400 /* RW: upper left - green */
283 #define MII16_DS3_FIFO 0x0800 /* RW: reset fifos */
284 #define MII16_DS3_CRC32 0x1000 /* RW: CRC length 16/32 */
285 #define MII16_DS3_SCRAM 0x2000 /* RW: payload scrambler */
286 #define MII16_DS3_POLY 0x4000 /* RW: 1=Larse, 0=DigLink|Kentrox */
287 #define MII16_DS3_FRAME 0x8000 /* RW: 1=stop txframe pulses */
288
289 /* MII register 16 bits for SSI */
290 #define MII16_SSI_DTR 0x0001 /* RW: DTR host->modem */
291 #define MII16_SSI_DSR 0x0002 /* RO: DSR modem->host */
292 #define MII16_SSI_RTS 0x0004 /* RW: RTS host->modem */
293 #define MII16_SSI_CTS 0x0008 /* RO: CTS modem->host */
294 #define MII16_SSI_DCD 0x0010 /* RW: DCD modem<->host */
295 #define MII16_SSI_RI 0x0020 /* RO: RI modem->host */
296 #define MII16_SSI_CRC32 0x0040 /* RW: CRC length 16/32 */
297 #define MII16_SSI_LED_LL 0x0080 /* RW: lower left - green */
298 #define MII16_SSI_LED_LR 0x0100 /* RW: lower right - green */
299 #define MII16_SSI_LED_UL 0x0200 /* RW: upper left - green */
300 #define MII16_SSI_LED_UR 0x0400 /* RW: upper right - red */
301 #define MII16_SSI_FIFO 0x0800 /* RW: reset fifos */
302 #define MII16_SSI_LL 0x1000 /* RW: LL: host->modem */
303 #define MII16_SSI_RL 0x2000 /* RW: RL: host->modem */
304 #define MII16_SSI_TM 0x4000 /* RO: TM: modem->host */
305 #define MII16_SSI_LOOP 0x8000 /* RW: Loop at ext conn */
306 #define MII16_SSI_MODEM 0x703F /* DTR+DSR+RTS+CTS+DCD+RI+LL+RL+TM */
307
308 /* Mii register 17 has the SSI cable bits */
309 #define MII17_SSI_CABLE_SHIFT 3 /* shift to get cable type */
310 #define MII17_SSI_CABLE_MASK 0x0038 /* RO: mask to get cable type */
311 #define MII17_SSI_PRESCALE 0x0040 /* RW: divide by: 0=16; 1=512 */
312 #define MII17_SSI_ITF 0x0100 /* RW: fill with: 0=flags; 1=ones */
313 #define MII17_SSI_NRZI 0x0400 /* RW: coding: NRZ= 0; NRZI=1 */
314
315 /* MII register 16 bits for T1/E1 */
316 #define MII16_T1_UNUSED1 0x0001
317 #define MII16_T1_INVERT 0x0002 /* RW: invert data (for SF/AMI) */
318 #define MII16_T1_XOE 0x0004 /* RW: TX Output Enable; 0=disable */
319 #define MII16_T1_RST 0x0008 /* RW: Bt8370 chip reset */
320 #define MII16_T1_Z 0x0010 /* RW: output impedance T1=1 E1=0 */
321 #define MII16_T1_INTR 0x0020 /* RO: interrupt from Bt8370 */
322 #define MII16_T1_ONESEC 0x0040 /* RO: one second square wave */
323 #define MII16_T1_LED_BLU 0x0080 /* RW: lower right - blue */
324 #define MII16_T1_LED_YEL 0x0100 /* RW: lower left - yellow */
325 #define MII16_T1_LED_RED 0x0200 /* RW: upper right - red */
326 #define MII16_T1_LED_GRN 0x0400 /* RW: upper left - green */
327 #define MII16_T1_FIFO 0x0800 /* RW: reset fifos */
328 #define MII16_T1_CRC32 0x1000 /* RW: CRC length 16/32 */
329 #define MII16_T1_UNUSED2 0xE000
330
331 /* T3 framer: RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */
332 #define T3CSR_STAT0 0x00 /* RO: real-time status */
333 #define T3CSR_CTL1 0x01 /* RW: global control bits */
334 #define T3CSR_FEBE 0x02 /* RC: Far End Block Error Counter */
335 #define T3CSR_CERR 0x03 /* RC: C-bit Parity Error Counter */
336 #define T3CSR_PERR 0x04 /* RC: P-bit Parity Error Counter */
337 #define T3CSR_TX_FEAC 0x05 /* RW: Far End Alarm & Control */
338 #define T3CSR_RX_FEAC 0x06 /* RO: Far End Alarm & Control */
339 #define T3CSR_STAT7 0x07 /* RL: latched real-time status */
340 #define T3CSR_CTL8 0x08 /* RW: extended global ctl bits */
341 #define T3CSR_STAT9 0x09 /* RL: extended status bits */
342 #define T3CSR_FERR 0x0A /* RC: F-bit Error Counter */
343 #define T3CSR_MERR 0x0B /* RC: M-bit Error Counter */
344 #define T3CSR_CTL12 0x0C /* RW: more extended ctl bits */
345 #define T3CSR_DBL_FEAC 0x0D /* RW: TX double FEAC */
346 #define T3CSR_CTL14 0x0E /* RW: even more extended ctl bits */
347 #define T3CSR_FEAC_STK 0x0F /* RO: RX FEAC stack */
348 #define T3CSR_STAT16 0x10 /* RL: extended latched status */
349 #define T3CSR_INTEN 0x11 /* RW: interrupt enable */
350 #define T3CSR_CVLO 0x12 /* RC: coding violation cntr LSB */
351 #define T3CSR_CVHI 0x13 /* RC: coding violation cntr MSB */
352 #define T3CSR_CTL20 0x14 /* RW: yet more extended ctl bits */
353
354 #define CTL1_XTX 0x01 /* Transmit X-bit value */
355 #define CTL1_3LOOP 0x02 /* framer loop back */
356 #define CTL1_SER 0x04 /* SERial interface selected */
357 #define CTL1_M13MODE 0x08 /* M13 frame format */
358 #define CTL1_TXIDL 0x10 /* Transmit Idle signal */
359 #define CTL1_ENAIS 0x20 /* Enable AIS upon LOS */
360 #define CTL1_TXAIS 0x40 /* Transmit Alarm Indication Sig */
361 #define CTL1_NOFEBE 0x80 /* No Far End Block Errors */
362
363 #define CTL5_EMODE 0x80 /* rev B Extended features enabled */
364 #define CTL5_START 0x40 /* transmit the FEAC msg now */
365
366 #define CTL8_FBEC 0x80 /* F-Bit Error Count control */
367 #define CTL8_TBLU 0x20 /* Transmit Blue signal */
368 #define CTL8_OUT_DIS 0x10 /* Output Disable */
369
370 #define STAT9_SEF 0x80 /* Severely Errored Frame */
371 #define STAT9_RBLU 0x20 /* Receive Blue signal */
372
373 #define CTL12_RTPLLEN 0x80 /* Rx-to-Tx Payload Lpbk Lock ENbl */
374 #define CTL12_RTPLOOP 0x40 /* Rx-to-Tx Payload Loopback */
375 #define CTL12_DLCB1 0x08 /* Data Link C-Bits forced to 1 */
376 #define CTL12_C21 0x04 /* C2 forced to 1 */
377 #define CTL12_MCB1 0x02 /* Most C-Bits forced to 1 */
378
379 #define CTL13_DFEXEC 0x40 /* Execute Double FEAC */
380
381 #define CTL14_FEAC10 0x80 /* Transmit FEAC word 10 times */
382 #define CTL14_RGCEN 0x20 /* Receive Gapped Clock Out Enbl */
383 #define CTL14_TGCEN 0x10 /* Timing Gen Gapped Clk Out Enbl */
384
385 #define FEAC_STK_MORE 0x80 /* FEAC stack has more FEACs */
386 #define FEAC_STK_VALID 0x40 /* FEAC stack is valid */
387 #define FEAC_STK_FEAC 0x3F /* FEAC stack FEAC data */
388
389 #define STAT16_XERR 0x01 /* X-bit Error */
390 #define STAT16_SEF 0x02 /* Severely Errored Frame */
391 #define STAT16_RTLOC 0x04 /* Rx/Tx Loss Of Clock */
392 #define STAT16_FEAC 0x08 /* new FEAC msg */
393 #define STAT16_RIDL 0x10 /* channel IDLe signal */
394 #define STAT16_RAIS 0x20 /* Alarm Indication Signal */
395 #define STAT16_ROOF 0x40 /* Out Of Frame sync */
396 #define STAT16_RLOS 0x80 /* Loss Of Signal */
397
398 #define CTL20_CVEN 0x01 /* Coding Violation Counter Enbl */
399
400 /* T1.107 Bit Oriented C-Bit Parity Far End Alarm Control and Status codes */
401 #define T3BOP_OOF 0x00 /* Yellow alarm status */
402 #define T3BOP_LINE_UP 0x07 /* line loopback activate */
403 #define T3BOP_LINE_DOWN 0x1C /* line loopback deactivate */
404 #define T3BOP_LOOP_DS3 0x1B /* loopback full DS3 */
405 #define T3BOP_IDLE 0x1A /* IDLE alarm status */
406 #define T3BOP_AIS 0x16 /* AIS alarm status */
407 #define T3BOP_LOS 0x0E /* LOS alarm status */
408
409 /* T1E1 regs; RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */
410 #define Bt8370_DID 0x000 /* RO: Device ID */
411 #define Bt8370_CR0 0x001 /* RW; Primary Control Register */
412 #define Bt8370_JAT_CR 0x002 /* RW: Jitter Attenuator CR */
413 #define Bt8370_IRR 0x003 /* RO: Interrupt Request Reg */
414 #define Bt8370_ISR7 0x004 /* RC: Alarm 1 Interrupt Status */
415 #define Bt8370_ISR6 0x005 /* RC: Alarm 2 Interrupt Status */
416 #define Bt8370_ISR5 0x006 /* RC: Error Interrupt Status */
417 #define Bt8370_ISR4 0x007 /* RC; Cntr Ovfl Interrupt Status */
418 #define Bt8370_ISR3 0x008 /* RC: Timer Interrupt Status */
419 #define Bt8370_ISR2 0x009 /* RC: Data Link 1 Int Status */
420 #define Bt8370_ISR1 0x00A /* RC: Data Link 2 Int Status */
421 #define Bt8370_ISR0 0x00B /* RC: Pattrn Interrupt Status */
422 #define Bt8370_IER7 0x00C /* RW: Alarm 1 Interrupt Enable */
423 #define Bt8370_IER6 0x00D /* RW: Alarm 2 Interrupt Enable */
424 #define Bt8370_IER5 0x00E /* RW: Error Interrupt Enable */
425 #define Bt8370_IER4 0x00F /* RW: Cntr Ovfl Interrupt Enable */
426
427 #define Bt8370_IER3 0x010 /* RW: Timer Interrupt Enable */
428 #define Bt8370_IER2 0x011 /* RW: Data Link 1 Int Enable */
429 #define Bt8370_IER1 0x012 /* RW: Data Link 2 Int Enable */
430 #define Bt8370_IER0 0x013 /* RW: Pattern Interrupt Enable */
431 #define Bt8370_LOOP 0x014 /* RW: Loopback Config Reg */
432 #define Bt8370_DL3_TS 0x015 /* RW: External Data Link Channel */
433 #define Bt8370_DL3_BIT 0x016 /* RW: External Data Link Bit */
434 #define Bt8370_FSTAT 0x017 /* RO: Offline Framer Status */
435 #define Bt8370_PIO 0x018 /* RW: Programmable Input/Output */
436 #define Bt8370_POE 0x019 /* RW: Programmable Output Enable */
437 #define Bt8370_CMUX 0x01A /* RW: Clock Input Mux */
438 #define Bt8370_TMUX 0x01B /* RW: Test Mux Config */
439 #define Bt8370_TEST 0x01C /* RW: Test Config */
440
441 #define Bt8370_LIU_CR 0x020 /* RW: Line Intf Unit Config Reg */
442 #define Bt8370_RSTAT 0x021 /* RO; Receive LIU Status */
443 #define Bt8370_RLIU_CR 0x022 /* RW: Receive LIU Config */
444 #define Bt8370_LPF 0x023 /* RW: RPLL Low Pass Filter */
445 #define Bt8370_VGA_MAX 0x024 /* RW: Variable Gain Amplifier Max */
446 #define Bt8370_EQ_DAT 0x025 /* RW: Equalizer Coeff Data Reg */
447 #define Bt8370_EQ_PTR 0x026 /* RW: Equzlizer Coeff Table Ptr */
448 #define Bt8370_DSLICE 0x027 /* RW: Data Slicer Threshold */
449 #define Bt8370_EQ_OUT 0x028 /* RW: Equalizer Output Levels */
450 #define Bt8370_VGA 0x029 /* RO: Variable Gain Ampl Status */
451 #define Bt8370_PRE_EQ 0x02A /* RW: Pre-Equalizer */
452
453 #define Bt8370_COEFF0 0x030 /* RO: LMS Adj Eq Coeff Status */
454 #define Bt8370_GAIN0 0x038 /* RW: Equalizer Gain Thresh */
455 #define Bt8370_GAIN1 0x039 /* RW: Equalizer Gain Thresh */
456 #define Bt8370_GAIN2 0x03A /* RW: Equalizer Gain Thresh */
457 #define Bt8370_GAIN3 0x03B /* RW: Equalizer Gain Thresh */
458 #define Bt8370_GAIN4 0x03C /* RW: Equalizer Gain Thresh */
459
460 #define Bt8370_RCR0 0x040 /* RW: Rx Configuration */
461 #define Bt8370_RPATT 0x041 /* RW: Rx Test Pattern Config */
462 #define Bt8370_RLB 0x042 /* RW: Rx Loopback Code Detr Conf */
463 #define Bt8370_LBA 0x043 /* RW: Loopback Activate Code Patt */
464 #define Bt8370_LBD 0x044 /* RW: Loopback Deact Code Patt */
465 #define Bt8370_RALM 0x045 /* RW: Rx Alarm Signal Config */
466 #define Bt8370_LATCH 0x046 /* RW: Alarm/Err/Cntr Latch Config */
467 #define Bt8370_ALM1 0x047 /* RO: Alarm 1 Status */
468 #define Bt8370_ALM2 0x048 /* RO: Alarm 2 Status */
469 #define Bt8370_ALM3 0x049 /* RO: Alarm 3 Status */
470
471 #define Bt8370_FERR_LO 0x050 /* RC: Framing Bit Error Cntr LSB */
472 #define Bt8370_FERR_HI 0x051 /* RC: Framing Bit Error Cntr MSB */
473 #define Bt8370_CRC_LO 0x052 /* RC: CRC Error Counter LSB */
474 #define Bt8370_CRC_HI 0x053 /* RC: CRC Error Counter MSB */
475 #define Bt8370_LCV_LO 0x054 /* RC: Line Code Viol Counter LSB */
476 #define Bt8370_LCV_HI 0x055 /* RC: Line Code Viol Counter MSB */
477 #define Bt8370_FEBE_LO 0x056 /* RC: Far End Block Err Cntr LSB */
478 #define Bt8370_FEBE_HI 0x057 /* RC: Far End Block Err Cntr MSB */
479 #define Bt8370_BERR_LO 0x058 /* RC: PRBS Bit Error Counter LSB */
480 #define Bt8370_BERR_HI 0x059 /* RC: PRBS Bit Error Counter MSB */
481 #define Bt8370_AERR 0x05A /* RC: SEF/LOF/COFA counter */
482 #define Bt8370_RSA4 0x05B /* RO: Rx Sa4 Byte Buffer */
483 #define Bt8370_RSA5 0x05C /* RO: Rx Sa5 Byte Buffer */
484 #define Bt8370_RSA6 0x05D /* RO: Rx Sa6 Byte Buffer */
485 #define Bt8370_RSA7 0x05E /* RO: Rx Sa7 Byte Buffer */
486 #define Bt8370_RSA8 0x05F /* RO: Rx Sa8 Byte Buffer */
487
488 #define Bt8370_SHAPE0 0x060 /* RW: Tx Pulse Shape Config */
489 #define Bt8370_TLIU_CR 0x068 /* RW: Tx LIU Config Reg */
490
491 #define Bt8370_TCR0 0x070 /* RW: Tx Framer Config */
492 #define Bt8370_TCR1 0x071 /* RW: Txter Configuration */
493 #define Bt8370_TFRM 0x072 /* RW: Tx Frame Format */
494 #define Bt8370_TERROR 0x073 /* RW: Tx Error Insert */
495 #define Bt8370_TMAN 0x074 /* RW: Tx Manual Sa/FEBE Config */
496 #define Bt8370_TALM 0x075 /* RW: Tx Alarm Signal Config */
497 #define Bt8370_TPATT 0x076 /* RW: Tx Test Pattern Config */
498 #define Bt8370_TLB 0x077 /* RW: Tx Inband Loopback Config */
499 #define Bt8370_LBP 0x078 /* RW: Tx Inband Loopback Patt */
500 #define Bt8370_TSA4 0x07B /* RW: Tx Sa4 Byte Buffer */
501 #define Bt8370_TSA5 0x07C /* RW: Tx Sa5 Byte Buffer */
502 #define Bt8370_TSA6 0x07D /* RW: Tx Sa6 Byte Buffer */
503 #define Bt8370_TSA7 0x07E /* RW: Tx Sa7 Byte Buffer */
504 #define Bt8370_TSA8 0x07F /* RW: Tx Sa8 Byte Buffer */
505
506 #define Bt8370_CLAD_CR 0x090 /* RW: Clock Rate Adapter Config */
507 #define Bt8370_CSEL 0x091 /* RW: CLAD Frequency Select */
508 #define Bt8370_CPHASE 0x092 /* RW: CLAD Phase Det Scale Factor */
509 #define Bt8370_CTEST 0x093 /* RW: CLAD Test */
510
511 #define Bt8370_BOP 0x0A0 /* RW: Bit Oriented Protocol Xcvr */
512 #define Bt8370_TBOP 0x0A1 /* RW: Tx BOP Codeword */
513 #define Bt8370_RBOP 0x0A2 /* RO; Rx BOP Codeword */
514 #define Bt8370_BOP_STAT 0x0A3 /* RO: BOP Status */
515 #define Bt8370_DL1_TS 0x0A4 /* RW: DL1 Time Slot Enable */
516 #define Bt8370_DL1_BIT 0x0A5 /* RW: DL1 Bit Enable */
517 #define Bt8370_DL1_CTL 0x0A6 /* RW: DL1 Control */
518 #define Bt8370_RDL1_FFC 0x0A7 /* RW: RDL1 FIFO Fill Control */
519 #define Bt8370_RDL1 0x0A8 /* RO: RDL1 FIFO */
520 #define Bt8370_RDL1_STAT 0x0A9 /* RO: RDL1 Status */
521 #define Bt8370_PRM 0x0AA /* RW: Performance Report Message */
522 #define Bt8370_TDL1_FEC 0x0AB /* RW: TDL1 FIFO Empty Control */
523 #define Bt8370_TDL1_EOM 0x0AC /* WO: TDL1 End Of Message Control */
524 #define Bt8370_TDL1 0x0AD /* RW: TDL1 FIFO */
525 #define Bt8370_TDL1_STAT 0x0AE /* RO: TDL1 Status */
526 #define Bt8370_DL2_TS 0x0AF /* RW: DL2 Time Slot Enable */
527
528 #define Bt8370_DL2_BIT 0x0B0 /* RW: DL2 Bit Enable */
529 #define Bt8370_DL2_CTL 0x0B1 /* RW: DL2 Control */
530 #define Bt8370_RDL2_FFC 0x0B2 /* RW: RDL2 FIFO Fill Control */
531 #define Bt8370_RDL2 0x0B3 /* RO: RDL2 FIFO */
532 #define Bt8370_RDL2_STAT 0x0B4 /* RO: RDL2 Status */
533 #define Bt8370_TDL2_FEC 0x0B6 /* RW: TDL2 FIFO Empty Control */
534 #define Bt8370_TDL2_EOM 0x0B7 /* WO; TDL2 End Of Message Control */
535 #define Bt8370_TDL2 0x0B8 /* RW: TDL2 FIFO */
536 #define Bt8370_TDL2_STAT 0x0B9 /* RO: TDL2 Status */
537 #define Bt8370_DL_TEST1 0x0BA /* RW: DLINK Test Config */
538 #define Bt8370_DL_TEST2 0x0BB /* RW: DLINK Test Status */
539 #define Bt8370_DL_TEST3 0x0BC /* RW: DLINK Test Status */
540 #define Bt8370_DL_TEST4 0x0BD /* RW: DLINK Test Control */
541 #define Bt8370_DL_TEST5 0x0BE /* RW: DLINK Test Control */
542
543 #define Bt8370_SBI_CR 0x0D0 /* RW: System Bus Interface Config */
544 #define Bt8370_RSB_CR 0x0D1 /* RW: Rx System Bus Config */
545 #define Bt8370_RSYNC_BIT 0x0D2 /* RW: Rx System Bus Sync Bit Offs */
546 #define Bt8370_RSYNC_TS 0x0D3 /* RW: Rx System Bus Sync TS Offs */
547 #define Bt8370_TSB_CR 0x0D4 /* RW: Tx System Bus Config */
548 #define Bt8370_TSYNC_BIT 0x0D5 /* RW: Tx System Bus Sync Bit OFfs */
549 #define Bt8370_TSYNC_TS 0x0D6 /* RW: Tx System Bus Sync TS Offs */
550 #define Bt8370_RSIG_CR 0x0D7 /* RW: Rx Siganalling Config */
551 #define Bt8370_RSYNC_FRM 0x0D8 /* RW: Sig Reinsertion Frame Offs */
552 #define Bt8370_SSTAT 0x0D9 /* RO: Slip Buffer Status */
553 #define Bt8370_STACK 0x0DA /* RO: Rx Signalling Stack */
554 #define Bt8370_RPHASE 0x0DB /* RO: RSLIP Phase Status */
555 #define Bt8370_TPHASE 0x0DC /* RO: TSLIP Phase Status */
556 #define Bt8370_PERR 0x0DD /* RO: RAM Parity Status */
557
558 #define Bt8370_SBCn 0x0E0 /* RW: System Bus Per-Channel Ctl */
559 #define Bt8370_TPCn 0x100 /* RW: Tx Per-Channel Control */
560 #define Bt8370_TSIGn 0x120 /* RW: Tx Signalling Buffer */
561 #define Bt8370_TSLIP_LOn 0x140 /* RW: Tx PCM Slip Buffer Lo */
562 #define Bt8370_TSLIP_HIn 0x160 /* RW: Tx PCM Slip Buffer Hi */
563 #define Bt8370_RPCn 0x180 /* RW: Rx Per-Channel Control */
564 #define Bt8370_RSIGn 0x1A0 /* RW: Rx Signalling Buffer */
565 #define Bt8370_RSLIP_LOn 0x1C0 /* RW: Rx PCM Slip Buffer Lo */
566 #define Bt8370_RSLIP_HIn 0x1E0 /* RW: Rx PCM Slip Buffer Hi */
567
568 /* Bt8370_LOOP (0x14) framer loopback control register bits */
569 #define LOOP_ANALOG 0x01 /* inward loop thru LIU */
570 #define LOOP_FRAMER 0x02 /* inward loop thru framer */
571 #define LOOP_LINE 0x04 /* outward loop thru LIU */
572 #define LOOP_PAYLOAD 0x08 /* outward loop of payload */
573 #define LOOP_DUAL 0x06 /* inward framer + outward line */
574
575 /* Bt8370_ALM1 (0x47) receiver alarm status register bits */
576 #define ALM1_SIGFRZ 0x01 /* Rx Signalling Freeze */
577 #define ALM1_RLOF 0x02 /* Rx loss of frame alignment */
578 #define ALM1_RLOS 0x04 /* Rx digital loss of signal */
579 #define ALM1_RALOS 0x08 /* Rx analog loss of signal */
580 #define ALM1_RAIS 0x10 /* Rx Alarm Indication Signal */
581 #define ALM1_RYEL 0x40 /* Rx Yellow alarm indication */
582 #define ALM1_RMYEL 0x80 /* Rx multiframe YELLOW alarm */
583
584 /* Bt8370_ALM3 (0x49) receive framer status register bits */
585 #define ALM3_FRED 0x04 /* Rx Out Of T1/FAS alignment */
586 #define ALM3_MRED 0x08 /* Rx Out Of MFAS alignment */
587 #define ALM3_SRED 0x10 /* Rx Out Of CAS alignment */
588 #define ALM3_SEF 0x20 /* Rx Severely Errored Frame */
589 #define ALM3_RMAIS 0x40 /* Rx TS16 AIS (CAS) */
590
591 /* Bt8370_TALM (0x75) transmit alarm control register bits */
592 #define TALM_TAIS 0x01 /* Tx Alarm Indication Signal */
593 #define TALM_TYEL 0x02 /* Tx Yellow alarm */
594 #define TALM_TMYEL 0x04 /* Tx Multiframe Yellow alarm */
595 #define TALM_AUTO_AIS 0x08 /* auto send AIS on LOS */
596 #define TALM_AUTO_YEL 0x10 /* auto send YEL on LOF */
597 #define TALM_AUTO_MYEL 0x20 /* auto send E1-Y16 on loss-of-CAS */
598
599 /* 8370 BOP (Bit Oriented Protocol) command fragments */
600 #define RBOP_OFF 0x00 /* BOP Rx disabled */
601 #define RBOP_25 0xE0 /* BOP Rx requires 25 BOPs */
602 #define TBOP_OFF 0x00 /* BOP Tx disabled */
603 #define TBOP_25 0x0B /* BOP Tx sends 25 BOPs */
604 #define TBOP_CONT 0x0F /* BOP Tx sends continuously */
605
606 /* T1.403 Bit-Oriented ESF Data-Link Message codes */
607 #define T1BOP_OOF 0x00 /* Yellow alarm status */
608 #define T1BOP_LINE_UP 0x07 /* line loopback activate */
609 #define T1BOP_LINE_DOWN 0x1C /* line loopback deactivate */
610 #define T1BOP_PAY_UP 0x0A /* payload loopback activate */
611 #define T1BOP_PAY_DOWN 0x19 /* payload loopback deactivate */
612 #define T1BOP_NET_UP 0x09 /* network loopback activate */
613 #define T1BOP_NET_DOWN 0x12 /* network loopback deactivate */
614
615 /* Unix & Linux reserve 16 device-private IOCTLs */
616 #if BSD
617 # define LMCIOCGSTAT _IOWR('i', 240, struct status)
618 # define LMCIOCGCFG _IOWR('i', 241, struct config)
619 # define LMCIOCSCFG _IOW('i', 242, struct config)
620 # define LMCIOCREAD _IOWR('i', 243, struct ioctl)
621 # define LMCIOCWRITE _IOW('i', 244, struct ioctl)
622 # define LMCIOCTL _IOWR('i', 245, struct ioctl)
623 #endif
624
625 struct iohdr /* all LMCIOCs begin with this */
626 {
627 char ifname[IFNAMSIZ]; /* interface name, e.g. "lmc0" */
628 u_int32_t cookie; /* interface version number */
629 u_int16_t direction; /* missing in Linux IOCTL */
630 u_int16_t length; /* missing in Linux IOCTL */
631 struct iohdr *iohdr; /* missing in Linux IOCTL */
632 u_int32_t spare; /* pad this struct to **32 bytes** */
633 };
634
635 #define DIR_IO 0
636 #define DIR_IOW 1 /* copy data user->kernel */
637 #define DIR_IOR 2 /* copy data kernel->user */
638 #define DIR_IOWR 3 /* copy data kernel<->user */
639
640 struct hssi_snmp
641 {
642 u_int16_t sigs; /* MII16_HSSI & MII16_HSSI_MODEM */
643 };
644
645 struct ssi_snmp
646 {
647 u_int16_t sigs; /* MII16_SSI & MII16_SSI_MODEM */
648 };
649
650 struct t3_snmp
651 {
652 u_int16_t febe; /* 8 bits - Far End Block err cnt */
653 u_int16_t lcv; /* 16 bits - BPV err cnt */
654 u_int16_t pcv; /* 8 bits - P-bit err cnt */
655 u_int16_t ccv; /* 8 bits - C-bit err cnt */
656 u_int16_t line; /* line status bit vector */
657 u_int16_t loop; /* loop status bit vector */
658 };
659
660 struct t1_snmp
661 {
662 u_int16_t prm[4]; /* T1.403 Performance Report Msg */
663 u_int16_t febe; /* 10 bits - E1 FAR CRC err cnt */
664 u_int16_t lcv; /* 16 bits - BPV + EXZ err cnt */
665 u_int16_t fe; /* 12 bits - Ft/Fs/FPS/FAS err cnt */
666 u_int16_t crc; /* 10 bits - CRC6/CRC4 err cnt */
667 u_int16_t line; /* line status bit vector */
668 u_int16_t loop; /* loop status bit vector */
669 };
670
671 /* SNMP trunk MIB Send codes */
672 #define TSEND_NORMAL 1 /* Send data (normal or looped) */
673 #define TSEND_LINE 2 /* Send 'line loopback activate' */
674 #define TSEND_PAYLOAD 3 /* Send 'payload loop activate' */
675 #define TSEND_RESET 4 /* Send 'loopback deactivate' */
676 #define TSEND_QRS 5 /* Send Quasi Random Signal */
677
678 /* ANSI T1.403 Performance Report Msg -- once a second from the far end */
679 #define T1PRM_FE 0x8000 /* Frame Sync Bit Error Event >= 1 */
680 #define T1PRM_SE 0x4000 /* Severely Err Framing Event >= 1 */
681 #define T1PRM_LB 0x2000 /* Payload Loopback Activated */
682 #define T1PRM_G1 0x1000 /* CRC Error Event = 1 */
683 #define T1PRM_R 0x0800 /* Reserved */
684 #define T1PRM_G2 0x0400 /* 1 < CRC Error Event <= 5 */
685 #define T1PRM_SEQ 0x0300 /* modulo 4 counter */
686 #define T1PRM_G3 0x0080 /* 5 < CRC Error Event <= 10 */
687 #define T1PRM_LV 0x0040 /* Line Code Violation Event >= 1 */
688 #define T1PRM_G4 0x0020 /* 10 < CRC Error Event <= 100 */
689 #define T1PRM_U 0x0018 /* Under study for synchronization */
690 #define T1PRM_G5 0x0004 /* 100 < CRC Error Event <= 319 */
691 #define T1PRM_SL 0x0002 /* Slip Event >= 1 */
692 #define T1PRM_G6 0x0001 /* CRC Error Event >= 320 */
693
694 /* SNMP Line Status */
695 #define TLINE_NORM 0x0001 /* no alarm present */
696 #define TLINE_RX_RAI 0x0002 /* receiving RAI = Yellow alarm */
697 #define TLINE_TX_RAI 0x0004 /* sending RAI = Yellow alarm */
698 #define TLINE_RX_AIS 0x0008 /* receiving AIS = blue alarm */
699 #define TLINE_TX_AIS 0x0010 /* sending AIS = blue alarm */
700 #define TLINE_LOF 0x0020 /* near end LOF = red alarm */
701 #define TLINE_LOS 0x0040 /* near end loss of Signal */
702 #define TLINE_LOOP 0x0080 /* near end is looped */
703 #define T1LINE_RX_TS16_AIS 0x0100 /* near end receiving TS16 AIS */
704 #define T1LINE_RX_TS16_LOMF 0x0200 /* near end sending TS16 LOMF */
705 #define T1LINE_TX_TS16_LOMF 0x0400 /* near end receiving TS16 LOMF */
706 #define T1LINE_RX_TEST 0x0800 /* near end receiving QRS Signal */
707 #define T1LINE_SEF 0x1000 /* near end severely errored frame */
708 #define T3LINE_RX_IDLE 0x0100 /* near end receiving IDLE signal */
709 #define T3LINE_SEF 0x0200 /* near end severely errored frame */
710
711 /* SNMP Loopback Status */
712 #define TLOOP_NONE 0x01 /* no loopback */
713 #define TLOOP_NEAR_PAYLOAD 0x02 /* near end payload loopback */
714 #define TLOOP_NEAR_LINE 0x04 /* near end line loopback */
715 #define TLOOP_NEAR_OTHER 0x08 /* near end looped somehow */
716 #define TLOOP_NEAR_INWARD 0x10 /* near end looped inward */
717 #define TLOOP_FAR_PAYLOAD 0x20 /* far end payload loopback */
718 #define TLOOP_FAR_LINE 0x40 /* far end line loopback */
719
720 /* event counters record interesting statistics */
721 struct cntrs
722 {
723 struct timeval reset_time; /* time when cntrs were reset */
724 u_int64_t ibytes; /* Rx bytes with good status */
725 u_int64_t obytes; /* Tx bytes */
726 u_int64_t ipackets; /* Rx packets with good status */
727 u_int64_t opackets; /* Tx packets */
728 u_int32_t ierrors; /* Rx packets with bad status */
729 u_int32_t oerrors; /* Tx packets with bad status */
730 u_int32_t idrops; /* Rx packets dropped by SW */
731 u_int32_t missed; /* Rx pkts missed: no DMA descs */
732 u_int32_t odrops; /* Tx packets dropped by SW */
733 u_int32_t fifo_over; /* Rx fifo overruns from DMA desc */
734 u_int32_t overruns; /* Rx fifo overruns from CSR */
735 u_int32_t fifo_under; /* Tx fifo underruns from DMA desc */
736 u_int32_t underruns; /* Rx fifo underruns from CSR */
737 u_int32_t fdl_pkts; /* Rx T1 Facility Data Link pkts */
738 u_int32_t crc_errs; /* Rx T1 frame CRC errors */
739 u_int32_t lcv_errs; /* Rx T1 T3 Line Coding Violation */
740 u_int32_t frm_errs; /* Rx T1 T3 Frame bit errors */
741 u_int32_t febe_errs; /* Rx T1 T3 Far End Bit Errors */
742 u_int32_t par_errs; /* Rx T3 P-bit parity errors */
743 u_int32_t cpar_errs; /* Rx T3 C-bit parity errors */
744 u_int32_t mfrm_errs; /* Rx T3 Multi-frame bit errors */
745 u_int32_t rxbuf; /* Rx out of packet buffers */
746 u_int32_t txdma; /* Tx out of DMA desciptors */
747 u_int32_t lck_watch; /* lock conflict in watchdog */
748 u_int32_t lck_intr; /* lock conflict in interrupt */
749 u_int32_t spare1; /* debugging temp */
750 u_int32_t spare2; /* debugging temp */
751 u_int32_t spare3; /* debugging temp */
752 u_int32_t spare4; /* debugging temp */
753 };
754
755 /* sc->status is the READ ONLY status of the card. */
756 /* Accessed using socket IO control calls or netgraph control messages. */
757 struct status
758 {
759 struct iohdr iohdr; /* common ioctl header */
760 u_int32_t card_type; /* PCI device number */
761 u_int16_t link_state; /* actual state: up, down, test */
762 u_int32_t tx_speed; /* measured TX bits/sec */
763 u_int32_t cable_type; /* SSI only: cable type */
764 u_int32_t time_slots; /* T1E1 only: actual TSs in use */
765 u_int32_t stack; /* actual line stack in use */
766 u_int32_t proto; /* actual line proto in use */
767 u_int32_t keep_alive; /* actual keep-alive status */
768 u_int32_t ticks; /* incremented by watchdog @ 1 Hz */
769 struct cntrs cntrs; /* event counters */
770 union
771 {
772 struct hssi_snmp hssi; /* data for RFC-???? HSSI MIB */
773 struct t3_snmp t3; /* data for RFC-2496 T3 MIB */
774 struct ssi_snmp ssi; /* data for RFC-1659 RS232 MIB */
775 struct t1_snmp t1; /* data for RFC-2495 T1 MIB */
776 } snmp;
777 };
778
779 /* protocol stack codes */
780 #define STACK_NONE 0 /* not set fnobl */
781 #define STACK_RAWIP 1 /* driver yyyyy */
782 #define STACK_SPPP 2 /* fbsd, nbsd, obsd yyynn */
783 #define STACK_P2P 3 /* bsd/os nnnyn */
784 #define STACK_GEN_HDLC 4 /* linux nnnny */
785 #define STACK_SYNC_PPP 5 /* linux nnnny */
786 #define STACK_NETGRAPH 6 /* fbsd ynnnn */
787
788 /* line protocol codes */
789 #define PROTO_NONE 0 /* not set fnobl */
790 #define PROTO_IP_HDLC 1 /* raw IP4/6 pkts in HDLC yyyyy */
791 #define PROTO_PPP 2 /* Point-to-Point Protocol yyyyy */
792 #define PROTO_C_HDLC 3 /* Cisco HDLC Protocol yyyyy */
793 #define PROTO_FRM_RLY 4 /* Frame Relay Protocol ynnyy */
794 #define PROTO_ETH_HDLC 5 /* raw Ether pkts in HDLC nnnny */
795 #define PROTO_X25 6 /* X.25/LAPB Protocol nnnny */
796
797 /* oper_status codes (same as SNMP status codes) */
798 #define STATE_UP 1 /* may/will tx/rx pkts */
799 #define STATE_DOWN 2 /* can't/won't tx/rx pkts */
800 #define STATE_TEST 3 /* currently not used */
801
802 struct synth /* programmable oscillator params */
803 {
804 unsigned n:7; /* numerator (3..127) */
805 unsigned m:7; /* denominator (3..127) */
806 unsigned v:1; /* mul by 1|8 */
807 unsigned x:2; /* div by 1|2|4|8 */
808 unsigned r:2; /* div by 1|2|4|8 */
809 unsigned prescale:13; /* log(final divisor): 2, 4 or 9 */
810 } __packed;
811
812 #define SYNTH_FREF 20e6 /* reference xtal = 20 MHz */
813 #define SYNTH_FMIN 50e6 /* internal VCO min 50 MHz */
814 #define SYNTH_FMAX 250e6 /* internal VCO max 250 MHz */
815
816 /* sc->config is the READ/WRITE configuration of the card. */
817 /* Accessed using socket IO control calls or netgraph control messages. */
818 struct config
819 {
820 struct iohdr iohdr; /* common ioctl header */
821 u_int32_t crc_len; /* ALL: CRC-16 or CRC-32 or none */
822 u_int32_t loop_back; /* ALL: many kinds of loopbacks */
823 u_int32_t tx_clk_src; /* T1, HSSI: ST, RT, int, ext */
824 u_int32_t format; /* T3, T1: ckt framing format */
825 u_int32_t time_slots; /* T1: 64Kb time slot config */
826 u_int32_t cable_len; /* T3, T1: cable length in meters */
827 u_int32_t scrambler; /* T3: payload scrambler config */
828 u_int32_t dte_dce; /* SSI, HSSIc: drive TXCLK */
829 struct synth synth; /* SSI, HSSIc: synth oscil params */
830 u_int32_t rx_gain_max; /* T1: receiver gain limit 0-50 dB */
831 u_int32_t tx_pulse; /* T1: transmitter pulse shape */
832 u_int32_t tx_lbo; /* T1: transmitter atten 0-22.5 dB */
833 u_int32_t debug; /* ALL: extra printout */
834 u_int32_t stack; /* ALL: use this line stack */
835 u_int32_t proto; /* ALL: use this line proto */
836 u_int32_t keep_alive; /* SPPP: use keep-alive packets */
837 };
838
839 #define CFG_CRC_0 0 /* no CRC */
840 #define CFG_CRC_16 2 /* X^16+X^12+X^5+1 (default) */
841 #define CFG_CRC_32 4 /* X^32+X^26+X^23+X^22+X^16+X^12+ */
842 /* X^11+X^10+X^8+X^7+X^5+X^4+X^2+X+1 */
843 #define CFG_LOOP_NONE 1 /* SNMP don't loop back anything */
844 #define CFG_LOOP_PAYLOAD 2 /* SNMP loop outward thru framer */
845 #define CFG_LOOP_LINE 3 /* SNMP loop outward thru LIU */
846 #define CFG_LOOP_OTHER 4 /* SNMP loop inward thru LIU */
847 #define CFG_LOOP_INWARD 5 /* SNMP loop inward thru framer */
848 #define CFG_LOOP_DUAL 6 /* SNMP loop inward & outward */
849 #define CFG_LOOP_TULIP 16 /* ALL: loop inward thru Tulip */
850 #define CFG_LOOP_PINS 17 /* HSSIc, SSI: loop inward-pins */
851 #define CFG_LOOP_LL 18 /* HSSI, SSI: assert LA/LL mdm pin */
852 #define CFG_LOOP_RL 19 /* HSSI, SSI: assert LB/RL mdm pin */
853
854 #define CFG_CLKMUX_ST 1 /* TX clk <- Send timing */
855 #define CFG_CLKMUX_INT 2 /* TX clk <- internal source */
856 #define CFG_CLKMUX_RT 3 /* TX clk <- Receive (loop) timing */
857 #define CFG_CLKMUX_EXT 4 /* TX clk <- ext connector */
858
859 /* values 0-31 are Bt8370 CR0 register values (LSB is zero if E1). */
860 /* values 32-99 are reserved for other T1E1 formats, (even number if E1) */
861 /* values 100 and up are used for T3 frame formats. */
862 #define CFG_FORMAT_T1SF 9 /* T1-SF AMI */
863 #define CFG_FORMAT_T1ESF 27 /* T1-ESF+CRC B8ZS X^6+X+1 */
864 #define CFG_FORMAT_E1FAS 0 /* E1-FAS HDB3 TS0 */
865 #define CFG_FORMAT_E1FASCRC 8 /* E1-FAS+CRC HDB3 TS0 X^4+X+1 */
866 #define CFG_FORMAT_E1FASCAS 16 /* E1-FAS +CAS HDB3 TS0 & TS16 */
867 #define CFG_FORMAT_E1FASCRCCAS 24 /* E1-FAS+CRC+CAS HDB3 TS0 & TS16 */
868 #define CFG_FORMAT_E1NONE 32 /* E1-NO framing HDB3 */
869 #define CFG_FORMAT_T3CPAR 100 /* T3-C-Bit par B3ZS */
870 #define CFG_FORMAT_T3M13 101 /* T3-M13 format B3ZS */
871
872 /* format aliases that improve code readability */
873 #define FORMAT_T1ANY ((sc->config.format & 1)==1)
874 #define FORMAT_E1ANY ((sc->config.format & 1)==0)
875 #define FORMAT_E1CAS ((sc->config.format & 0x11)==0x10)
876 #define FORMAT_E1CRC ((sc->config.format & 0x09)==0x08)
877 #define FORMAT_E1NONE (sc->config.format == CFG_FORMAT_E1NONE)
878 #define FORMAT_T1ESF (sc->config.format == CFG_FORMAT_T1ESF)
879 #define FORMAT_T1SF (sc->config.format == CFG_FORMAT_T1SF)
880 #define FORMAT_T3CPAR (sc->config.format == CFG_FORMAT_T3CPAR)
881
882 #define CFG_SCRAM_OFF 1 /* DS3 payload scrambler off */
883 #define CFG_SCRAM_DL_KEN 2 /* DS3 DigitalLink/Kentrox X^43+1 */
884 #define CFG_SCRAM_LARS 3 /* DS3 Larscom X^20+X^17+1 w/28ZS */
885
886 #define CFG_DTE 1 /* HSSIc, SSI: rcv TXCLK; rcv DCD */
887 #define CFG_DCE 2 /* HSSIc, SSI: drv TXCLK; drv DCD */
888
889 #define CFG_GAIN_SHORT 0x24 /* 0-20 dB of equalized gain */
890 #define CFG_GAIN_MEDIUM 0x2C /* 0-30 dB of equalized gain */
891 #define CFG_GAIN_LONG 0x34 /* 0-40 dB of equalized gain */
892 #define CFG_GAIN_EXTEND 0x3F /* 0-64 dB of equalized gain */
893 #define CFG_GAIN_AUTO 0xFF /* auto-set based on cable length */
894
895 #define CFG_PULSE_T1DSX0 0 /* T1 DSX 0- 40 meters */
896 #define CFG_PULSE_T1DSX1 2 /* T1 DSX 40- 80 meters */
897 #define CFG_PULSE_T1DSX2 4 /* T1 DSX 80-120 meters */
898 #define CFG_PULSE_T1DSX3 6 /* T1 DSX 120-160 meters */
899 #define CFG_PULSE_T1DSX4 8 /* T1 DSX 160-200 meters */
900 #define CFG_PULSE_E1COAX 10 /* E1 75 ohm coax pair */
901 #define CFG_PULSE_E1TWIST 12 /* E1 120 ohm twisted pairs */
902 #define CFG_PULSE_T1CSU 14 /* T1 CSU 200-2000 meters; set LBO */
903 #define CFG_PULSE_AUTO 0xFF /* auto-set based on cable length */
904
905 #define CFG_LBO_0DB 0 /* T1CSU LBO = 0.0 dB; FCC opt A */
906 #define CFG_LBO_7DB 16 /* T1CSU LBO = 7.5 dB; FCC opt B */
907 #define CFG_LBO_15DB 32 /* T1CSU LBO = 15.0 dB; FCC opt C */
908 #define CFG_LBO_22DB 48 /* T1CSU LBO = 22.5 dB; final span */
909 #define CFG_LBO_AUTO 0xFF /* auto-set based on cable length */
910
911 struct ioctl
912 {
913 struct iohdr iohdr; /* common ioctl header */
914 u_int32_t cmd; /* command */
915 u_int32_t address; /* command address */
916 u_int32_t data; /* command data */
917 char *ucode; /* user-land address of ucode */
918 };
919
920 #define IOCTL_RW_PCI 1 /* RW: Tulip PCI config registers */
921 #define IOCTL_RW_CSR 2 /* RW: Tulip Control & Status Regs */
922 #define IOCTL_RW_SROM 3 /* RW: Tulip Serial Rom */
923 #define IOCTL_RW_BIOS 4 /* RW: Tulip Boot rom */
924 #define IOCTL_RW_MII 5 /* RW: MII registers */
925 #define IOCTL_RW_FRAME 6 /* RW: Framer registers */
926 #define IOCTL_WO_SYNTH 7 /* WO: Synthesized oscillator */
927 #define IOCTL_WO_DAC 8 /* WO: Digital/Analog Converter */
928
929 #define IOCTL_XILINX_RESET 16 /* reset Xilinx: all FFs set to 0 */
930 #define IOCTL_XILINX_ROM 17 /* load Xilinx program from ROM */
931 #define IOCTL_XILINX_FILE 18 /* load Xilinx program from file */
932
933 #define IOCTL_SET_STATUS 50 /* set mdm ctrl bits (internal) */
934 #define IOCTL_SNMP_SEND 51 /* trunk MIB send code */
935 #define IOCTL_SNMP_LOOP 52 /* trunk MIB loop configuration */
936 #define IOCTL_SNMP_SIGS 53 /* RS232-like modem control sigs */
937 #define IOCTL_RESET_CNTRS 54 /* reset event counters */
938
939 /* storage for these strings is allocated here! */
940 const char *ssi_cables[] =
941 {
942 "V.10/EIA423",
943 "V.11/EIA530A",
944 "RESERVED",
945 "X.21",
946 "V.35",
947 "V.36/EIA449",
948 "V.28/EIA232",
949 "NO CABLE",
950 NULL,
951 };
952
953 /***************************************************************************/
954 /* Declarations above here are shared with the user lmcconfig program. */
955 /* Declarations below here are private to the kernel device driver. */
956 /***************************************************************************/
957
958 #if KERNEL || _KERNEL || __KERNEL__
959
960 /* Hide the minor differences between Operating Systems */
961
962 typedef int intr_return_t;
963 # define READ_PCI_CFG(sc, addr) pci_conf_read ((sc)->pa_pc, (sc)->pa_tag, addr)
964 # define WRITE_PCI_CFG(sc, addr, data) pci_conf_write((sc)->pa_pc, (sc)->pa_tag, addr, data)
965 # define READ_CSR(sc, csr) bus_space_read_4 ((sc)->csr_tag, (sc)->csr_handle, csr)
966 # define WRITE_CSR(sc, csr, val) bus_space_write_4((sc)->csr_tag, (sc)->csr_handle, csr, val)
967 # define NAME_UNIT device_xname(&sc->dev)
968 # define BOOT_VERBOSE (boothowto & AB_VERBOSE)
969 # define TOP_LOCK(sc) (mutex_spin_enter(&(sc)->top_lock), 0)
970 # define TOP_TRYLOCK(sc) mutex_tryenter(&(sc)->top_lock)
971 # define TOP_UNLOCK(sc) mutex_spin_exit(&(sc)->top_lock)
972 # define BOTTOM_TRYLOCK(sc) __cpu_simple_lock_try(&(sc)->bottom_lock)
973 # define BOTTOM_UNLOCK(sc) __cpu_simple_unlock (&(sc)->bottom_lock)
974 # define CHECK_CAP kauth_authorize_generic(curlwp->l_cred, KAUTH_GENERIC_ISSUSER, NULL)
975 # define DISABLE_INTR int spl = splnet()
976 # define ENABLE_INTR splx(spl)
977 # define IRQ_NONE 0
978 # define IRQ_HANDLED 1
979 # define IFP2SC(ifp) (ifp)->if_softc
980 # define COPY_BREAK MHLEN
981 # define SLEEP(usecs) tsleep(sc, PZERO, DEVICE_NAME, 1+(usecs/tick))
982 # define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, 0, size, flags)
983 # define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, 0, BUS_DMA_NOWAIT)
984 # if NBPFILTER
985 # define LMC_BPF_MTAP(sc, mbuf) if ((sc)->ifp->if_bpf) bpf_mtap((sc)->ifp->if_bpf, mbuf)
986 # define LMC_BPF_ATTACH(sc, dlt, len) bpfattach((sc)->ifp, dlt, len)
987 # define LMC_BPF_DETACH(sc) bpfdetach((sc)->ifp)
988 # endif
989
990 static int driver_announced = 0; /* print driver info once only */
991
992 #define SNDQ_MAXLEN 32 /* packets awaiting transmission */
993 #define DESCS_PER_PKT 4 /* DMA descriptors per TX pkt */
994 #define NUM_TX_DESCS (DESCS_PER_PKT * SNDQ_MAXLEN)
995 /* Increase DESCS_PER_PKT if status.cntrs.txdma increments. */
996
997 /* A Tulip DMA descriptor can point to two chunks of memory.
998 * Each chunk has a max length of 2047 bytes (ask the VMS guys).
999 * 2047 isn't a multiple of a cache line size (32 bytes typically).
1000 * So back off to 2048-32 = 2016 bytes per chunk (2 chunks per descr).
1001 */
1002 #define MAX_CHUNK_LEN (2048-32)
1003 #define MAX_DESC_LEN (2 * MAX_CHUNK_LEN)
1004
1005 /* Tulip DMA descriptor; THIS STRUCT MUST MATCH THE HARDWARE */
1006 struct dma_desc
1007 {
1008 u_int32_t status; /* hardware->to->software */
1009 #if BYTE_ORDER == LITTLE_ENDIAN /* left-to-right packing */
1010 unsigned length1:11; /* buffer1 length */
1011 unsigned length2:11; /* buffer2 length */
1012 unsigned control:10; /* software->to->hardware */
1013 #else /* right-to-left packing */
1014 unsigned control:10; /* software->to->hardware */
1015 unsigned length2:11; /* buffer2 length */
1016 unsigned length1:11; /* buffer1 length */
1017 #endif
1018 u_int32_t address1; /* buffer1 bus address */
1019 u_int32_t address2; /* buffer2 bus address */
1020 bus_dmamap_t map; /* bus dmamap for this descriptor */
1021 # define TLP_BUS_DSL_VAL (sizeof(bus_dmamap_t) & TLP_BUS_DSL)
1022 } __packed;
1023
1024 /* Tulip DMA descriptor status bits */
1025 #define TLP_DSTS_OWNER 0x80000000
1026 #define TLP_DSTS_RX_DESC_ERR 0x00004000
1027 #define TLP_DSTS_RX_FIRST_DESC 0x00000200
1028 #define TLP_DSTS_RX_LAST_DESC 0x00000100
1029 #define TLP_DSTS_RX_MII_ERR 0x00000008
1030 #define TLP_DSTS_RX_DRIBBLE 0x00000004
1031 #define TLP_DSTS_TX_UNDERRUN 0x00000002
1032 #define TLP_DSTS_RX_OVERRUN 0x00000001 /* not documented in rev AF */
1033 #define TLP_DSTS_RX_BAD (TLP_DSTS_RX_MII_ERR | \
1034 TLP_DSTS_RX_DRIBBLE | \
1035 TLP_DSTS_RX_DESC_ERR | \
1036 TLP_DSTS_RX_OVERRUN)
1037
1038 /* Tulip DMA descriptor control bits */
1039 #define TLP_DCTL_TX_INTERRUPT 0x0200
1040 #define TLP_DCTL_TX_LAST_SEG 0x0100
1041 #define TLP_DCTL_TX_FIRST_SEG 0x0080
1042 #define TLP_DCTL_TX_NO_CRC 0x0010
1043 #define TLP_DCTL_END_RING 0x0008
1044 #define TLP_DCTL_TX_NO_PAD 0x0002
1045
1046 /* DMA descriptors are kept in a ring.
1047 * Ring is empty when (read == write).
1048 * Ring is full when (read == wrap(write+1)),
1049 * The ring also contains a tailq of data buffers.
1050 */
1051 struct desc_ring
1052 {
1053 struct dma_desc *read; /* next descriptor to be read */
1054 struct dma_desc *write; /* next descriptor to be written */
1055 struct dma_desc *first; /* first descriptor in ring */
1056 struct dma_desc *last; /* last descriptor in ring */
1057 struct dma_desc *temp; /* temporary write pointer for tx */
1058 u_int32_t dma_addr; /* bus addr for desc array XXX */
1059 int size_descs; /* bus_dmamap_sync needs this */
1060 int num_descs; /* used to set rx quota */
1061 #if IFNET || NETGRAPH
1062 struct mbuf *head; /* tail-queue of mbufs */
1063 struct mbuf *tail;
1064 #elif NETDEV
1065 struct sk_buff *head; /* tail-queue of skbuffs */
1066 struct sk_buff *tail;
1067 #endif
1068 bus_dma_tag_t tag; /* bus_dma_tag for desc array */
1069 bus_dmamap_t map; /* bus_dmamap for desc array */
1070 bus_dma_segment_t segs[2]; /* bus_dmamap_load() or bus_dmamem_alloc() */
1071 int nsegs; /* bus_dmamap_load() or bus_dmamem_alloc() */
1072 };
1073
1074 /* break circular definition */
1075 typedef struct softc softc_t;
1076
1077 struct card /* an object */
1078 {
1079 void (*ident) (softc_t *);
1080 void (*watchdog) (softc_t *);
1081 int (*ioctl) (softc_t *, struct ioctl *);
1082 void (*attach) (softc_t *, struct config *);
1083 void (*detach) (softc_t *);
1084 };
1085
1086 struct stack /* an object */
1087 {
1088 #if IFNET || NETGRAPH
1089 int (*ioctl) (softc_t *, u_long, void *);
1090 void (*input) (softc_t *, struct mbuf *);
1091 void (*output) (softc_t *);
1092 #elif NETDEV
1093 int (*ioctl) (softc_t *, struct ifreq *, int);
1094 int (*type) (softc_t *, struct sk_buff *);
1095 int (*mtu) (softc_t *, int);
1096 #endif
1097 void (*watchdog) (softc_t *);
1098 int (*open) (softc_t *, struct config *);
1099 int (*attach) (softc_t *, struct config *);
1100 int (*detach) (softc_t *);
1101 };
1102
1103 /* This is the instance data, or "software context" for the device driver. */
1104 /* NetBSD, OpenBSD and BSD/OS want struct device first in the softc. */
1105 struct softc
1106 {
1107
1108 struct device dev; /* must be first in softc */
1109 pcitag_t pa_tag;
1110 pci_chipset_tag_t pa_pc;
1111 bus_dma_tag_t pa_dmat;
1112 bus_space_tag_t csr_tag;
1113 bus_space_handle_t csr_handle;
1114 pci_intr_handle_t intr_handle;
1115 void *irq_cookie;
1116 void *sdh_cookie;
1117 struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */
1118 kmutex_t top_lock; /* lock card->watchdog vs ioctls */
1119 __cpu_simple_lock_t bottom_lock; /* lock buf queues & descriptor rings */
1120
1121 /* State for kernel-resident Line Protocols */
1122 #if IFNET
1123 # if SPPP
1124 struct sppp spppcom;
1125 struct sppp *sppp;
1126 # elif P2P
1127 struct p2pcom p2pcom;
1128 struct p2pcom *p2p;
1129 # else
1130 struct ifnet ifnet;
1131 # endif
1132 struct ifnet *ifp;
1133 struct ifmedia ifm;
1134 #endif /* IFNET */
1135
1136 #if NETDEV
1137 # if GEN_HDLC
1138 hdlc_device *hdlcdev; /* contains struct net_device_stats */
1139 # else
1140 struct net_device_stats netdev_stats;
1141 # endif
1142 # if SYNC_PPP
1143 struct ppp_device *ppd;
1144 struct ppp_device ppp_dev; /* contains a struct sppp */
1145 struct sppp *sppp;
1146 # endif
1147 struct net_device *netdev;
1148 #endif /* NETDEV */
1149
1150
1151
1152
1153 /* State used by all card types; lock with top_lock. */
1154 struct status status; /* lmcconfig can read */
1155 struct config config; /* lmcconfig can read/write */
1156 const char *dev_desc; /* string describing card */
1157 struct card *card; /* card methods */
1158 struct stack *stack; /* line methods */
1159 u_int32_t gpio_dir; /* s/w copy of GPIO direction reg */
1160 u_int16_t led_state; /* last value written to mii16 */
1161 int quota; /* used for packet flow control */
1162
1163 /* State used by card-specific watchdogs; lock with top_lock. */
1164 u_int32_t last_mii16; /* SSI, HSSI: MII reg 16 one sec ago */
1165 u_int32_t last_stat16; /* T3: framer reg 16 one sec ago */
1166 u_int32_t last_alm1; /* T1E1: framer reg 47 one sec ago */
1167 u_int32_t last_link_state; /* ALL: status.link_state 1 ec ago */
1168 u_int32_t last_FEAC; /* T3: last FEAC msg code received */
1169 u_int32_t loop_timer; /* T1E1, T3: secs until loop ends */
1170
1171 /* State used by the interrupt code; lock with bottom_lock. */
1172 struct desc_ring txring; /* tx descriptor ring state */
1173 struct desc_ring rxring; /* rx descriptor ring state */
1174 }; /* end of softc */
1175
1176 #if BSD && (NBPFILTER == 0)
1177 # define LMC_BPF_MTAP(sc, mbuf) /* nothing */
1178 # define LMC_BPF_ATTACH(sc, dlt, len) /* nothing */
1179 # define LMC_BPF_DETACH(sc) /* nothing */
1180 #endif
1181
1182
1183 #define HSSI_DESC "LMC5200 HSSI Card"
1184 #define T3_DESC "LMC5245 T3 Card"
1185 #define SSI_DESC "LMC1000 SSI Card"
1186 #define T1E1_DESC "LMC1200 T1E1 Card"
1187
1188 /* procedure prototypes */
1189
1190 static void srom_shift_bits(softc_t *, u_int32_t, u_int32_t);
1191 static u_int16_t srom_read(softc_t *, u_int8_t);
1192 static void srom_write(softc_t *, u_int8_t, u_int16_t);
1193
1194 static u_int8_t bios_read(softc_t *, u_int32_t);
1195 static void bios_write_phys(softc_t *, u_int32_t, u_int8_t);
1196 static void bios_write(softc_t *, u_int32_t, u_int8_t);
1197 static void bios_erase(softc_t *);
1198
1199 static void mii_shift_bits(softc_t *, u_int32_t, u_int32_t);
1200 static u_int16_t mii_read(softc_t *, u_int8_t);
1201 static void mii_write(softc_t *, u_int8_t, u_int16_t);
1202
1203 static void mii16_set_bits(softc_t *, u_int16_t);
1204 static void mii16_clr_bits(softc_t *, u_int16_t);
1205 static void mii17_set_bits(softc_t *, u_int16_t);
1206 static void mii17_clr_bits(softc_t *, u_int16_t);
1207
1208 static void led_off(softc_t *, u_int16_t);
1209 static void led_on(softc_t *, u_int16_t);
1210 static void led_inv(softc_t *, u_int16_t);
1211
1212 static void framer_write(softc_t *, u_int16_t, u_int8_t);
1213 static u_int8_t framer_read(softc_t *, u_int16_t);
1214
1215 static void gpio_make_input(softc_t *, u_int32_t);
1216 static void gpio_make_output(softc_t *, u_int32_t);
1217 static u_int32_t gpio_read(softc_t *);
1218 static void gpio_set_bits(softc_t *, u_int32_t);
1219 static void gpio_clr_bits(softc_t *, u_int32_t);
1220
1221 static void xilinx_reset(softc_t *);
1222 static void xilinx_load_from_rom(softc_t *);
1223 static int xilinx_load_from_file(softc_t *, char *, u_int32_t);
1224
1225 static void synth_shift_bits(softc_t *, u_int32_t, u_int32_t);
1226 static void synth_write(softc_t *, struct synth *);
1227
1228 static void dac_write(softc_t *, u_int16_t);
1229
1230 static void hssi_ident(softc_t *);
1231 static void hssi_watchdog(softc_t *);
1232 static int hssi_ioctl(softc_t *, struct ioctl *);
1233 static void hssi_attach(softc_t *, struct config *);
1234 static void hssi_detach(softc_t *);
1235
1236 static void t3_ident(softc_t *);
1237 static void t3_watchdog(softc_t *);
1238 static int t3_ioctl(softc_t *, struct ioctl *);
1239 static void t3_send_dbl_feac(softc_t *, int, int);
1240 static void t3_attach(softc_t *, struct config *);
1241 static void t3_detach(softc_t *);
1242
1243 static void ssi_ident(softc_t *);
1244 static void ssi_watchdog(softc_t *);
1245 static int ssi_ioctl(softc_t *, struct ioctl *);
1246 static void ssi_attach(softc_t *, struct config *);
1247 static void ssi_detach(softc_t *);
1248
1249 static void t1_ident(softc_t *);
1250 static void t1_watchdog(softc_t *);
1251 static int t1_ioctl(softc_t *, struct ioctl *);
1252 static void t1_send_bop(softc_t *, int);
1253 static void t1_attach(softc_t *, struct config *);
1254 static void t1_detach(softc_t *);
1255
1256
1257 #if SYNC_PPP
1258 static int sync_ppp_ioctl(softc_t *, struct ifreq *, int);
1259 static int sync_ppp_type(softc_t *, struct sk_buff *);
1260 static int sync_ppp_mtu(softc_t *, int);
1261 static void sync_ppp_watchdog(softc_t *);
1262 static int sync_ppp_open(softc_t *, struct config *);
1263 static int sync_ppp_attach(softc_t *, struct config *);
1264 static int sync_ppp_detach(softc_t *);
1265 #endif /* SYNC_PPP */
1266
1267 #if GEN_HDLC
1268 static int gen_hdlc_ioctl(softc_t *, struct ifreq *, int);
1269 static int gen_hdlc_type(softc_t *, struct sk_buff *);
1270 static int gen_hdlc_mtu(softc_t *, int);
1271 static void gen_hdlc_watchdog(softc_t *);
1272 static int gen_hdlc_open(softc_t *, struct config *);
1273 static int gen_hdlc_attach(softc_t *, struct config *);
1274 static int gen_hdlc_detach(softc_t *);
1275 static int gen_hdlc_card_params(struct net_device *, unsigned short,
1276 unsigned short);
1277 #endif /* GEN_HDLC */
1278
1279 #if P2P
1280 static int p2p_stack_ioctl(softc_t *, u_long, void *);
1281 static void p2p_stack_input(softc_t *, struct mbuf *);
1282 static void p2p_stack_output(softc_t *);
1283 static void p2p_stack_watchdog(softc_t *);
1284 static int p2p_stack_open(softc_t *, struct config *);
1285 static int p2p_stack_attach(softc_t *, struct config *);
1286 static int p2p_stack_detach(softc_t *);
1287 static int p2p_getmdm(struct p2pcom *, void *);
1288 static int p2p_mdmctl(struct p2pcom *, int);
1289 #endif /* P2P */
1290
1291 #if SPPP
1292 static int sppp_stack_ioctl(softc_t *, u_long, void *);
1293 static void sppp_stack_input(softc_t *, struct mbuf *);
1294 static void sppp_stack_output(softc_t *);
1295 static void sppp_stack_watchdog(softc_t *);
1296 static int sppp_stack_open(softc_t *, struct config *);
1297 static int sppp_stack_attach(softc_t *, struct config *);
1298 static int sppp_stack_detach(softc_t *);
1299 static void sppp_tls(struct sppp *);
1300 static void sppp_tlf(struct sppp *);
1301 #endif /* SPPP */
1302
1303 #if IFNET
1304 static int rawip_ioctl(softc_t *, u_long, void *);
1305 static void rawip_input(softc_t *, struct mbuf *);
1306 static void rawip_output(softc_t *);
1307 #elif NETDEV
1308 static int rawip_ioctl(softc_t *, struct ifreq *, int);
1309 static int rawip_type(softc_t *, struct sk_buff *);
1310 static int rawip_mtu(softc_t *, int);
1311 #endif
1312 static void rawip_watchdog(softc_t *);
1313 static int rawip_open(softc_t *, struct config *);
1314 static int rawip_attach(softc_t *, struct config *);
1315 static int rawip_detach(softc_t *);
1316
1317 #if IFNET
1318 static void ifnet_input(struct ifnet *, struct mbuf *);
1319 static int ifnet_output(struct ifnet *, struct mbuf *,
1320 const struct sockaddr *, struct rtentry *);
1321 static int ifnet_ioctl(struct ifnet *, u_long, void *);
1322 static void ifnet_start(struct ifnet *);
1323 static void ifnet_watchdog(struct ifnet *);
1324
1325 static void ifnet_setup(struct ifnet *);
1326 static int ifnet_attach(softc_t *);
1327 static void ifnet_detach(softc_t *);
1328
1329 static void ifmedia_setup(softc_t *);
1330 static int lmc_ifmedia_change(struct ifnet *);
1331 static void ifmedia_status(struct ifnet *, struct ifmediareq *);
1332 #endif /* IFNET */
1333
1334 #if NETDEV
1335 static int netdev_open(struct net_device *);
1336 static int netdev_stop(struct net_device *);
1337 static int netdev_start(struct sk_buff *, struct net_device *);
1338 # if NAPI
1339 static int netdev_poll(struct net_device *, int *);
1340 # endif
1341 static int netdev_ioctl(struct net_device *, struct ifreq *, int);
1342 static int netdev_mtu(struct net_device *, int);
1343 static void netdev_timeout(struct net_device *);
1344 static struct net_device_stats *netdev_stats(struct net_device *);
1345 static void netdev_watchdog(unsigned long);
1346
1347 static void netdev_setup(struct net_device *);
1348 static int netdev_attach(softc_t *);
1349 static void netdev_detach(softc_t *);
1350 #endif /* NETDEV */
1351
1352
1353 #if BSD
1354 static int create_ring(softc_t *, struct desc_ring *, int);
1355 static void destroy_ring(softc_t *, struct desc_ring *);
1356
1357 static void mbuf_enqueue(struct desc_ring *, struct mbuf *);
1358 static struct mbuf *mbuf_dequeue(struct desc_ring *);
1359
1360 static int rxintr_cleanup(softc_t *);
1361 static int rxintr_setup(softc_t *);
1362 static int txintr_cleanup(softc_t *);
1363 static int txintr_setup_mbuf(softc_t *, struct mbuf *);
1364 static int txintr_setup(softc_t *);
1365
1366 static intr_return_t bsd_interrupt(void *);
1367 # if DEVICE_POLLING
1368 static void bsd_poll(struct ifnet *, enum poll_cmd, int);
1369 # endif
1370 #endif /* BSD */
1371
1372 static int open_proto(softc_t *, struct config *);
1373 static int attach_stack(softc_t *, struct config *);
1374
1375 static int lmc_ioctl(softc_t *, u_long, void *);
1376 static void lmc_watchdog(softc_t *);
1377
1378 static void set_ready(softc_t *, int);
1379 static void reset_cntrs(softc_t *);
1380
1381 static void lmc_interrupt(void *, int, int);
1382 static void check_intr_status(softc_t *);
1383
1384 static int lmc_attach(softc_t *);
1385 static void lmc_detach(softc_t *);
1386
1387 static void tulip_loop(softc_t *, struct config *);
1388 static int tulip_attach(softc_t *);
1389 static void tulip_detach(void *);
1390
1391 static void print_driver_info(void);
1392
1393 static int nbsd_match(struct device *, cfdata_t, void *);
1394 static void nbsd_attach(struct device *, struct device *, void *);
1395 static int nbsd_detach(struct device *, int);
1396
1397 #endif /* KERNEL */
1398
1399 #endif /* IF_LMC_H */
NetBSD on the FriendlyARM MINI2440