sys/dev/pci/if_skreg.h

   1 /* $NetBSD: if_skreg.h,v 1.12 2008/04/28 20:23:55 martin Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2003 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  * POSSIBILITY OF SUCH DAMAGE.
  27  */
  28 /*      $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $      */
  29 /*      $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $       */
  30 /*      $OpenBSD: if_skreg.h,v 1.41 2006/11/23 21:56:32 kettenis Exp $  */
  31
  32 /*
  33  * Copyright (c) 1997, 1998, 1999, 2000
  34  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  * 1. Redistributions of source code must retain the above copyright
  40  *    notice, this list of conditions and the following disclaimer.
  41  * 2. Redistributions in binary form must reproduce the above copyright
  42  *    notice, this list of conditions and the following disclaimer in the
  43  *    documentation and/or other materials provided with the distribution.
  44  * 3. All advertising materials mentioning features or use of this software
  45  *    must display the following acknowledgement:
  46  *      This product includes software developed by Bill Paul.
  47  * 4. Neither the name of the author nor the names of any co-contributors
  48  *    may be used to endorse or promote products derived from this software
  49  *    without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  52  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  53  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  54  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  55  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  56  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  57  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  58  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  59  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  60  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  61  * THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $
  64  * $FreeBSD: /c/ncvs/src/sys/pci/xmaciireg.h,v 1.3 2000/04/22 02:16:37 wpaul Exp $
  65  */
  66
  67 /*
  68  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  69  *
  70  * Permission to use, copy, modify, and distribute this software for any
  71  * purpose with or without fee is hereby granted, provided that the above
  72  * copyright notice and this permission notice appear in all copies.
  73  *
  74  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  75  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  76  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  77  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  78  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  79  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  80  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  81  */
  82
  83 #ifndef _DEV_PCI_IF_SKREG_H_
  84 #define _DEV_PCI_IF_SKREG_H_
  85
  86 #include <net/if.h>
  87 #include <net/if_ether.h>
  88 #include <net/if_media.h>
  89
  90
  91 /*
  92  * GEnesis registers. The GEnesis chip has a 256-byte I/O window
  93  * but internally it has a 16K register space. This 16K space is
  94  * divided into 128-byte blocks. The first 128 bytes of the I/O
  95  * window represent the first block, which is permanently mapped
  96  * at the start of the window. The other 127 blocks can be mapped
  97  * to the second 128 bytes of the I/O window by setting the desired
  98  * block value in the RAP register in block 0. Not all of the 127
  99  * blocks are actually used. Most registers are 32 bits wide, but
 100  * there are a few 16-bit and 8-bit ones as well.
 101  */
 102
 103
 104 /* Start of remappable register window. */
 105 #define SK_WIN_BASE             0x0080
 106
 107 /* Size of a window */
 108 #define SK_WIN_LEN              0x80
 109
 110 #define SK_WIN_MASK             0x3F80
 111 #define SK_REG_MASK             0x7F
 112
 113 /* Compute the window of a given register (for the RAP register) */
 114 #define SK_WIN(reg)             (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
 115
 116 /* Compute the relative offset of a register within the window */
 117 #define SK_REG(reg)             ((reg) & SK_REG_MASK)
 118
 119 #define SK_PORT_A       0
 120 #define SK_PORT_B       1
 121
 122 /*
 123  * Compute offset of port-specific register. Since there are two
 124  * ports, there are two of some GEnesis modules (e.g. two sets of
 125  * DMA queues, two sets of FIFO control registers, etc...). Normally,
 126  * the block for port 0 is at offset 0x0 and the block for port 1 is
 127  * at offset 0x80 (i.e. the next page over). However for the transmit
 128  * BMUs and RAMbuffers, there are two blocks for each port: one for
 129  * the sync transmit queue and one for the async queue (which we don't
 130  * use). However instead of ordering them like this:
 131  * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
 132  * SysKonnect has instead ordered them like this:
 133  * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
 134  * This means that when referencing the TX BMU and RAMbuffer registers,
 135  * we have to double the block offset (0x80 * 2) in order to reach the
 136  * second queue. This prevents us from using the same formula
 137  * (sk_port * 0x80) to compute the offsets for all of the port-specific
 138  * blocks: we need an extra offset for the BMU and RAMbuffer registers.
 139  * The simplest thing is to provide an extra argument to these macros:
 140  * the 'skip' parameter. The 'skip' value is the number of extra pages
 141  * for skip when computing the port0/port1 offsets. For most registers,
 142  * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
 143  */
 144 #define SK_IF_READ_4(sc_if, skip, reg)          \
 145         sk_win_read_4(sc_if->sk_softc, reg +    \
 146         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
 147 #define SK_IF_READ_2(sc_if, skip, reg)          \
 148         sk_win_read_2(sc_if->sk_softc, reg +    \
 149         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
 150 #define SK_IF_READ_1(sc_if, skip, reg)          \
 151         sk_win_read_1(sc_if->sk_softc, reg +    \
 152         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
 153
 154 #define SK_IF_WRITE_4(sc_if, skip, reg, val)    \
 155         sk_win_write_4(sc_if->sk_softc,         \
 156         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
 157 #define SK_IF_WRITE_2(sc_if, skip, reg, val)    \
 158         sk_win_write_2(sc_if->sk_softc,         \
 159         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
 160 #define SK_IF_WRITE_1(sc_if, skip, reg, val)    \
 161         sk_win_write_1(sc_if->sk_softc,         \
 162         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
 163
 164 /* Block 0 registers, permanently mapped at iobase. */
 165 #define SK_RAP          0x0000
 166 #define SK_CSR          0x0004
 167 #define SK_LED          0x0006
 168 /* XXX 0x0007 B0_POWER_CTRL */
 169 #define SK_ISR          0x0008  /* interrupt source */
 170 #define SK_IMR          0x000C  /* interrupt mask */
 171 #define SK_IESR         0x0010  /* interrupt hardware error source */
 172 #define SK_IEMR         0x0014  /* interrupt hardware error mask */
 173 #define SK_ISSR         0x0018  /* special interrupt source */
 174 #define SK_Y2_ISSR2     0x001C
 175 #define SK_Y2_ISSR3     0x0020
 176 #define SK_Y2_EISR      0x0024
 177 #define SK_Y2_LISR      0x0028
 178 #define SK_Y2_ICR       0x002C
 179 #define SK_XM_IMR0      0x0020
 180 #define SK_XM_ISR0      0x0028
 181 #define SK_XM_PHYADDR0  0x0030
 182 #define SK_XM_PHYDATA0  0x0034
 183 #define SK_XM_IMR1      0x0040
 184 #define SK_XM_ISR1      0x0048
 185 #define SK_XM_PHYADDR1  0x0050
 186 #define SK_XM_PHYDATA1  0x0054
 187 #define SK_BMU_RX_CSR0  0x0060
 188 #define SK_BMU_RX_CSR1  0x0064
 189 #define SK_BMU_TXS_CSR0 0x0068
 190 #define SK_BMU_TXA_CSR0 0x006C
 191 #define SK_BMU_TXS_CSR1 0x0070
 192 #define SK_BMU_TXA_CSR1 0x0074
 193
 194 /* SK_CSR register */
 195 #define SK_CSR_SW_RESET                 0x0001
 196 #define SK_CSR_SW_UNRESET               0x0002
 197 #define SK_CSR_MASTER_RESET             0x0004
 198 #define SK_CSR_MASTER_UNRESET           0x0008
 199 #define SK_CSR_MASTER_STOP              0x0010
 200 #define SK_CSR_MASTER_DONE              0x0020
 201 #define SK_CSR_SW_IRQ_CLEAR             0x0040
 202 #define SK_CSR_SW_IRQ_SET               0x0080
 203 #define SK_CSR_SLOTSIZE                 0x0100 /* 1 == 64 bits, 0 == 32 */
 204 #define SK_CSR_BUSCLOCK                 0x0200 /* 1 == 33/66 MHz, = 33 */
 205 #define SK_CSR_ASF_OFF                  0x1000
 206 #define SK_CSR_ASF_ON                   0x2000
 207 #define SK_CSR_WOL_OFF                  __BIT(14)
 208 #define SK_CSR_WOL_ON                   __BIT(15)
 209
 210 /* SK_LED register */
 211 #define SK_LED_GREEN_OFF                0x01
 212 #define SK_LED_GREEN_ON                 0x02
 213
 214 /* SK_ISR register */
 215 #define SK_ISR_TX2_AS_CHECK             0x00000001
 216 #define SK_ISR_TX2_AS_EOF               0x00000002
 217 #define SK_ISR_TX2_AS_EOB               0x00000004
 218 #define SK_ISR_TX2_S_CHECK              0x00000008
 219 #define SK_ISR_TX2_S_EOF                0x00000010
 220 #define SK_ISR_TX2_S_EOB                0x00000020
 221 #define SK_ISR_TX1_AS_CHECK             0x00000040
 222 #define SK_ISR_TX1_AS_EOF               0x00000080
 223 #define SK_ISR_TX1_AS_EOB               0x00000100
 224 #define SK_ISR_TX1_S_CHECK              0x00000200
 225 #define SK_ISR_TX1_S_EOF                0x00000400
 226 #define SK_ISR_TX1_S_EOB                0x00000800
 227 #define SK_ISR_RX2_CHECK                0x00001000
 228 #define SK_ISR_RX2_EOF                  0x00002000
 229 #define SK_ISR_RX2_EOB                  0x00004000
 230 #define SK_ISR_RX1_CHECK                0x00008000
 231 #define SK_ISR_RX1_EOF                  0x00010000
 232 #define SK_ISR_RX1_EOB                  0x00020000
 233 #define SK_ISR_LINK2_OFLOW              0x00040000
 234 #define SK_ISR_MAC2                     0x00080000
 235 #define SK_ISR_LINK1_OFLOW              0x00100000
 236 #define SK_ISR_MAC1                     0x00200000
 237 #define SK_ISR_TIMER                    0x00400000
 238 #define SK_ISR_EXTERNAL_REG             0x00800000
 239 #define SK_ISR_SW                       0x01000000
 240 #define SK_ISR_I2C_RDY                  0x02000000
 241 #define SK_ISR_TX2_TIMEO                0x04000000
 242 #define SK_ISR_TX1_TIMEO                0x08000000
 243 #define SK_ISR_RX2_TIMEO                0x10000000
 244 #define SK_ISR_RX1_TIMEO                0x20000000
 245 #define SK_ISR_RSVD                     0x40000000
 246 #define SK_ISR_HWERR                    0x80000000
 247
 248 /* SK_IMR register */
 249 #define SK_IMR_TX2_AS_CHECK             0x00000001
 250 #define SK_IMR_TX2_AS_EOF               0x00000002
 251 #define SK_IMR_TX2_AS_EOB               0x00000004
 252 #define SK_IMR_TX2_S_CHECK              0x00000008
 253 #define SK_IMR_TX2_S_EOF                0x00000010
 254 #define SK_IMR_TX2_S_EOB                0x00000020
 255 #define SK_IMR_TX1_AS_CHECK             0x00000040
 256 #define SK_IMR_TX1_AS_EOF               0x00000080
 257 #define SK_IMR_TX1_AS_EOB               0x00000100
 258 #define SK_IMR_TX1_S_CHECK              0x00000200
 259 #define SK_IMR_TX1_S_EOF                0x00000400
 260 #define SK_IMR_TX1_S_EOB                0x00000800
 261 #define SK_IMR_RX2_CHECK                0x00001000
 262 #define SK_IMR_RX2_EOF                  0x00002000
 263 #define SK_IMR_RX2_EOB                  0x00004000
 264 #define SK_IMR_RX1_CHECK                0x00008000
 265 #define SK_IMR_RX1_EOF                  0x00010000
 266 #define SK_IMR_RX1_EOB                  0x00020000
 267 #define SK_IMR_LINK2_OFLOW              0x00040000
 268 #define SK_IMR_MAC2                     0x00080000
 269 #define SK_IMR_LINK1_OFLOW              0x00100000
 270 #define SK_IMR_MAC1                     0x00200000
 271 #define SK_IMR_TIMER                    0x00400000
 272 #define SK_IMR_EXTERNAL_REG             0x00800000
 273 #define SK_IMR_SW                       0x01000000
 274 #define SK_IMR_I2C_RDY                  0x02000000
 275 #define SK_IMR_TX2_TIMEO                0x04000000
 276 #define SK_IMR_TX1_TIMEO                0x08000000
 277 #define SK_IMR_RX2_TIMEO                0x10000000
 278 #define SK_IMR_RX1_TIMEO                0x20000000
 279 #define SK_IMR_RSVD                     0x40000000
 280 #define SK_IMR_HWERR                    0x80000000
 281
 282 #define SK_INTRS1       \
 283         (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
 284
 285 #define SK_INTRS2       \
 286         (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
 287
 288 #define SK_Y2_IMR_TX1_AS_CHECK          0x00000001
 289 #define SK_Y2_IMR_TX1_S_CHECK           0x00000002
 290 #define SK_Y2_IMR_RX1_CHECK             0x00000004
 291 #define SK_Y2_IMR_MAC1                  0x00000008
 292 #define SK_Y2_IMR_PHY1                  0x00000010
 293 #define SK_Y2_IMR_TX2_AS_CHECK          0x00000100
 294 #define SK_Y2_IMR_TX2_S_CHECK           0x00000200
 295 #define SK_Y2_IMR_RX2_CHECK             0x00000400
 296 #define SK_Y2_IMR_MAC2                  0x00000800
 297 #define SK_Y2_IMR_PHY2                  0x00001000
 298 #define SK_Y2_IMR_TIMER                 0x01000000
 299 #define SK_Y2_IMR_SW                    0x02000000
 300 #define SK_Y2_IMR_ASF                   0x20000000
 301 #define SK_Y2_IMR_BMU                   0x40000000
 302 #define SK_Y2_IMR_HWERR                 0x80000000
 303
 304 #define SK_Y2_INTRS1    \
 305         (SK_Y2_IMR_RX1_CHECK|SK_Y2_IMR_TX1_AS_CHECK \
 306         |SK_Y2_IMR_MAC1|SK_Y2_IMR_PHY1)
 307
 308 #define SK_Y2_INTRS2    \
 309         (SK_Y2_IMR_RX2_CHECK|SK_Y2_IMR_TX2_AS_CHECK \
 310         |SK_Y2_IMR_MAC2|SK_Y2_IMR_PHY2)
 311
 312 /* SK_IESR register */
 313 #define SK_IESR_PAR_RX2                 0x00000001
 314 #define SK_IESR_PAR_RX1                 0x00000002
 315 #define SK_IESR_PAR_MAC2                0x00000004
 316 #define SK_IESR_PAR_MAC1                0x00000008
 317 #define SK_IESR_PAR_WR_RAM              0x00000010
 318 #define SK_IESR_PAR_RD_RAM              0x00000020
 319 #define SK_IESR_NO_TSTAMP_MAC2          0x00000040
 320 #define SK_IESR_NO_TSTAMO_MAC1          0x00000080
 321 #define SK_IESR_NO_STS_MAC2             0x00000100
 322 #define SK_IESR_NO_STS_MAC1             0x00000200
 323 #define SK_IESR_IRQ_STS                 0x00000400
 324 #define SK_IESR_MASTERERR               0x00000800
 325
 326 /* SK_IEMR register */
 327 #define SK_IEMR_PAR_RX2                 0x00000001
 328 #define SK_IEMR_PAR_RX1                 0x00000002
 329 #define SK_IEMR_PAR_MAC2                0x00000004
 330 #define SK_IEMR_PAR_MAC1                0x00000008
 331 #define SK_IEMR_PAR_WR_RAM              0x00000010
 332 #define SK_IEMR_PAR_RD_RAM              0x00000020
 333 #define SK_IEMR_NO_TSTAMP_MAC2          0x00000040
 334 #define SK_IEMR_NO_TSTAMO_MAC1          0x00000080
 335 #define SK_IEMR_NO_STS_MAC2             0x00000100
 336 #define SK_IEMR_NO_STS_MAC1             0x00000200
 337 #define SK_IEMR_IRQ_STS                 0x00000400
 338 #define SK_IEMR_MASTERERR               0x00000800
 339
 340 /* Block 2 */
 341 #define SK_MAC0_0       0x0100
 342 #define SK_MAC0_1       0x0104
 343 #define SK_MAC1_0       0x0108
 344 #define SK_MAC1_1       0x010C
 345 #define SK_MAC2_0       0x0110
 346 #define SK_MAC2_1       0x0114
 347 #define SK_CONNTYPE     0x0118
 348 #define SK_PMDTYPE      0x0119
 349 #define SK_CONFIG       0x011A
 350 #define SK_CHIPVER      0x011B
 351 #define SK_EPROM0       0x011C
 352 #define SK_EPROM1       0x011D          /* yukon/genesis */
 353 #define SK_Y2_CLKGATE   0x011D          /* yukon 2 */
 354 #define SK_EPROM2       0x011E          /* yukon/genesis */
 355 #define SK_Y2_HWRES     0x011E          /* yukon 2 */
 356 #define SK_EPROM3       0x011F
 357 #define SK_EP_ADDR      0x0120
 358 #define SK_EP_DATA      0x0124
 359 #define SK_EP_LOADCTL   0x0128
 360 #define SK_EP_LOADTST   0x0129
 361 #define SK_TIMERINIT    0x0130
 362 #define SK_TIMER        0x0134
 363 #define SK_TIMERCTL     0x0138
 364 #define SK_TIMERTST     0x0139
 365 #define SK_IMTIMERINIT  0x0140
 366 #define SK_IMTIMER      0x0144
 367 #define SK_IMTIMERCTL   0x0148
 368 #define SK_IMTIMERTST   0x0149
 369 #define SK_IMMR         0x014C
 370 #define SK_IHWEMR       0x0150
 371 #define SK_TESTCTL1     0x0158
 372 #define SK_TESTCTL2     0x0159
 373 #define SK_GPIO         0x015C
 374 #define SK_I2CHWCTL     0x0160
 375 #define SK_I2CHWDATA    0x0164
 376 #define SK_I2CHWIRQ     0x0168
 377 #define SK_I2CSW        0x016C
 378 #define SK_BLNKINIT     0x0170
 379 #define SK_BLNKCOUNT    0x0174
 380 #define SK_BLNKCTL      0x0178
 381 #define SK_BLNKSTS      0x0179
 382 #define SK_BLNKTST      0x017A
 383
 384 /* Values for SK_CHIPVER */
 385 #define SK_GENESIS              0x0A
 386 #define SK_YUKON                0xB0
 387 #define SK_YUKON_LITE           0xB1
 388 #define SK_YUKON_LP             0xB2
 389 #define SK_YUKON_XL             0xB3
 390 #define SK_YUKON_EC_U           0xB4
 391 #define SK_YUKON_EC             0xB6
 392 #define SK_YUKON_FE             0xB7
 393 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
 394
 395 #define SK_IS_GENESIS(sc) \
 396     ((sc)->sk_type == SK_GENESIS)
 397 #define SK_IS_YUKON(sc) \
 398     ((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP)
 399 #define SK_IS_YUKON2(sc) \
 400     ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE)
 401
 402 /* Known revisions in SK_CONFIG */
 403 #define SK_YUKON_LITE_REV_A0    0x0 /* invented, see test in skc_attach */
 404 #define SK_YUKON_LITE_REV_A1    0x3
 405 #define SK_YUKON_LITE_REV_A3    0x7
 406
 407 #define SK_YUKON_XL_REV_A0      0x0
 408 #define SK_YUKON_XL_REV_A1      0x1
 409 #define SK_YUKON_XL_REV_A2      0x2
 410 #define SK_YUKON_XL_REV_A3      0x3
 411
 412 #define SK_YUKON_EC_REV_A1      0x0
 413 #define SK_YUKON_EC_REV_A2      0x1
 414 #define SK_YUKON_EC_REV_A3      0x2
 415
 416 #define SK_YUKON_EC_U_REV_A0    0x1
 417 #define SK_YUKON_EC_U_REV_A1    0x2
 418 #define SK_YUKON_EC_U_REV_B0    0x3
 419
 420 #define SK_YUKON_FE_REV_A1      0x1
 421 #define SK_YUKON_FE_REV_A2      0x3
 422
 423 /* Workaround */
 424 #define SK_WA_43_418    0x01
 425 #define SK_WA_4109      0x02
 426
 427 #define SK_IMCTL_IRQ_CLEAR      0x01
 428 #define SK_IMCTL_STOP           0x02
 429 #define SK_IMCTL_START          0x04
 430
 431 /* Number of ticks per usec for interrupt moderation */
 432 #define SK_IMTIMER_TICKS_GENESIS        53
 433 #define SK_IMTIMER_TICKS_YUKON          156
 434 #define SK_IMTIMER_TICKS_YUKON_EC       125
 435 #define SK_IMTIMER_TICKS_YUKON_FE       100
 436 #define SK_IMTIMER_TICKS_YUKON_XL       156
 437 #define SK_IM_USECS(x)          ((x) * imtimer_ticks)
 438
 439 #define SK_IM_MIN       0
 440 #define SK_IM_DEFAULT   1000
 441 #define SK_IM_MAX       10000
 442 /*
 443  * The SK_EPROM0 register contains a byte that describes the
 444  * amount of SRAM mounted on the NIC. The value also tells if
 445  * the chips are 64K or 128K. This affects the RAMbuffer address
 446  * offset that we need to use.
 447  */
 448 #define SK_RAMSIZE_512K_64      0x1
 449 #define SK_RAMSIZE_1024K_128    0x2
 450 #define SK_RAMSIZE_1024K_64     0x3
 451 #define SK_RAMSIZE_2048K_128    0x4
 452
 453 #define SK_RBOFF_0              0x0
 454 #define SK_RBOFF_80000          0x80000
 455
 456 /*
 457  * SK_EEPROM1 contains the PHY type, which may be XMAC for
 458  * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
 459  * PHY.
 460  */
 461 #define SK_PHYTYPE_XMAC         0       /* integeated XMAC II PHY */
 462 #define SK_PHYTYPE_BCOM         1       /* Broadcom BCM5400 */
 463 #define SK_PHYTYPE_LONE         2       /* Level One LXT1000 */
 464 #define SK_PHYTYPE_NAT          3       /* National DP83891 */
 465 #define SK_PHYTYPE_MARV_COPPER  4       /* Marvell 88E1011S */
 466 #define SK_PHYTYPE_MARV_FIBER   5       /* Marvell 88E1011S (fiber) */
 467
 468 /*
 469  * PHY addresses.
 470  */
 471 #define SK_PHYADDR_XMAC         0x0
 472 #define SK_PHYADDR_BCOM         0x1
 473 #define SK_PHYADDR_LONE         0x3
 474 #define SK_PHYADDR_NAT          0x0
 475 #define SK_PHYADDR_MARV         0x0
 476
 477 #define SK_CONFIG_SINGLEMAC     0x01
 478 #define SK_CONFIG_DIS_DSL_CLK   0x02
 479
 480 #define SK_PMD_1000BASETX_ALT   0x31
 481 #define SK_PMD_1000BASECX       0x43
 482 #define SK_PMD_1000BASELX       0x4C
 483 #define SK_PMD_1000BASESX       0x53
 484 #define SK_PMD_1000BASETX       0x54
 485
 486 /* GPIO bits */
 487 #define SK_GPIO_DAT0            0x00000001
 488 #define SK_GPIO_DAT1            0x00000002
 489 #define SK_GPIO_DAT2            0x00000004
 490 #define SK_GPIO_DAT3            0x00000008
 491 #define SK_GPIO_DAT4            0x00000010
 492 #define SK_GPIO_DAT5            0x00000020
 493 #define SK_GPIO_DAT6            0x00000040
 494 #define SK_GPIO_DAT7            0x00000080
 495 #define SK_GPIO_DAT8            0x00000100
 496 #define SK_GPIO_DAT9            0x00000200
 497 #define SK_GPIO_DIR0            0x00010000
 498 #define SK_GPIO_DIR1            0x00020000
 499 #define SK_GPIO_DIR2            0x00040000
 500 #define SK_GPIO_DIR3            0x00080000
 501 #define SK_GPIO_DIR4            0x00100000
 502 #define SK_GPIO_DIR5            0x00200000
 503 #define SK_GPIO_DIR6            0x00400000
 504 #define SK_GPIO_DIR7            0x00800000
 505 #define SK_GPIO_DIR8            0x01000000
 506 #define SK_GPIO_DIR9           0x02000000
 507
 508 #define SK_Y2_CLKGATE_LINK2_INACTIVE    0x80    /* port 2 inactive */
 509 #define SK_Y2_CLKGATE_LINK2_GATE_DIS    0x40    /* disable clock gate, 2 */
 510 #define SK_Y2_CLKGATE_LINK2_CORE_DIS    0x20    /* disable core clock, 2 */
 511 #define SK_Y2_CLKGATE_LINK2_PCI_DIS     0x10    /* disable pci clock, 2 */
 512 #define SK_Y2_CLKGATE_LINK1_INACTIVE    0x08    /* port 1 inactive */
 513 #define SK_Y2_CLKGATE_LINK1_GATE_DIS    0x04    /* disable clock gate, 1 */
 514 #define SK_Y2_CLKGATE_LINK1_CORE_DIS    0x02    /* disable core clock, 1 */
 515 #define SK_Y2_CLKGATE_LINK1_PCI_DIS     0x01    /* disable pci clock, 1 */
 516
 517 #define SK_Y2_HWRES_LINK_1      0x01
 518 #define SK_Y2_HWRES_LINK_2      0x02
 519 #define SK_Y2_HWRES_LINK_MASK   (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
 520 #define SK_Y2_HWRES_LINK_DUAL   (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
 521
 522 /* Block 3 Ram interface and MAC arbiter registers */
 523 #define SK_RAMADDR      0x0180
 524 #define SK_RAMDATA0     0x0184
 525 #define SK_RAMDATA1     0x0188
 526 #define SK_TO0          0x0190
 527 #define SK_TO1          0x0191
 528 #define SK_TO2          0x0192
 529 #define SK_TO3          0x0193
 530 #define SK_TO4          0x0194
 531 #define SK_TO5          0x0195
 532 #define SK_TO6          0x0196
 533 #define SK_TO7          0x0197
 534 #define SK_TO8          0x0198
 535 #define SK_TO9          0x0199
 536 #define SK_TO10         0x019A
 537 #define SK_TO11         0x019B
 538 #define SK_RITIMEO_TMR  0x019C
 539 #define SK_RAMCTL       0x01A0
 540 #define SK_RITIMER_TST  0x01A2
 541
 542 #define SK_RAMCTL_RESET         0x0001
 543 #define SK_RAMCTL_UNRESET       0x0002
 544 #define SK_RAMCTL_CLR_IRQ_WPAR  0x0100
 545 #define SK_RAMCTL_CLR_IRQ_RPAR  0x0200
 546
 547 /* Mac arbiter registers */
 548 #define SK_MINIT_RX1    0x01B0
 549 #define SK_MINIT_RX2    0x01B1
 550 #define SK_MINIT_TX1    0x01B2
 551 #define SK_MINIT_TX2    0x01B3
 552 #define SK_MTIMEO_RX1   0x01B4
 553 #define SK_MTIMEO_RX2   0x01B5
 554 #define SK_MTIMEO_TX1   0x01B6
 555 #define SK_MTIEMO_TX2   0x01B7
 556 #define SK_MACARB_CTL   0x01B8
 557 #define SK_MTIMER_TST   0x01BA
 558 #define SK_RCINIT_RX1   0x01C0
 559 #define SK_RCINIT_RX2   0x01C1
 560 #define SK_RCINIT_TX1   0x01C2
 561 #define SK_RCINIT_TX2   0x01C3
 562 #define SK_RCTIMEO_RX1  0x01C4
 563 #define SK_RCTIMEO_RX2  0x01C5
 564 #define SK_RCTIMEO_TX1  0x01C6
 565 #define SK_RCTIMEO_TX2  0x01C7
 566 #define SK_RECOVERY_CTL 0x01C8
 567 #define SK_RCTIMER_TST  0x01CA
 568
 569 /* Packet arbiter registers */
 570 #define SK_RXPA1_TINIT  0x01D0
 571 #define SK_RXPA2_TINIT  0x01D4
 572 #define SK_TXPA1_TINIT  0x01D8
 573 #define SK_TXPA2_TINIT  0x01DC
 574 #define SK_RXPA1_TIMEO  0x01E0
 575 #define SK_RXPA2_TIMEO  0x01E4
 576 #define SK_TXPA1_TIMEO  0x01E8
 577 #define SK_TXPA2_TIMEO  0x01EC
 578 #define SK_PKTARB_CTL   0x01F0
 579 #define SK_PKTATB_TST   0x01F2
 580
 581 #define SK_PKTARB_TIMEOUT       0x2000
 582
 583 #define SK_PKTARBCTL_RESET              0x0001
 584 #define SK_PKTARBCTL_UNRESET            0x0002
 585 #define SK_PKTARBCTL_RXTO1_OFF          0x0004
 586 #define SK_PKTARBCTL_RXTO1_ON           0x0008
 587 #define SK_PKTARBCTL_RXTO2_OFF          0x0010
 588 #define SK_PKTARBCTL_RXTO2_ON           0x0020
 589 #define SK_PKTARBCTL_TXTO1_OFF          0x0040
 590 #define SK_PKTARBCTL_TXTO1_ON           0x0080
 591 #define SK_PKTARBCTL_TXTO2_OFF          0x0100
 592 #define SK_PKTARBCTL_TXTO2_ON           0x0200
 593 #define SK_PKTARBCTL_CLR_IRQ_RXTO1      0x0400
 594 #define SK_PKTARBCTL_CLR_IRQ_RXTO2      0x0800
 595 #define SK_PKTARBCTL_CLR_IRQ_TXTO1      0x1000
 596 #define SK_PKTARBCTL_CLR_IRQ_TXTO2      0x2000
 597
 598 #define SK_MINIT_XMAC_B2        54
 599 #define SK_MINIT_XMAC_C1        63
 600
 601 #define SK_MACARBCTL_RESET      0x0001
 602 #define SK_MACARBCTL_UNRESET    0x0002
 603 #define SK_MACARBCTL_FASTOE_OFF 0x0004
 604 #define SK_MACARBCRL_FASTOE_ON  0x0008
 605
 606 #define SK_RCINIT_XMAC_B2       54
 607 #define SK_RCINIT_XMAC_C1       0
 608
 609 #define SK_RECOVERYCTL_RX1_OFF  0x0001
 610 #define SK_RECOVERYCTL_RX1_ON   0x0002
 611 #define SK_RECOVERYCTL_RX2_OFF  0x0004
 612 #define SK_RECOVERYCTL_RX2_ON   0x0008
 613 #define SK_RECOVERYCTL_TX1_OFF  0x0010
 614 #define SK_RECOVERYCTL_TX1_ON   0x0020
 615 #define SK_RECOVERYCTL_TX2_OFF  0x0040
 616 #define SK_RECOVERYCTL_TX2_ON   0x0080
 617
 618 #define SK_RECOVERY_XMAC_B2                             \
 619         (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON|   \
 620         SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
 621
 622 #define SK_RECOVERY_XMAC_C1                             \
 623         (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
 624         SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
 625
 626 /* Block 4 -- TX Arbiter MAC 1 */
 627 #define SK_TXAR1_TIMERINIT      0x0200
 628 #define SK_TXAR1_TIMERVAL       0x0204
 629 #define SK_TXAR1_LIMITINIT      0x0208
 630 #define SK_TXAR1_LIMITCNT       0x020C
 631 #define SK_TXAR1_COUNTERCTL     0x0210
 632 #define SK_TXAR1_COUNTERTST     0x0212
 633 #define SK_TXAR1_COUNTERSTS     0x0212
 634
 635 /* Block 5 -- TX Arbiter MAC 2 */
 636 #define SK_TXAR2_TIMERINIT      0x0280
 637 #define SK_TXAR2_TIMERVAL       0x0284
 638 #define SK_TXAR2_LIMITINIT      0x0288
 639 #define SK_TXAR2_LIMITCNT       0x028C
 640 #define SK_TXAR2_COUNTERCTL     0x0290
 641 #define SK_TXAR2_COUNTERTST     0x0291
 642 #define SK_TXAR2_COUNTERSTS     0x0292
 643
 644 #define SK_TXARCTL_OFF          0x01
 645 #define SK_TXARCTL_ON           0x02
 646 #define SK_TXARCTL_RATECTL_OFF  0x04
 647 #define SK_TXARCTL_RATECTL_ON   0x08
 648 #define SK_TXARCTL_ALLOC_OFF    0x10
 649 #define SK_TXARCTL_ALLOC_ON     0x20
 650 #define SK_TXARCTL_FSYNC_OFF    0x40
 651 #define SK_TXARCTL_FSYNC_ON     0x80
 652
 653 /* Block 6 -- External registers */
 654 #define SK_EXTREG_BASE  0x300
 655 #define SK_EXTREG_END   0x37C
 656
 657 /* Block 7 -- PCI config registers */
 658 #define SK_PCI_BASE     0x0380
 659 #define SK_PCI_END      0x03FC
 660
 661 /* Compute offset of mirrored PCI register */
 662 #define SK_PCI_REG(reg)         ((reg) + SK_PCI_BASE)
 663
 664 /* Block 8 -- RX queue 1 */
 665 #define SK_RXQ1_BUFCNT          0x0400
 666 #define SK_RXQ1_BUFCTL          0x0402
 667 #define SK_RXQ1_NEXTDESC        0x0404
 668 #define SK_RXQ1_RXBUF_LO        0x0408
 669 #define SK_RXQ1_RXBUF_HI        0x040C
 670 #define SK_RXQ1_RXSTAT          0x0410
 671 #define SK_RXQ1_TIMESTAMP       0x0414
 672 #define SK_RXQ1_CSUM1           0x0418
 673 #define SK_RXQ1_CSUM2           0x041A
 674 #define SK_RXQ1_CSUM1_START     0x041C
 675 #define SK_RXQ1_CSUM2_START     0x041E
 676 #define SK_RXQ1_CURADDR_LO      0x0420
 677 #define SK_RXQ1_CURADDR_HI      0x0424
 678 #define SK_RXQ1_CURCNT_LO       0x0428
 679 #define SK_RXQ1_CURCNT_HI       0x042C
 680 #define SK_RXQ1_CURBYTES        0x0430
 681 #define SK_RXQ1_BMU_CSR         0x0434
 682 #define SK_RXQ1_WATERMARK       0x0438
 683 #define SK_RXQ1_FLAG            0x043A
 684 #define SK_RXQ1_TEST1           0x043C
 685 #define SK_RXQ1_TEST2           0x0440
 686 #define SK_RXQ1_TEST3           0x0444
 687 /* yukon-2 only */
 688 #define SK_RXQ1_Y2_WM           0x0440
 689 #define SK_RXQ1_Y2_AL           0x0442
 690 #define SK_RXQ1_Y2_RSP          0x0444
 691 #define SK_RXQ1_Y2_RSL          0x0446
 692 #define SK_RXQ1_Y2_RP           0x0448
 693 #define SK_RXQ1_Y2_RL           0x044A
 694 #define SK_RXQ1_Y2_WP           0x044C
 695 #define SK_RXQ1_Y2_WSP          0x044D
 696 #define SK_RXQ1_Y2_WL           0x044E
 697 #define SK_RXQ1_Y2_WSL          0x044F
 698 /* yukon-2 only (prefetch unit) */
 699 #define SK_RXQ1_Y2_PREF_CSR     0x0450
 700 #define SK_RXQ1_Y2_PREF_LIDX    0x0454
 701 #define SK_RXQ1_Y2_PREF_ADDRLO  0x0458
 702 #define SK_RXQ1_Y2_PREF_ADDRHI  0x045C
 703 #define SK_RXQ1_Y2_PREF_GETIDX  0x0460
 704 #define SK_RXQ1_Y2_PREF_PUTIDX  0x0464
 705 #define SK_RXQ1_Y2_PREF_FIFOWP  0x0470
 706 #define SK_RXQ1_Y2_PREF_FIFORP  0x0474
 707 #define SK_RXQ1_Y2_PREF_FIFOWM  0x0478
 708 #define SK_RXQ1_Y2_PREF_FIFOLV  0x047C
 709
 710 /* Block 9 -- RX queue 2 */
 711 #define SK_RXQ2_BUFCNT          0x0480
 712 #define SK_RXQ2_BUFCTL          0x0482
 713 #define SK_RXQ2_NEXTDESC        0x0484
 714 #define SK_RXQ2_RXBUF_LO        0x0488
 715 #define SK_RXQ2_RXBUF_HI        0x048C
 716 #define SK_RXQ2_RXSTAT          0x0490
 717 #define SK_RXQ2_TIMESTAMP       0x0494
 718 #define SK_RXQ2_CSUM1           0x0498
 719 #define SK_RXQ2_CSUM2           0x049A
 720 #define SK_RXQ2_CSUM1_START     0x049C
 721 #define SK_RXQ2_CSUM2_START     0x049E
 722 #define SK_RXQ2_CURADDR_LO      0x04A0
 723 #define SK_RXQ2_CURADDR_HI      0x04A4
 724 #define SK_RXQ2_CURCNT_LO       0x04A8
 725 #define SK_RXQ2_CURCNT_HI       0x04AC
 726 #define SK_RXQ2_CURBYTES        0x04B0
 727 #define SK_RXQ2_BMU_CSR         0x04B4
 728 #define SK_RXQ2_WATERMARK       0x04B8
 729 #define SK_RXQ2_FLAG            0x04BA
 730 #define SK_RXQ2_TEST1           0x04BC
 731 #define SK_RXQ2_TEST2           0x04C0
 732 #define SK_RXQ2_TEST3           0x04C4
 733 /* yukon-2 only */
 734 #define SK_RXQ2_Y2_WM           0x04C0
 735 #define SK_RXQ2_Y2_AL           0x04C2
 736 #define SK_RXQ2_Y2_RSP          0x04C4
 737 #define SK_RXQ2_Y2_RSL          0x04C6
 738 #define SK_RXQ2_Y2_RP           0x04C8
 739 #define SK_RXQ2_Y2_RL           0x04CA
 740 #define SK_RXQ2_Y2_WP           0x04CC
 741 #define SK_RXQ2_Y2_WSP          0x04CD
 742 #define SK_RXQ2_Y2_WL           0x04CE
 743 #define SK_RXQ2_Y2_WSL          0x04CF
 744 /* yukon-2 only (prefetch unit) */
 745 #define SK_RXQ2_Y2_PREF_CSR     0x04D0
 746 #define SK_RXQ2_Y2_PREF_LIDX    0x04D4
 747 #define SK_RXQ2_Y2_PREF_ADDRLO  0x04D8
 748 #define SK_RXQ2_Y2_PREF_ADDRHI  0x04DC
 749 #define SK_RXQ2_Y2_PREF_GETIDX  0x04E0
 750 #define SK_RXQ2_Y2_PREF_PUTIDX  0x04E4
 751 #define SK_RXQ2_Y2_PREF_FIFOWP  0x04F0
 752 #define SK_RXQ2_Y2_PREF_FIFORP  0x04F4
 753 #define SK_RXQ2_Y2_PREF_FIFOWM  0x04F8
 754 #define SK_RXQ2_Y2_PREF_FIFOLV  0x04FC
 755
 756 #define SK_RXBMU_CLR_IRQ_ERR            0x00000001
 757 #define SK_RXBMU_CLR_IRQ_EOF            0x00000002
 758 #define SK_RXBMU_CLR_IRQ_EOB            0x00000004
 759 #define SK_RXBMU_CLR_IRQ_PAR            0x00000008
 760 #define SK_RXBMU_RX_START               0x00000010
 761 #define SK_RXBMU_RX_STOP                0x00000020
 762 #define SK_RXBMU_POLL_OFF               0x00000040
 763 #define SK_RXBMU_POLL_ON                0x00000080
 764 #define SK_RXBMU_TRANSFER_SM_RESET      0x00000100
 765 #define SK_RXBMU_TRANSFER_SM_UNRESET    0x00000200
 766 #define SK_RXBMU_DESCWR_SM_RESET        0x00000400
 767 #define SK_RXBMU_DESCWR_SM_UNRESET      0x00000800
 768 #define SK_RXBMU_DESCRD_SM_RESET        0x00001000
 769 #define SK_RXBMU_DESCRD_SM_UNRESET      0x00002000
 770 #define SK_RXBMU_SUPERVISOR_SM_RESET    0x00004000
 771 #define SK_RXBMU_SUPERVISOR_SM_UNRESET  0x00008000
 772 #define SK_RXBMU_PFI_SM_RESET           0x00010000
 773 #define SK_RXBMU_PFI_SM_UNRESET         0x00020000
 774 #define SK_RXBMU_FIFO_RESET             0x00040000
 775 #define SK_RXBMU_FIFO_UNRESET           0x00080000
 776 #define SK_RXBMU_DESC_RESET             0x00100000
 777 #define SK_RXBMU_DESC_UNRESET           0x00200000
 778 #define SK_RXBMU_SUPERVISOR_IDLE        0x01000000
 779
 780 #define SK_RXBMU_ONLINE         \
 781         (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET|       \
 782         SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET|      \
 783         SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET|                  \
 784         SK_RXBMU_DESC_UNRESET)
 785
 786 #define SK_RXBMU_OFFLINE                \
 787         (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET|   \
 788         SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET|  \
 789         SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET|              \
 790         SK_RXBMU_DESC_RESET)
 791
 792 /* Block 12 -- TX sync queue 1 */
 793 #define SK_TXQS1_BUFCNT         0x0600
 794 #define SK_TXQS1_BUFCTL         0x0602
 795 #define SK_TXQS1_NEXTDESC       0x0604
 796 #define SK_TXQS1_RXBUF_LO       0x0608
 797 #define SK_TXQS1_RXBUF_HI       0x060C
 798 #define SK_TXQS1_RXSTAT         0x0610
 799 #define SK_TXQS1_CSUM_STARTVAL  0x0614
 800 #define SK_TXQS1_CSUM_STARTPOS  0x0618
 801 #define SK_TXQS1_CSUM_WRITEPOS  0x061A
 802 #define SK_TXQS1_CURADDR_LO     0x0620
 803 #define SK_TXQS1_CURADDR_HI     0x0624
 804 #define SK_TXQS1_CURCNT_LO      0x0628
 805 #define SK_TXQS1_CURCNT_HI      0x062C
 806 #define SK_TXQS1_CURBYTES       0x0630
 807 #define SK_TXQS1_BMU_CSR        0x0634
 808 #define SK_TXQS1_WATERMARK      0x0638
 809 #define SK_TXQS1_FLAG           0x063A
 810 #define SK_TXQS1_TEST1          0x063C
 811 #define SK_TXQS1_TEST2          0x0640
 812 #define SK_TXQS1_TEST3          0x0644
 813 /* yukon-2 only (prefetch unit) */
 814 #define SK_TXQS1_Y2_PREF_CSR    0x0650
 815 #define SK_TXQS1_Y2_PREF_LIDX   0x0654
 816 #define SK_TXQS1_Y2_PREF_ADDRLO 0x0658
 817 #define SK_TXQS1_Y2_PREF_ADDRHI 0x065C
 818 #define SK_TXQS1_Y2_PREF_GETIDX 0x0660
 819 #define SK_TXQS1_Y2_PREF_PUTIDX 0x0664
 820 #define SK_TXQS1_Y2_PREF_FIFOWP 0x0670
 821 #define SK_TXQS1_Y2_PREF_FIFORP 0x0674
 822 #define SK_TXQS1_Y2_PREF_FIFOWM 0x0678
 823 #define SK_TXQS1_Y2_PREF_FIFOLV 0x067C
 824
 825 /* Block 13 -- TX async queue 1 */
 826 #define SK_TXQA1_BUFCNT         0x0680
 827 #define SK_TXQA1_BUFCTL         0x0682
 828 #define SK_TXQA1_NEXTDESC       0x0684
 829 #define SK_TXQA1_RXBUF_LO       0x0688
 830 #define SK_TXQA1_RXBUF_HI       0x068C
 831 #define SK_TXQA1_RXSTAT         0x0690
 832 #define SK_TXQA1_CSUM_STARTVAL  0x0694
 833 #define SK_TXQA1_CSUM_STARTPOS  0x0698
 834 #define SK_TXQA1_CSUM_WRITEPOS  0x069A
 835 #define SK_TXQA1_CURADDR_LO     0x06A0
 836 #define SK_TXQA1_CURADDR_HI     0x06A4
 837 #define SK_TXQA1_CURCNT_LO      0x06A8
 838 #define SK_TXQA1_CURCNT_HI      0x06AC
 839 #define SK_TXQA1_CURBYTES       0x06B0
 840 #define SK_TXQA1_BMU_CSR        0x06B4
 841 #define SK_TXQA1_WATERMARK      0x06B8
 842 #define SK_TXQA1_FLAG           0x06BA
 843 #define SK_TXQA1_TEST1          0x06BC
 844 #define SK_TXQA1_TEST2          0x06C0
 845 #define SK_TXQA1_TEST3          0x06C4
 846 /* yukon-2 only */
 847 #define SK_TXQA1_Y2_WM          0x06C0
 848 #define SK_TXQA1_Y2_AL          0x06C2
 849 #define SK_TXQA1_Y2_RSP         0x06C4
 850 #define SK_TXQA1_Y2_RSL         0x06C6
 851 #define SK_TXQA1_Y2_RP          0x06C8
 852 #define SK_TXQA1_Y2_RL          0x06CA
 853 #define SK_TXQA1_Y2_WP          0x06CC
 854 #define SK_TXQA1_Y2_WSP         0x06CD
 855 #define SK_TXQA1_Y2_WL          0x06CE
 856 #define SK_TXQA1_Y2_WSL         0x06CF
 857 /* yukon-2 only (prefetch unit) */
 858 #define SK_TXQA1_Y2_PREF_CSR    0x06D0
 859 #define SK_TXQA1_Y2_PREF_LIDX   0x06D4
 860 #define SK_TXQA1_Y2_PREF_ADDRLO 0x06D8
 861 #define SK_TXQA1_Y2_PREF_ADDRHI 0x06DC
 862 #define SK_TXQA1_Y2_PREF_GETIDX 0x06E0
 863 #define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4
 864 #define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0
 865 #define SK_TXQA1_Y2_PREF_FIFORP 0x06F4
 866 #define SK_TXQA1_Y2_PREF_FIFOWM 0x06F8
 867 #define SK_TXQA1_Y2_PREF_FIFOLV 0x06FC
 868
 869 /* Block 14 -- TX sync queue 2 */
 870 #define SK_TXQS2_BUFCNT         0x0700
 871 #define SK_TXQS2_BUFCTL         0x0702
 872 #define SK_TXQS2_NEXTDESC       0x0704
 873 #define SK_TXQS2_RXBUF_LO       0x0708
 874 #define SK_TXQS2_RXBUF_HI       0x070C
 875 #define SK_TXQS2_RXSTAT         0x0710
 876 #define SK_TXQS2_CSUM_STARTVAL  0x0714
 877 #define SK_TXQS2_CSUM_STARTPOS  0x0718
 878 #define SK_TXQS2_CSUM_WRITEPOS  0x071A
 879 #define SK_TXQS2_CURADDR_LO     0x0720
 880 #define SK_TXQS2_CURADDR_HI     0x0724
 881 #define SK_TXQS2_CURCNT_LO      0x0728
 882 #define SK_TXQS2_CURCNT_HI      0x072C
 883 #define SK_TXQS2_CURBYTES       0x0730
 884 #define SK_TXQS2_BMU_CSR        0x0734
 885 #define SK_TXQS2_WATERMARK      0x0738
 886 #define SK_TXQS2_FLAG           0x073A
 887 #define SK_TXQS2_TEST1          0x073C
 888 #define SK_TXQS2_TEST2          0x0740
 889 #define SK_TXQS2_TEST3          0x0744
 890 /* yukon-2 only */
 891 #define SK_TXQS2_Y2_WM          0x0740
 892 #define SK_TXQS2_Y2_AL          0x0742
 893 #define SK_TXQS2_Y2_RSP         0x0744
 894 #define SK_TXQS2_Y2_RSL         0x0746
 895 #define SK_TXQS2_Y2_RP          0x0748
 896 #define SK_TXQS2_Y2_RL          0x074A
 897 #define SK_TXQS2_Y2_WP          0x074C
 898 #define SK_TXQS2_Y2_WSP         0x074D
 899 #define SK_TXQS2_Y2_WL          0x074E
 900 #define SK_TXQS2_Y2_WSL         0x074F
 901 /* yukon-2 only (prefetch unit) */
 902 #define SK_TXQS2_Y2_PREF_CSR    0x0750
 903 #define SK_TXQS2_Y2_PREF_LIDX   0x0754
 904 #define SK_TXQS2_Y2_PREF_ADDRLO 0x0758
 905 #define SK_TXQS2_Y2_PREF_ADDRHI 0x075C
 906 #define SK_TXQS2_Y2_PREF_GETIDX 0x0760
 907 #define SK_TXQS2_Y2_PREF_PUTIDX 0x0764
 908 #define SK_TXQS2_Y2_PREF_FIFOWP 0x0770
 909 #define SK_TXQS2_Y2_PREF_FIFORP 0x0774
 910 #define SK_TXQS2_Y2_PREF_FIFOWM 0x0778
 911 #define SK_TXQS2_Y2_PREF_FIFOLV 0x077C
 912
 913 /* Block 15 -- TX async queue 2 */
 914 #define SK_TXQA2_BUFCNT         0x0780
 915 #define SK_TXQA2_BUFCTL         0x0782
 916 #define SK_TXQA2_NEXTDESC       0x0784
 917 #define SK_TXQA2_RXBUF_LO       0x0788
 918 #define SK_TXQA2_RXBUF_HI       0x078C
 919 #define SK_TXQA2_RXSTAT         0x0790
 920 #define SK_TXQA2_CSUM_STARTVAL  0x0794
 921 #define SK_TXQA2_CSUM_STARTPOS  0x0798
 922 #define SK_TXQA2_CSUM_WRITEPOS  0x079A
 923 #define SK_TXQA2_CURADDR_LO     0x07A0
 924 #define SK_TXQA2_CURADDR_HI     0x07A4
 925 #define SK_TXQA2_CURCNT_LO      0x07A8
 926 #define SK_TXQA2_CURCNT_HI      0x07AC
 927 #define SK_TXQA2_CURBYTES       0x07B0
 928 #define SK_TXQA2_BMU_CSR        0x07B4
 929 #define SK_TXQA2_WATERMARK      0x07B8
 930 #define SK_TXQA2_FLAG           0x07BA
 931 #define SK_TXQA2_TEST1          0x07BC
 932 #define SK_TXQA2_TEST2          0x07C0
 933 #define SK_TXQA2_TEST3          0x07C4
 934 /* yukon-2 only */
 935 #define SK_TXQA2_Y2_WM          0x07C0
 936 #define SK_TXQA2_Y2_AL          0x07C2
 937 #define SK_TXQA2_Y2_RSP         0x07C4
 938 #define SK_TXQA2_Y2_RSL         0x07C6
 939 #define SK_TXQA2_Y2_RP          0x07C8
 940 #define SK_TXQA2_Y2_RL          0x07CA
 941 #define SK_TXQA2_Y2_WP          0x07CC
 942 #define SK_TXQA2_Y2_WSP         0x07CD
 943 #define SK_TXQA2_Y2_WL          0x07CE
 944 #define SK_TXQA2_Y2_WSL         0x07CF
 945 /* yukon-2 only (prefetch unit) */
 946 #define SK_TXQA2_Y2_PREF_CSR    0x07D0
 947 #define SK_TXQA2_Y2_PREF_LIDX   0x07D4
 948 #define SK_TXQA2_Y2_PREF_ADDRLO 0x07D8
 949 #define SK_TXQA2_Y2_PREF_ADDRHI 0x07DC
 950 #define SK_TXQA2_Y2_PREF_GETIDX 0x07E0
 951 #define SK_TXQA2_Y2_PREF_PUTIDX 0x07E4
 952 #define SK_TXQA2_Y2_PREF_FIFOWP 0x07F0
 953 #define SK_TXQA2_Y2_PREF_FIFORP 0x07F4
 954 #define SK_TXQA2_Y2_PREF_FIFOWM 0x07F8
 955 #define SK_TXQA2_Y2_PREF_FIFOLV 0x07FC
 956
 957 #define SK_TXBMU_CLR_IRQ_ERR            0x00000001
 958 #define SK_TXBMU_CLR_IRQ_EOF            0x00000002
 959 #define SK_TXBMU_CLR_IRQ_EOB            0x00000004
 960 #define SK_TXBMU_TX_START               0x00000010
 961 #define SK_TXBMU_TX_STOP                0x00000020
 962 #define SK_TXBMU_POLL_OFF               0x00000040
 963 #define SK_TXBMU_POLL_ON                0x00000080
 964 #define SK_TXBMU_TRANSFER_SM_RESET      0x00000100
 965 #define SK_TXBMU_TRANSFER_SM_UNRESET    0x00000200
 966 #define SK_TXBMU_DESCWR_SM_RESET        0x00000400
 967 #define SK_TXBMU_DESCWR_SM_UNRESET      0x00000800
 968 #define SK_TXBMU_DESCRD_SM_RESET        0x00001000
 969 #define SK_TXBMU_DESCRD_SM_UNRESET      0x00002000
 970 #define SK_TXBMU_SUPERVISOR_SM_RESET    0x00004000
 971 #define SK_TXBMU_SUPERVISOR_SM_UNRESET  0x00008000
 972 #define SK_TXBMU_PFI_SM_RESET           0x00010000
 973 #define SK_TXBMU_PFI_SM_UNRESET         0x00020000
 974 #define SK_TXBMU_FIFO_RESET             0x00040000
 975 #define SK_TXBMU_FIFO_UNRESET           0x00080000
 976 #define SK_TXBMU_DESC_RESET             0x00100000
 977 #define SK_TXBMU_DESC_UNRESET           0x00200000
 978 #define SK_TXBMU_SUPERVISOR_IDLE        0x01000000
 979
 980 #define SK_TXBMU_ONLINE         \
 981         (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET|       \
 982         SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET|      \
 983         SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET|                  \
 984         SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
 985
 986 #define SK_TXBMU_OFFLINE                \
 987         (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET|   \
 988         SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET|  \
 989         SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET|              \
 990         SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
 991
 992 /* Block 16 -- Receive RAMbuffer 1 */
 993 #define SK_RXRB1_START          0x0800
 994 #define SK_RXRB1_END            0x0804
 995 #define SK_RXRB1_WR_PTR         0x0808
 996 #define SK_RXRB1_RD_PTR         0x080C
 997 #define SK_RXRB1_UTHR_PAUSE     0x0810
 998 #define SK_RXRB1_LTHR_PAUSE     0x0814
 999 #define SK_RXRB1_UTHR_HIPRIO    0x0818
1000 #define SK_RXRB1_UTHR_LOPRIO    0x081C
1001 #define SK_RXRB1_PKTCNT         0x0820
1002 #define SK_RXRB1_LVL            0x0824
1003 #define SK_RXRB1_CTLTST         0x0828
1004
1005 /* Block 17 -- Receive RAMbuffer 2 */
1006 #define SK_RXRB2_START          0x0880
1007 #define SK_RXRB2_END            0x0884
1008 #define SK_RXRB2_WR_PTR         0x0888
1009 #define SK_RXRB2_RD_PTR         0x088C
1010 #define SK_RXRB2_UTHR_PAUSE     0x0890
1011 #define SK_RXRB2_LTHR_PAUSE     0x0894
1012 #define SK_RXRB2_UTHR_HIPRIO    0x0898
1013 #define SK_RXRB2_UTHR_LOPRIO    0x089C
1014 #define SK_RXRB2_PKTCNT         0x08A0
1015 #define SK_RXRB2_LVL            0x08A4
1016 #define SK_RXRB2_CTLTST         0x08A8
1017
1018 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
1019 #define SK_TXRBS1_START         0x0A00
1020 #define SK_TXRBS1_END           0x0A04
1021 #define SK_TXRBS1_WR_PTR        0x0A08
1022 #define SK_TXRBS1_RD_PTR        0x0A0C
1023 #define SK_TXRBS1_PKTCNT        0x0A20
1024 #define SK_TXRBS1_LVL           0x0A24
1025 #define SK_TXRBS1_CTLTST        0x0A28
1026
1027 /* Block 21 -- Async. Transmit RAMbuffer 1 */
1028 #define SK_TXRBA1_START         0x0A80
1029 #define SK_TXRBA1_END           0x0A84
1030 #define SK_TXRBA1_WR_PTR        0x0A88
1031 #define SK_TXRBA1_RD_PTR        0x0A8C
1032 #define SK_TXRBA1_PKTCNT        0x0AA0
1033 #define SK_TXRBA1_LVL           0x0AA4
1034 #define SK_TXRBA1_CTLTST        0x0AA8
1035
1036 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
1037 #define SK_TXRBS2_START         0x0B00
1038 #define SK_TXRBS2_END           0x0B04
1039 #define SK_TXRBS2_WR_PTR        0x0B08
1040 #define SK_TXRBS2_RD_PTR        0x0B0C
1041 #define SK_TXRBS2_PKTCNT        0x0B20
1042 #define SK_TXRBS2_LVL           0x0B24
1043 #define SK_TXRBS2_CTLTST        0x0B28
1044
1045 /* Block 23 -- Async. Transmit RAMbuffer 2 */
1046 #define SK_TXRBA2_START         0x0B80
1047 #define SK_TXRBA2_END           0x0B84
1048 #define SK_TXRBA2_WR_PTR        0x0B88
1049 #define SK_TXRBA2_RD_PTR        0x0B8C
1050 #define SK_TXRBA2_PKTCNT        0x0BA0
1051 #define SK_TXRBA2_LVL           0x0BA4
1052 #define SK_TXRBA2_CTLTST        0x0BA8
1053
1054 #define SK_RBCTL_RESET          0x01
1055 #define SK_RBCTL_UNRESET        0x02
1056 #define SK_RBCTL_OFF            0x04
1057 #define SK_RBCTL_ON             0x08
1058 #define SK_RBCTL_STORENFWD_OFF  0x10
1059 #define SK_RBCTL_STORENFWD_ON   0x20
1060
1061 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
1062 #define SK_RXF1_END             0x0C00
1063 #define SK_RXF1_WPTR            0x0C04
1064 #define SK_RXF1_RPTR            0x0C0C
1065 #define SK_RXF1_PKTCNT          0x0C10
1066 #define SK_RXF1_LVL             0x0C14
1067 #define SK_RXF1_MACCTL          0x0C18
1068 #define SK_RXF1_CTL             0x0C1C
1069 #define SK_RXLED1_CNTINIT       0x0C20
1070 #define SK_RXLED1_COUNTER       0x0C24
1071 #define SK_RXLED1_CTL           0x0C28
1072 #define SK_RXLED1_TST           0x0C29
1073 #define SK_LINK_SYNC1_CINIT     0x0C30
1074 #define SK_LINK_SYNC1_COUNTER   0x0C34
1075 #define SK_LINK_SYNC1_CTL       0x0C38
1076 #define SK_LINK_SYNC1_TST       0x0C39
1077 #define SK_LINKLED1_CTL         0x0C3C
1078
1079 #define SK_FIFO_END             0x3F
1080
1081 /* Receive MAC FIFO 1 (Yukon Only) */
1082 #define SK_RXMF1_END            0x0C40
1083 #define SK_RXMF1_THRESHOLD      0x0C44
1084 #define SK_RXMF1_CTRL_TEST      0x0C48
1085 #define SK_RXMF1_FLUSH_MASK     0x0C4C
1086 #define SK_RXMF1_FLUSH_THRESHOLD        0x0C50
1087 #define SK_RXMF1_WRITE_PTR      0x0C60
1088 #define SK_RXMF1_WRITE_LEVEL    0x0C68
1089 #define SK_RXMF1_READ_PTR       0x0C70
1090 #define SK_RXMF1_READ_LEVEL     0x0C78
1091
1092 /* Receive MAC FIFO 1 Control/Test */
1093 #define SK_RFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
1094 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
1095 #define SK_RFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
1096 #define SK_RFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
1097 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
1098 #define SK_RFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
1099 #define SK_RFCTL_FIFO_FLUSH_ON  0x00000080      /* RX FIFO Flush mode on */
1100 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000040      /* RX FIFO Flsuh mode off */
1101 #define SK_RFCTL_RX_FIFO_OVER   0x00000020      /* Clear IRQ RX FIFO Overrun */
1102 #define SK_RFCTL_FRAME_RX_DONE  0x00000010      /* Clear IRQ Frame RX Done */
1103 #define SK_RFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
1104 #define SK_RFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
1105 #define SK_RFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
1106 #define SK_RFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
1107
1108 #define SK_RFCTL_FIFO_THRESHOLD 0x0a    /* flush threshold (default) */
1109
1110 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
1111 #define SK_RXF2_END             0x0C80
1112 #define SK_RXF2_WPTR            0x0C84
1113 #define SK_RXF2_RPTR            0x0C8C
1114 #define SK_RXF2_PKTCNT          0x0C90
1115 #define SK_RXF2_LVL             0x0C94
1116 #define SK_RXF2_MACCTL          0x0C98
1117 #define SK_RXF2_CTL             0x0C9C
1118 #define SK_RXLED2_CNTINIT       0x0CA0
1119 #define SK_RXLED2_COUNTER       0x0CA4
1120 #define SK_RXLED2_CTL           0x0CA8
1121 #define SK_RXLED2_TST           0x0CA9
1122 #define SK_LINK_SYNC2_CINIT     0x0CB0
1123 #define SK_LINK_SYNC2_COUNTER   0x0CB4
1124 #define SK_LINK_SYNC2_CTL       0x0CB8
1125 #define SK_LINK_SYNC2_TST       0x0CB9
1126 #define SK_LINKLED2_CTL         0x0CBC
1127
1128 #define SK_RXMACCTL_CLR_IRQ_NOSTS       0x00000001
1129 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP    0x00000002
1130 #define SK_RXMACCTL_TSTAMP_OFF          0x00000004
1131 #define SK_RXMACCTL_RSTAMP_ON           0x00000008
1132 #define SK_RXMACCTL_FLUSH_OFF           0x00000010
1133 #define SK_RXMACCTL_FLUSH_ON            0x00000020
1134 #define SK_RXMACCTL_PAUSE_OFF           0x00000040
1135 #define SK_RXMACCTL_PAUSE_ON            0x00000080
1136 #define SK_RXMACCTL_AFULL_OFF           0x00000100
1137 #define SK_RXMACCTL_AFULL_ON            0x00000200
1138 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
1139 #define SK_RXMACCTL_VALIDTIME_PATCH_ON  0x00000800
1140 #define SK_RXMACCTL_RXRDY_PATCH_OFF     0x00001000
1141 #define SK_RXMACCTL_RXRDY_PATCH_ON      0x00002000
1142 #define SK_RXMACCTL_STS_TIMEO           0x00FF0000
1143 #define SK_RXMACCTL_TSTAMP_TIMEO        0xFF000000
1144
1145 #define SK_RXLEDCTL_ENABLE              0x0001
1146 #define SK_RXLEDCTL_COUNTER_STOP        0x0002
1147 #define SK_RXLEDCTL_COUNTER_START       0x0004
1148
1149 #define SK_LINKLED_OFF                  0x0001
1150 #define SK_LINKLED_ON                   0x0002
1151 #define SK_LINKLED_LINKSYNC_OFF         0x0004
1152 #define SK_LINKLED_LINKSYNC_ON          0x0008
1153 #define SK_LINKLED_BLINK_OFF            0x0010
1154 #define SK_LINKLED_BLINK_ON             0x0020
1155
1156 /* Block 26 -- TX MAC FIFO 1 regisrers  */
1157 #define SK_TXF1_END             0x0D00
1158 #define SK_TXF1_WPTR            0x0D04
1159 #define SK_TXF1_RPTR            0x0D0C
1160 #define SK_TXF1_PKTCNT          0x0D10
1161 #define SK_TXF1_LVL             0x0D14
1162 #define SK_TXF1_MACCTL          0x0D18
1163 #define SK_TXF1_CTL             0x0D1C
1164 #define SK_TXLED1_CNTINIT       0x0D20
1165 #define SK_TXLED1_COUNTER       0x0D24
1166 #define SK_TXLED1_CTL           0x0D28
1167 #define SK_TXLED1_TST           0x0D29
1168
1169 /* Transmit MAC FIFO 1 (Yukon Only) */
1170 #define SK_TXMF1_END            0x0D40
1171 #define SK_TXMF1_THRESHOLD      0x0D44
1172 #define SK_TXMF1_CTRL_TEST      0x0D48
1173 #define SK_TXMF1_WRITE_PTR      0x0D60
1174 #define SK_TXMF1_WRITE_SHADOW   0x0D64
1175 #define SK_TXMF1_WRITE_LEVEL    0x0D68
1176 #define SK_TXMF1_READ_PTR       0x0D70
1177 #define SK_TXMF1_RESTART_PTR    0x0D74
1178 #define SK_TXMF1_READ_LEVEL     0x0D78
1179
1180 /* Transmit MAC FIFO Control/Test */
1181 #define SK_TFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
1182 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
1183 #define SK_TFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
1184 #define SK_TFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
1185 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
1186 #define SK_TFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
1187 #define SK_TFCTL_TX_FIFO_UNDER  0x00000040      /* Clear IRQ TX FIFO Under */
1188 #define SK_TFCTL_FRAME_TX_DONE  0x00000020      /* Clear IRQ Frame TX Done */
1189 #define SK_TFCTL_IRQ_PARITY_ER  0x00000010      /* Clear IRQ Parity Error */
1190 #define SK_TFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
1191 #define SK_TFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
1192 #define SK_TFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
1193 #define SK_TFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
1194
1195 /* Block 27 -- TX MAC FIFO 2 regisrers  */
1196 #define SK_TXF2_END             0x0D80
1197 #define SK_TXF2_WPTR            0x0D84
1198 #define SK_TXF2_RPTR            0x0D8C
1199 #define SK_TXF2_PKTCNT          0x0D90
1200 #define SK_TXF2_LVL             0x0D94
1201 #define SK_TXF2_MACCTL          0x0D98
1202 #define SK_TXF2_CTL             0x0D9C
1203 #define SK_TXLED2_CNTINIT       0x0DA0
1204 #define SK_TXLED2_COUNTER       0x0DA4
1205 #define SK_TXLED2_CTL           0x0DA8
1206 #define SK_TXLED2_TST           0x0DA9
1207
1208 #define SK_TXMACCTL_XMAC_RESET          0x00000001
1209 #define SK_TXMACCTL_XMAC_UNRESET        0x00000002
1210 #define SK_TXMACCTL_LOOP_OFF            0x00000004
1211 #define SK_TXMACCTL_LOOP_ON             0x00000008
1212 #define SK_TXMACCTL_FLUSH_OFF           0x00000010
1213 #define SK_TXMACCTL_FLUSH_ON            0x00000020
1214 #define SK_TXMACCTL_WAITEMPTY_OFF       0x00000040
1215 #define SK_TXMACCTL_WAITEMPTY_ON        0x00000080
1216 #define SK_TXMACCTL_AFULL_OFF           0x00000100
1217 #define SK_TXMACCTL_AFULL_ON            0x00000200
1218 #define SK_TXMACCTL_TXRDY_PATCH_OFF     0x00000400
1219 #define SK_TXMACCTL_RXRDY_PATCH_ON      0x00000800
1220 #define SK_TXMACCTL_PKT_RECOVERY_OFF    0x00001000
1221 #define SK_TXMACCTL_PKT_RECOVERY_ON     0x00002000
1222 #define SK_TXMACCTL_CLR_IRQ_PERR        0x00008000
1223 #define SK_TXMACCTL_WAITAFTERFLUSH      0x00010000
1224
1225 #define SK_TXLEDCTL_ENABLE              0x0001
1226 #define SK_TXLEDCTL_COUNTER_STOP        0x0002
1227 #define SK_TXLEDCTL_COUNTER_START       0x0004
1228
1229 #define SK_FIFO_RESET           0x00000001
1230 #define SK_FIFO_UNRESET         0x00000002
1231 #define SK_FIFO_OFF             0x00000004
1232 #define SK_FIFO_ON              0x00000008
1233
1234 /* Block 28 -- Descriptor Poll Timer */
1235 #define SK_DPT_INIT             0x0e00  /* Initial value 24 bits */
1236 #define SK_DPT_TIMER            0x0e04  /* Mul of 78.12MHz clk (24b) */
1237
1238 #define SK_DPT_TIMER_MAX        0x00ffffffff    /* 214.75ms at 78.125MHz */
1239
1240 #define SK_DPT_TIMER_CTRL       0x0e08  /* Timer Control 8 bits */
1241 #define SK_DPT_TCTL_STOP        0x01    /* Stop Timer */
1242 #define SK_DPT_TCTL_START       0x02    /* Start Timer */
1243
1244 #define SK_DPT_TIMER_TEST       0x0e0a  /* Timer Test 16 bits */
1245 #define SK_DPT_TTEST_STEP       0x0001  /* Timer Decrement */
1246 #define SK_DPT_TTEST_OFF        0x0002  /* Test Mode Off */
1247 #define SK_DPT_TTEST_ON         0x0004  /* Test Mode On */
1248
1249 #define SK_TSTAMP_COUNT         0x0e14
1250 #define SK_TSTAMP_CTL           0x0e18
1251
1252 #define SK_TSTAMP_IRQ_CLEAR     0x01
1253 #define SK_TSTAMP_STOP          0x02
1254 #define SK_TSTAMP_START         0x04
1255
1256 #define SK_Y2_ASF_CSR           0x0e68
1257
1258 #define SK_Y2_ASF_RESET         0x08
1259
1260 #define SK_Y2_LEV_ITIMERINIT    0x0eb0
1261 #define SK_Y2_LEV_ITIMERCTL     0x0eb8
1262 #define SK_Y2_TX_ITIMERINIT     0x0ec0
1263 #define SK_Y2_TX_ITIMERCTL      0x0ec8
1264 #define SK_Y2_ISR_ITIMERINIT    0x0ed0
1265 #define SK_Y2_ISR_ITIMERCTL     0x0ed8
1266
1267 /* Block 29 -- Status BMU (Yukon-2 only) */
1268 #define SK_STAT_BMU_CSR         0x0e80
1269 #define SK_STAT_BMU_LIDX        0x0e84
1270 #define SK_STAT_BMU_ADDRLO      0x0e88
1271 #define SK_STAT_BMU_ADDRHI      0x0e8c
1272 #define SK_STAT_BMU_TXA1_RIDX   0x0e90
1273 #define SK_STAT_BMU_TXS1_RIDX   0x0e92
1274 #define SK_STAT_BMU_TXA2_RIDX   0x0e94
1275 #define SK_STAT_BMU_TXS2_RIDX   0x0e96
1276 #define SK_STAT_BMU_TX_THRESH   0x0e98
1277 #define SK_STAT_BMU_PUTIDX      0x0e9c
1278 #define SK_STAT_BMU_FIFOWP      0x0ea0
1279 #define SK_STAT_BMU_FIFORP      0x0ea4
1280 #define SK_STAT_BMU_FIFORSP     0x0ea6
1281 #define SK_STAT_BMU_FIFOLV      0x0ea8
1282 #define SK_STAT_BMU_FIFOSLV     0x0eaa
1283 #define SK_STAT_BMU_FIFOWM      0x0eac
1284 #define SK_STAT_BMU_FIFOIWM     0x0ead
1285
1286 #define SK_STAT_BMU_RESET       0x00000001
1287 #define SK_STAT_BMU_UNRESET     0x00000002
1288 #define SK_STAT_BMU_OFF         0x00000004
1289 #define SK_STAT_BMU_ON          0x00000008
1290 #define SK_STAT_BMU_IRQ_CLEAR   0x00000010
1291
1292 #define SK_STAT_BMU_TXTHIDX_MSK 0x0fff
1293
1294 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
1295 #define SK_GMAC_CTRL            0x0f00  /* GMAC Control Register */
1296 #define SK_GPHY_CTRL            0x0f04  /* GPHY Control Register */
1297 #define SK_GMAC_ISR             0x0f08  /* GMAC Interrupt Source Register */
1298 #define SK_GMAC_IMR             0x0f0c  /* GMAC Interrupt Mask Register */
1299 #define SK_LINK_CTRL            0x0f10  /* Link Control Register (LCR) */
1300 #define SK_WOL_CTRL             0x0f20  /* Wake on LAN Control Register */
1301 #define SK_MAC_ADDR_LOW         0x0f24  /* Mack Address Registers LOW */
1302 #define SK_MAC_ADDR_HIGH        0x0f28  /* Mack Address Registers HIGH */
1303 #define SK_PAT_READ_PTR         0x0f2c  /* Pattern Read Pointer Register */
1304 #define SK_PAT_LEN_REG0         0x0f30  /* Pattern Length Register 0 */
1305 #define SK_PAT_LEN0             0x0f30  /* Pattern Length 0 */
1306 #define SK_PAT_LEN1             0x0f31  /* Pattern Length 1 */
1307 #define SK_PAT_LEN2             0x0f32  /* Pattern Length 2 */
1308 #define SK_PAT_LEN3             0x0f33  /* Pattern Length 3 */
1309 #define SK_PAT_LEN_REG1         0x0f34  /* Pattern Length Register 1 */
1310 #define SK_PAT_LEN4             0x0f34  /* Pattern Length 4 */
1311 #define SK_PAT_LEN5             0x0f35  /* Pattern Length 5 */
1312 #define SK_PAT_LEN6             0x0f36  /* Pattern Length 6 */
1313 #define SK_PAT_LEN7             0x0f37  /* Pattern Length 7 */
1314 #define SK_PAT_CTR_REG0         0x0f38  /* Pattern Counter Register 0 */
1315 #define SK_PAT_CTR0             0x0f38  /* Pattern Counter 0 */
1316 #define SK_PAT_CTR1             0x0f39  /* Pattern Counter 1 */
1317 #define SK_PAT_CTR2             0x0f3a  /* Pattern Counter 2 */
1318 #define SK_PAT_CTR3             0x0f3b  /* Pattern Counter 3 */
1319 #define SK_PAT_CTR_REG1         0x0f3c  /* Pattern Counter Register 1 */
1320 #define SK_PAT_CTR4             0x0f3c  /* Pattern Counter 4 */
1321 #define SK_PAT_CTR5             0x0f3d  /* Pattern Counter 5 */
1322 #define SK_PAT_CTR6             0x0f3e  /* Pattern Counter 6 */
1323 #define SK_PAT_CTR7             0x0f3f  /* Pattern Counter 7 */
1324
1325 #define SK_GMAC_LOOP_ON         0x00000020      /* Loopback mode for testing */
1326 #define SK_GMAC_LOOP_OFF        0x00000010      /* purposes */
1327 #define SK_GMAC_PAUSE_ON        0x00000008      /* enable forward of pause */
1328 #define SK_GMAC_PAUSE_OFF       0x00000004      /* signal to GMAC */
1329 #define SK_GMAC_RESET_CLEAR     0x00000002      /* Clear GMAC Reset */
1330 #define SK_GMAC_RESET_SET       0x00000001      /* Set GMAC Reset */
1331
1332 #define SK_GPHY_SEL_BDT         0x10000000      /* Select Bidirectional xfer */
1333 #define SK_GPHY_INT_POL_HI      0x08000000      /* IRQ Polarity Active */
1334 #define SK_GPHY_75_OHM          0x04000000      /* Use 75 Ohm Termination */
1335 #define SK_GPHY_DIS_FC          0x02000000      /* Disable Auto Fiber/Copper */
1336 #define SK_GPHY_DIS_SLEEP       0x01000000      /* Disable Energy Detect */
1337 #define SK_GPHY_HWCFG_M_3       0x00800000      /* HWCFG_MODE[3] */
1338 #define SK_GPHY_HWCFG_M_2       0x00400000      /* HWCFG_MODE[2] */
1339 #define SK_GPHY_HWCFG_M_1       0x00200000      /* HWCFG_MODE[1] */
1340 #define SK_GPHY_HWCFG_M_0       0x00100000      /* HWCFG_MODE[0] */
1341 #define SK_GPHY_ANEG_0          0x00080000      /* ANEG[0] */
1342 #define SK_GPHY_ENA_XC          0x00040000      /* Enable MDI Crossover */
1343 #define SK_GPHY_DIS_125         0x00020000      /* Disable 125MHz Clock */
1344 #define SK_GPHY_ANEG_3          0x00010000      /* ANEG[3] */
1345 #define SK_GPHY_ANEG_2          0x00008000      /* ANEG[2] */
1346 #define SK_GPHY_ANEG_1          0x00004000      /* ANEG[1] */
1347 #define SK_GPHY_ENA_PAUSE       0x00002000      /* Enable Pause */
1348 #define SK_GPHY_PHYADDR_4       0x00001000      /* Bit 4 of Phy Addr */
1349 #define SK_GPHY_PHYADDR_3       0x00000800      /* Bit 3 of Phy Addr */
1350 #define SK_GPHY_PHYADDR_2       0x00000400      /* Bit 2 of Phy Addr */
1351 #define SK_GPHY_PHYADDR_1       0x00000200      /* Bit 1 of Phy Addr */
1352 #define SK_GPHY_PHYADDR_0       0x00000100      /* Bit 0 of Phy Addr */
1353 #define SK_GPHY_RESET_CLEAR     0x00000002      /* Clear GPHY Reset */
1354 #define SK_GPHY_RESET_SET       0x00000001      /* Set GPHY Reset */
1355
1356 #define SK_GPHY_COPPER          (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1357                                  SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
1358 #define SK_GPHY_FIBER           (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1359                                  SK_GPHY_HWCFG_M_2 )
1360 #define SK_GPHY_ANEG_ALL        (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
1361                                  SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
1362
1363 #define SK_GMAC_INT_TX_OFLOW    0x20    /* Transmit Counter Overflow */
1364 #define SK_GMAC_INT_RX_OFLOW    0x10    /* Receiver Overflow */
1365 #define SK_GMAC_INT_TX_UNDER    0x08    /* Transmit FIFO Underrun */
1366 #define SK_GMAC_INT_TX_DONE     0x04    /* Transmit Complete */
1367 #define SK_GMAC_INT_RX_OVER     0x02    /* Receive FIFO Overrun */
1368 #define SK_GMAC_INT_RX_DONE     0x01    /* Receive Complete */
1369
1370 #define SK_LINK_RESET_CLEAR     0x0002  /* Link Reset Clear */
1371 #define SK_LINK_RESET_SET       0x0001  /* Link Reset Set */
1372
1373 /* Block 31 -- reserved */
1374
1375 /* Block 32-33 -- Pattern Ram */
1376 #define SK_WOL_PRAM             0x1000
1377
1378 /* Block 0x22 - 0x37 -- reserved */
1379
1380 /* Block 0x38 -- Y2 PCI config registers */
1381 #define SK_Y2_PCI_BASE          0x1c00
1382
1383 /* Compute offset of mirrored PCI register */
1384 #define SK_Y2_PCI_REG(reg)      ((reg) + SK_Y2_PCI_BASE)
1385
1386 /* Block 0x39 - 0x3f -- reserved */
1387
1388 /* Block 0x40 to 0x4F -- XMAC 1 registers */
1389 #define SK_XMAC1_BASE   0x2000
1390
1391 /* Block 0x50 to 0x5F -- MARV 1 registers */
1392 #define SK_MARV1_BASE   0x2800
1393
1394 /* Block 0x60 to 0x6F -- XMAC 2 registers */
1395 #define SK_XMAC2_BASE   0x3000
1396
1397 /* Block 0x70 to 0x7F -- MARV 2 registers */
1398 #define SK_MARV2_BASE   0x3800
1399
1400 /* Compute relative offset of an XMAC register in the XMAC window(s). */
1401 #define SK_XMAC_REG(sc, reg)    (((reg) * 2) + SK_XMAC1_BASE + \
1402         (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
1403
1404 #if 0
1405 #define SK_XM_READ_4(sc, reg)                                           \
1406         ((sk_win_read_2(sc->sk_softc,                                   \
1407               SK_XMAC_REG(sc, reg)) & 0xFFFF) |         \
1408          ((sk_win_read_2(sc->sk_softc,                                  \
1409               SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
1410
1411 #define SK_XM_WRITE_4(sc, reg, val)                                     \
1412         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg),              \
1413                        ((val) & 0xFFFF));                               \
1414         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2),          \
1415                        ((val) >> 16) & 0xFFFF)
1416 #else
1417 #define SK_XM_READ_4(sc, reg)           \
1418         sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
1419
1420 #define SK_XM_WRITE_4(sc, reg, val)     \
1421         sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
1422 #endif
1423
1424 #define SK_XM_READ_2(sc, reg)           \
1425         sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
1426
1427 #define SK_XM_WRITE_2(sc, reg, val)     \
1428         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
1429
1430 #define SK_XM_SETBIT_4(sc, reg, x)      \
1431         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
1432
1433 #define SK_XM_CLRBIT_4(sc, reg, x)      \
1434         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
1435
1436 #define SK_XM_SETBIT_2(sc, reg, x)      \
1437         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
1438
1439 #define SK_XM_CLRBIT_2(sc, reg, x)      \
1440         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
1441
1442 /* Compute relative offset of an MARV register in the MARV window(s). */
1443 #define SK_YU_REG(sc, reg) \
1444         ((reg) + SK_MARV1_BASE + \
1445         (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
1446
1447 #define SK_YU_READ_4(sc, reg)           \
1448         sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1449
1450 #define SK_YU_READ_2(sc, reg)           \
1451         sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1452
1453 #define SK_YU_WRITE_4(sc, reg, val)     \
1454         sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1455
1456 #define SK_YU_WRITE_2(sc, reg, val)     \
1457         sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1458
1459 #define SK_YU_SETBIT_4(sc, reg, x)      \
1460         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
1461
1462 #define SK_YU_CLRBIT_4(sc, reg, x)      \
1463         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
1464
1465 #define SK_YU_SETBIT_2(sc, reg, x)      \
1466         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
1467
1468 #define SK_YU_CLRBIT_2(sc, reg, x)      \
1469         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
1470
1471 /*
1472  * The default FIFO threshold on the XMAC II is 4 bytes. On
1473  * dual port NICs, this often leads to transmit underruns, so we
1474  * bump the threshold a little.
1475  */
1476 #define SK_XM_TX_FIFOTHRESH     512
1477
1478 #define SK_PCI_VENDOR_ID        0x0000
1479 #define SK_PCI_DEVICE_ID        0x0002
1480 #define SK_PCI_COMMAND          0x0004
1481 #define SK_PCI_STATUS           0x0006
1482 #define SK_PCI_REVID            0x0008
1483 #define SK_PCI_CLASSCODE        0x0009
1484 #define SK_PCI_CACHELEN         0x000C
1485 #define SK_PCI_LATENCY_TIMER    0x000D
1486 #define SK_PCI_HEADER_TYPE      0x000E
1487 #define SK_PCI_LOMEM            0x0010
1488 #define SK_PCI_LOIO             0x0014
1489 #define SK_PCI_SUBVEN_ID        0x002C
1490 #define SK_PCI_SYBSYS_ID        0x002E
1491 #define SK_PCI_BIOSROM          0x0030
1492 #define SK_PCI_INTLINE          0x003C
1493 #define SK_PCI_INTPIN           0x003D
1494 #define SK_PCI_MINGNT           0x003E
1495 #define SK_PCI_MINLAT           0x003F
1496
1497 /* device specific PCI registers */
1498 #define SK_PCI_OURREG1          0x0040
1499 #define SK_PCI_OURREG2          0x0044
1500 #define SK_PCI_CAPID            0x0048 /* 8 bits */
1501 #define SK_PCI_NEXTPTR          0x0049 /* 8 bits */
1502 #define SK_PCI_PWRMGMTCAP       0x004A /* 16 bits */
1503 #define SK_PCI_PWRMGMTCTRL      0x004C /* 16 bits */
1504 #define SK_PCI_PME_EVENT        0x004F
1505 #define SK_PCI_VPD_CAPID        0x0050
1506 #define SK_PCI_VPD_NEXTPTR      0x0051
1507 #define SK_PCI_VPD_ADDR         0x0052
1508 #define SK_PCI_VPD_DATA         0x0054
1509 #define SK_PCI_OURREG3          0x0080 /* Yukon EC U */
1510 #define SK_PCI_OURREG4          0x0084
1511 #define SK_PCI_OURREG5          0x0088
1512
1513 #define SK_Y2_REG1_PHY1_COMA    0x10000000
1514 #define SK_Y2_REG1_PHY2_COMA    0x20000000
1515
1516 /* SK_PCI_OURREG4 32bits (Yukon-ECU only) */
1517 #define SK_Y2_REG4_TIMER_VALUE_MSK      (0xff << 16)
1518 #define SK_Y2_REG4_FORCE_ASPM_REQUEST   __BIT(15)
1519 #define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN  __BIT(14)
1520 #define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY  __BIT(13)
1521 #define SK_Y2_REG4_ASPM_CLKRUN_REQUEST  __BIT(12)
1522 #define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA        __BIT(4)
1523 #define SK_Y2_REG4_ASPM_CLKREQ_PAD      __BIT(3)
1524 #define SK_Y2_REG4_ASPM_A1_MODE_SELECT  __BIT(2)
1525 #define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA        __BIT(1)
1526 #define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA        __BIT(0)
1527
1528 #define SK_PSTATE_MASK          0x0003
1529 #define SK_PSTATE_D0            0x0000
1530 #define SK_PSTATE_D1            0x0001
1531 #define SK_PSTATE_D2            0x0002
1532 #define SK_PSTATE_D3            0x0003
1533 #define SK_PME_EN               0x0010
1534 #define SK_PME_STATUS           0x8000
1535
1536 /*
1537  * VPD flag bit. Set to 0 to initiate a read, will become 1 when
1538  * read is complete. Set to 1 to initiate a write, will become 0
1539  * when write is finished.
1540  */
1541 #define SK_VPD_FLAG             0x8000
1542
1543 /* VPD structures */
1544 struct vpd_res {
1545         u_int8_t                vr_id;
1546         u_int8_t                vr_len;
1547         u_int8_t                vr_pad;
1548 };
1549
1550 struct vpd_key {
1551         char                    vk_key[2];
1552         u_int8_t                vk_len;
1553 };
1554
1555 #define VPD_RES_ID      0x82    /* ID string */
1556 #define VPD_RES_READ    0x90    /* start of read only area */
1557 #define VPD_RES_WRITE   0x81    /* start of read/write area */
1558 #define VPD_RES_END     0x78    /* end tag */
1559
1560 #define CSR_WRITE_4(sc, reg, val) \
1561         bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1562 #define CSR_WRITE_2(sc, reg, val) \
1563         bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1564 #define CSR_WRITE_1(sc, reg, val) \
1565         bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1566
1567 #define CSR_READ_4(sc, reg) \
1568         bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1569 #define CSR_READ_2(sc, reg) \
1570         bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1571 #define CSR_READ_1(sc, reg) \
1572         bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1573
1574 struct sk_type {
1575         u_int16_t               sk_vid;
1576         u_int16_t               sk_did;
1577         const char              *sk_name;
1578 };
1579
1580 #define SK_ADDR_LO(x)   ((u_int64_t) (x) & 0xffffffff)
1581 #define SK_ADDR_HI(x)   ((u_int64_t) (x) >> 32)
1582
1583 #define SK_RING_ALIGN   64
1584
1585 #define SK_ADDR_LO(x)   ((u_int64_t) (x) & 0xffffffff)
1586 #define SK_ADDR_HI(x)   ((u_int64_t) (x) >> 32)
1587
1588 #define SK_RING_ALIGN   64
1589
1590 /* RX queue descriptor data structure */
1591 struct sk_rx_desc {
1592         u_int32_t               sk_ctl;
1593         u_int32_t               sk_next;
1594         u_int32_t               sk_data_lo;
1595         u_int32_t               sk_data_hi;
1596         u_int32_t               sk_xmac_rxstat;
1597         u_int32_t               sk_timestamp;
1598         u_int16_t               sk_csum2;
1599         u_int16_t               sk_csum1;
1600         u_int16_t               sk_csum2_start;
1601         u_int16_t               sk_csum1_start;
1602 };
1603
1604 #define SK_OPCODE_DEFAULT       0x00550000
1605 #define SK_OPCODE_CSUM          0x00560000
1606
1607 #define SK_RXCTL_LEN            0x0000FFFF
1608 #define SK_RXCTL_OPCODE         0x00FF0000
1609 #define SK_RXCTL_TSTAMP_VALID   0x01000000
1610 #define SK_RXCTL_STATUS_VALID   0x02000000
1611 #define SK_RXCTL_DEV0           0x04000000
1612 #define SK_RXCTL_EOF_INTR       0x08000000
1613 #define SK_RXCTL_EOB_INTR       0x10000000
1614 #define SK_RXCTL_LASTFRAG       0x20000000
1615 #define SK_RXCTL_FIRSTFRAG      0x40000000
1616 #define SK_RXCTL_OWN            0x80000000
1617
1618 #define SK_RXSTAT       \
1619         (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
1620          SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1621
1622 struct sk_tx_desc {
1623         u_int32_t               sk_ctl;
1624         u_int32_t               sk_next;
1625         u_int32_t               sk_data_lo;
1626         u_int32_t               sk_data_hi;
1627         u_int32_t               sk_xmac_txstat;
1628         u_int16_t               sk_rsvd0;
1629         u_int16_t               sk_csum_startval;
1630         u_int16_t               sk_csum_startpos;
1631         u_int16_t               sk_csum_writepos;
1632         u_int32_t               sk_rsvd1;
1633 };
1634
1635 #define SK_TXCTL_LEN            0x0000FFFF
1636 #define SK_TXCTL_OPCODE         0x00FF0000
1637 #define SK_TXCTL_SW             0x01000000
1638 #define SK_TXCTL_NOCRC          0x02000000
1639 #define SK_TXCTL_STORENFWD      0x04000000
1640 #define SK_TXCTL_EOF_INTR       0x08000000
1641 #define SK_TXCTL_EOB_INTR       0x10000000
1642 #define SK_TXCTL_LASTFRAG       0x20000000
1643 #define SK_TXCTL_FIRSTFRAG      0x40000000
1644 #define SK_TXCTL_OWN            0x80000000
1645
1646 #define SK_TXSTAT       \
1647         (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1648
1649 #define SK_RXBYTES(x)           ((x) & 0x0000FFFF);
1650 #define SK_TXBYTES              SK_RXBYTES
1651
1652 #define SK_TX_RING_CNT          512
1653 #define SK_RX_RING_CNT          256
1654
1655 struct msk_rx_desc {
1656         u_int32_t               sk_addr;
1657         u_int16_t               sk_len;
1658         u_int8_t                sk_ctl;
1659         u_int8_t                sk_opcode;
1660 } __packed;
1661
1662 #define SK_Y2_RXOPC_BUFFER      0x40
1663 #define SK_Y2_RXOPC_PACKET      0x41
1664 #define SK_Y2_RXOPC_OWN         0x80
1665
1666 struct msk_tx_desc {
1667         u_int32_t               sk_addr;
1668         u_int16_t               sk_len;
1669         u_int8_t                sk_ctl;
1670         u_int8_t                sk_opcode;
1671 } __packed;
1672
1673 #define SK_Y2_TXCTL_LASTFRAG    0x80
1674
1675 #define SK_Y2_TXOPC_BUFFER      0x40
1676 #define SK_Y2_TXOPC_PACKET      0x41
1677 #define SK_Y2_TXOPC_OWN         0x80
1678
1679 struct msk_status_desc {
1680         u_int32_t               sk_status;
1681         u_int16_t               sk_len;
1682         u_int8_t                sk_link;
1683         u_int8_t                sk_opcode;
1684 } __packed;
1685
1686 #define SK_Y2_STOPC_RXSTAT      0x60
1687 #define SK_Y2_STOPC_TXSTAT      0x68
1688 #define SK_Y2_STOPC_OWN         0x80
1689
1690 #define SK_Y2_ST_TXA1_MSKL      0x00000fff
1691 #define SK_Y2_ST_TXA1_SHIFT     0
1692
1693 #define SK_Y2_ST_TXA2_MSKL      0xff000000
1694 #define SK_Y2_ST_TXA2_SHIFTL    24
1695 #define SK_Y2_ST_TXA2_MSKH      0x000f
1696 #define SK_Y2_ST_TXA2_SHIFTH    8
1697
1698 #define SK_Y2_ST_TXA1_MSKL      0x00000fff
1699 #define SK_Y2_ST_TXA1_SHIFT     0
1700
1701 #define SK_Y2_ST_TXA2_MSKL      0xff000000
1702 #define SK_Y2_ST_TXA2_SHIFTL    24
1703 #define SK_Y2_ST_TXA2_MSKH      0x000f
1704 #define SK_Y2_ST_TXA2_SHIFTH    8
1705
1706 #define MSK_TX_RING_CNT         512
1707 #define MSK_RX_RING_CNT         512
1708 #define MSK_STATUS_RING_CNT     2048
1709
1710 /*
1711  * Jumbo buffer stuff. Note that we must allocate more jumbo
1712  * buffers than there are descriptors in the receive ring. This
1713  * is because we don't know how long it will take for a packet
1714  * to be released after we hand it off to the upper protocol
1715  * layers. To be safe, we allocate 1.5 times the number of
1716  * receive descriptors.
1717  */
1718 #define SK_JUMBO_FRAMELEN       9018
1719 #define SK_JUMBO_MTU            (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1720 #define SK_MIN_FRAMELEN         (ETHER_MIN_LEN - ETHER_CRC_LEN)
1721 #define SK_JSLOTS               384
1722
1723 #define SK_JRAWLEN      (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
1724 #define SK_JLEN         SK_JRAWLEN
1725 #define SK_MCLBYTES     SK_JLEN
1726 #define SK_JPAGESZ      PAGE_SIZE
1727 #define SK_RESID        (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
1728 #define SK_JMEM         ((SK_JLEN * SK_JSLOTS) + SK_RESID)
1729
1730 #define MSK_JSLOTS              ((MSK_RX_RING_CNT / 2) * 3)
1731
1732 #define MSK_RESID       (SK_JPAGESZ - (SK_JLEN * MSK_JSLOTS) % SK_JPAGESZ)
1733 #define MSK_JMEM        ((SK_JLEN * MSK_JSLOTS) + MSK_RESID)
1734
1735 #define SK_MAXUNIT      256
1736 #define SK_TIMEOUT      1000
1737 #define ETHER_ALIGN     2
1738
1739 /* YUKON registers */
1740
1741 /* General Purpose Status Register (GPSR) */
1742 #define YUKON_GPSR              0x0000
1743
1744 #define YU_GPSR_SPEED           0x8000  /* speed 0 - 10Mbps, 1 - 100Mbps */
1745 #define YU_GPSR_DUPLEX          0x4000  /* 0 - half duplex, 1 - full duplex */
1746 #define YU_GPSR_FCTL_TX         0x2000  /* Tx flow control, 1 - disabled */
1747 #define YU_GPSR_LINK            0x1000  /* link status (down/up) */
1748 #define YU_GPSR_PAUSE           0x0800  /* flow control enable/disable */
1749 #define YU_GPSR_TX_IN_PROG      0x0400  /* transmit in progress */
1750 #define YU_GPSR_EXCESS_COL      0x0200  /* excessive collisions occurred */
1751 #define YU_GPSR_LATE_COL        0x0100  /* late collision occurred */
1752 #define YU_GPSR_MII_PHY_STC     0x0020  /* MII PHY status change */
1753 #define YU_GPSR_GIG_SPEED       0x0010  /* Gigabit Speed (0 - use speed bit) */
1754 #define YU_GPSR_PARTITION       0x0008  /* partition mode */
1755 #define YU_GPSR_FCTL_RX         0x0004  /* Rx flow control, 1 - disabled  */
1756 #define YU_GPSR_PROMS_EN        0x0002  /* promiscuous mode, 1 - enabled */
1757
1758 /* General Purpose Control Register (GPCR) */
1759 #define YUKON_GPCR              0x0004
1760
1761 #define YU_GPCR_FCTL_TX_DIS     0x2000  /* Disable Tx flow control 802.3x */
1762 #define YU_GPCR_TXEN            0x1000  /* Transmit Enable */
1763 #define YU_GPCR_RXEN            0x0800  /* Receive Enable */
1764 #define YU_GPCR_BURSTEN         0x0400  /* Burst Mode Enable */
1765 #define YU_GPCR_LPBK            0x0200  /* MAC Loopback Enable */
1766 #define YU_GPCR_PAR             0x0100  /* Partition Enable */
1767 #define YU_GPCR_GIG             0x0080  /* Gigabit Speed 1000Mbps */
1768 #define YU_GPCR_FLP             0x0040  /* Force Link Pass */
1769 #define YU_GPCR_DUPLEX          0x0020  /* Duplex Enable */
1770 #define YU_GPCR_FCTL_RX_DIS     0x0010  /* Disable Rx flow control 802.3x */
1771 #define YU_GPCR_SPEED           0x0008  /* Port Speed 100Mbps */
1772 #define YU_GPCR_DPLX_DIS        0x0004  /* Disable Auto-Update for duplex */
1773 #define YU_GPCR_FCTL_DIS        0x0002  /* Disable Auto-Update for 802.3x */
1774 #define YU_GPCR_SPEED_DIS       0x0001  /* Disable Auto-Update for speed */
1775
1776 /* Transmit Control Register (TCR) */
1777 #define YUKON_TCR               0x0008
1778
1779 #define YU_TCR_FJ               0x8000  /* force jam / flow control */
1780 #define YU_TCR_CRCD             0x4000  /* insert CRC (0 - enable) */
1781 #define YU_TCR_PADD             0x2000  /* pad packets to 64b (0 - enable) */
1782 #define YU_TCR_COLTH            0x1c00  /* collision threshold */
1783
1784 /* Receive Control Register (RCR) */
1785 #define YUKON_RCR               0x000c
1786
1787 #define YU_RCR_UFLEN            0x8000  /* unicast filter enable */
1788 #define YU_RCR_MUFLEN           0x4000  /* multicast filter enable */
1789 #define YU_RCR_CRCR             0x2000  /* remove CRC */
1790 #define YU_RCR_PASSFC           0x1000  /* pass flow control packets */
1791
1792 /* Transmit Flow Control Register (TFCR) */
1793 #define YUKON_TFCR              0x0010  /* Pause Time */
1794
1795 /* Transmit Parameter Register (TPR) */
1796 #define YUKON_TPR               0x0014
1797
1798 #define YU_TPR_JAM_LEN(x)       (((x) & 0x3) << 14)
1799 #define YU_TPR_JAM_IPG(x)       (((x) & 0x1f) << 9)
1800 #define YU_TPR_JAM2DATA_IPG(x)  (((x) & 0x1f) << 4)
1801
1802 /* Serial Mode Register (SMR) */
1803 #define YUKON_SMR               0x0018
1804
1805 #define YU_SMR_DATA_BLIND(x)    (((x) & 0x1f) << 11)
1806 #define YU_SMR_LIMIT4           0x0400  /* reset after 16 / 4 collisions */
1807 #define YU_SMR_MFL_JUMBO        0x0100  /* max frame length for jumbo frames */
1808 #define YU_SMR_MFL_VLAN         0x0200  /* max frame length + vlan tag */
1809 #define YU_SMR_IPG_DATA(x)      ((x) & 0x1f)
1810
1811 /* Source Address Low #1 (SAL1) */
1812 #define YUKON_SAL1              0x001c  /* SA1[15:0] */
1813
1814 /* Source Address Middle #1 (SAM1) */
1815 #define YUKON_SAM1              0x0020  /* SA1[31:16] */
1816
1817 /* Source Address High #1 (SAH1) */
1818 #define YUKON_SAH1              0x0024  /* SA1[47:32] */
1819
1820 /* Source Address Low #2 (SAL2) */
1821 #define YUKON_SAL2              0x0028  /* SA2[15:0] */
1822
1823 /* Source Address Middle #2 (SAM2) */
1824 #define YUKON_SAM2              0x002c  /* SA2[31:16] */
1825
1826 /* Source Address High #2 (SAH2) */
1827 #define YUKON_SAH2              0x0030  /* SA2[47:32] */
1828
1829 /* Multicatst Address Hash Register 1 (MCAH1) */
1830 #define YUKON_MCAH1             0x0034
1831
1832 /* Multicatst Address Hash Register 2 (MCAH2) */
1833 #define YUKON_MCAH2             0x0038
1834
1835 /* Multicatst Address Hash Register 3 (MCAH3) */
1836 #define YUKON_MCAH3             0x003c
1837
1838 /* Multicatst Address Hash Register 4 (MCAH4) */
1839 #define YUKON_MCAH4             0x0040
1840
1841 /* Transmit Interrupt Register (TIR) */
1842 #define YUKON_TIR               0x0044
1843
1844 #define YU_TIR_OUT_UNICAST      0x0001  /* Num Unicast Packets Transmitted */
1845 #define YU_TIR_OUT_BROADCAST    0x0002  /* Num Broadcast Packets Transmitted */
1846 #define YU_TIR_OUT_PAUSE        0x0004  /* Num Pause Packets Transmitted */
1847 #define YU_TIR_OUT_MULTICAST    0x0008  /* Num Multicast Packets Transmitted */
1848 #define YU_TIR_OUT_OCTETS       0x0030  /* Num Bytes Transmitted */
1849 #define YU_TIR_OUT_64_OCTETS    0x0000  /* Num Packets Transmitted */
1850 #define YU_TIR_OUT_127_OCTETS   0x0000  /* Num Packets Transmitted */
1851 #define YU_TIR_OUT_255_OCTETS   0x0000  /* Num Packets Transmitted */
1852 #define YU_TIR_OUT_511_OCTETS   0x0000  /* Num Packets Transmitted */
1853 #define YU_TIR_OUT_1023_OCTETS  0x0000  /* Num Packets Transmitted */
1854 #define YU_TIR_OUT_1518_OCTETS  0x0000  /* Num Packets Transmitted */
1855 #define YU_TIR_OUT_MAX_OCTETS   0x0000  /* Num Packets Transmitted */
1856 #define YU_TIR_OUT_SPARE        0x0000  /* Num Packets Transmitted */
1857 #define YU_TIR_OUT_COLLISIONS   0x0000  /* Num Packets Transmitted */
1858 #define YU_TIR_OUT_LATE         0x0000  /* Num Packets Transmitted */
1859
1860 /* Receive Interrupt Register (RIR) */
1861 #define YUKON_RIR               0x0048
1862
1863 /* Transmit and Receive Interrupt Register (TRIR) */
1864 #define YUKON_TRIR              0x004c
1865
1866 /* Transmit Interrupt Mask Register (TIMR) */
1867 #define YUKON_TIMR              0x0050
1868
1869 /* Receive Interrupt Mask Register (RIMR) */
1870 #define YUKON_RIMR              0x0054
1871
1872 /* Transmit and Receive Interrupt Mask Register (TRIMR) */
1873 #define YUKON_TRIMR             0x0058
1874
1875 /* SMI Control Register (SMICR) */
1876 #define YUKON_SMICR             0x0080
1877
1878 #define YU_SMICR_PHYAD(x)       (((x) & 0x1f) << 11)
1879 #define YU_SMICR_REGAD(x)       (((x) & 0x1f) << 6)
1880 #define YU_SMICR_OPCODE         0x0020  /* opcode (0 - write, 1 - read) */
1881 #define YU_SMICR_OP_READ        0x0020  /* opcode read */
1882 #define YU_SMICR_OP_WRITE       0x0000  /* opcode write */
1883 #define YU_SMICR_READ_VALID     0x0010  /* read valid */
1884 #define YU_SMICR_BUSY           0x0008  /* busy (writing) */
1885
1886 /* SMI Data Register (SMIDR) */
1887 #define YUKON_SMIDR             0x0084
1888
1889 /* PHY Addres Register (PAR) */
1890 #define YUKON_PAR               0x0088
1891
1892 #define YU_PAR_MIB_CLR          0x0020  /* MIB Counters Clear Mode */
1893 #define YU_PAR_LOAD_TSTCNT      0x0010  /* Load count 0xfffffff0 into cntr */
1894
1895 /* Receive status */
1896 #define YU_RXSTAT_FOFL          0x00000001      /* Rx FIFO overflow */
1897 #define YU_RXSTAT_CRCERR        0x00000002      /* CRC error */
1898 #define YU_RXSTAT_FRAGMENT      0x00000008      /* fragment */
1899 #define YU_RXSTAT_LONGERR       0x00000010      /* too long packet */
1900 #define YU_RXSTAT_MIIERR        0x00000020      /* MII error */
1901 #define YU_RXSTAT_BADFC         0x00000040      /* bad flow-control packet */
1902 #define YU_RXSTAT_GOODFC        0x00000080      /* good flow-control packet */
1903 #define YU_RXSTAT_RXOK          0x00000100      /* receice OK (Good packet) */
1904 #define YU_RXSTAT_BROADCAST     0x00000200      /* broadcast packet */
1905 #define YU_RXSTAT_MULTICAST     0x00000400      /* multicast packet */
1906 #define YU_RXSTAT_RUNT          0x00000800      /* undersize packet */
1907 #define YU_RXSTAT_JABBER        0x00001000      /* jabber packet */
1908 #define YU_RXSTAT_VLAN          0x00002000      /* VLAN packet */
1909 #define YU_RXSTAT_LENSHIFT      16
1910
1911 #define YU_RXSTAT_BYTES(x)      ((x) >> YU_RXSTAT_LENSHIFT)
1912
1913 /* Receive status */
1914 #define YU_RXSTAT_FOFL          0x00000001      /* Rx FIFO overflow */
1915 #define YU_RXSTAT_CRCERR        0x00000002      /* CRC error */
1916 #define YU_RXSTAT_FRAGMENT      0x00000008      /* fragment */
1917 #define YU_RXSTAT_LONGERR       0x00000010      /* too long packet */
1918 #define YU_RXSTAT_MIIERR        0x00000020      /* MII error */
1919 #define YU_RXSTAT_BADFC         0x00000040      /* bad flow-control packet */
1920 #define YU_RXSTAT_GOODFC        0x00000080      /* good flow-control packet */
1921 #define YU_RXSTAT_RXOK          0x00000100      /* receice OK (Good packet) */
1922 #define YU_RXSTAT_BROADCAST     0x00000200      /* broadcast packet */
1923 #define YU_RXSTAT_MULTICAST     0x00000400      /* multicast packet */
1924 #define YU_RXSTAT_RUNT          0x00000800      /* undersize packet */
1925 #define YU_RXSTAT_JABBER        0x00001000      /* jabber packet */
1926 #define YU_RXSTAT_VLAN          0x00002000      /* VLAN packet */
1927 #define YU_RXSTAT_LENSHIFT      16
1928
1929 #define YU_RXSTAT_BYTES(x)      ((x) >> YU_RXSTAT_LENSHIFT)
1930
1931 /* Receive status */
1932 #define YU_RXSTAT_FOFL          0x00000001      /* Rx FIFO overflow */
1933 #define YU_RXSTAT_CRCERR        0x00000002      /* CRC error */
1934 #define YU_RXSTAT_FRAGMENT      0x00000008      /* fragment */
1935 #define YU_RXSTAT_LONGERR       0x00000010      /* too long packet */
1936 #define YU_RXSTAT_MIIERR        0x00000020      /* MII error */
1937 #define YU_RXSTAT_BADFC         0x00000040      /* bad flow-control packet */
1938 #define YU_RXSTAT_GOODFC        0x00000080      /* good flow-control packet */
1939 #define YU_RXSTAT_RXOK          0x00000100      /* receice OK (Good packet) */
1940 #define YU_RXSTAT_BROADCAST     0x00000200      /* broadcast packet */
1941 #define YU_RXSTAT_MULTICAST     0x00000400      /* multicast packet */
1942 #define YU_RXSTAT_RUNT          0x00000800      /* undersize packet */
1943 #define YU_RXSTAT_JABBER        0x00001000      /* jabber packet */
1944 #define YU_RXSTAT_VLAN          0x00002000      /* VLAN packet */
1945 #define YU_RXSTAT_LENSHIFT      16
1946
1947 #define YU_RXSTAT_BYTES(x)      ((x) >> YU_RXSTAT_LENSHIFT)
1948
1949 /*
1950  * Registers and data structures for the XaQti Corporation XMAC II
1951  * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com.
1952  * The XMAC can be programmed for 16-bit or 32-bit register access modes.
1953  * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's
1954  * how the registers are laid out here.
1955  */
1956
1957 #define XM_DEVICEID             0x00E0AE20
1958 #define XM_XAQTI_OUI            0x00E0AE
1959
1960 #define XM_XMAC_REV(x)          (((x) & 0x000000E0) >> 5)
1961
1962 #define XM_XMAC_REV_B2          0x0
1963 #define XM_XMAC_REV_C1          0x1
1964
1965 #define XM_MMUCMD               0x0000
1966 #define XM_POFF                 0x0008
1967 #define XM_BURST                0x000C
1968 #define XM_VLAN_TAGLEV1         0x0010
1969 #define XM_VLAN_TAGLEV2         0x0014
1970 #define XM_TXCMD                0x0020
1971 #define XM_TX_RETRYLIMIT        0x0024
1972 #define XM_TX_SLOTTIME          0x0028
1973 #define XM_TX_IPG               0x003C
1974 #define XM_RXCMD                0x0030
1975 #define XM_PHY_ADDR             0x0034
1976 #define XM_PHY_DATA             0x0038
1977 #define XM_GPIO                 0x0040
1978 #define XM_IMR                  0x0044
1979 #define XM_ISR                  0x0048
1980 #define XM_HWCFG                0x004C
1981 #define XM_TX_LOWAT             0x0060
1982 #define XM_TX_HIWAT             0x0062
1983 #define XM_TX_REQTHRESH_LO      0x0064
1984 #define XM_TX_REQTHRESH_HI      0x0066
1985 #define XM_TX_REQTHRESH         XM_TX_REQTHRESH_LO
1986 #define XM_PAUSEDST0            0x0068
1987 #define XM_PAUSEDST1            0x006A
1988 #define XM_PAUSEDST2            0x006C
1989 #define XM_CTLPARM_LO           0x0070
1990 #define XM_CTLPARM_HI           0x0072
1991 #define XM_CTLPARM              XM_CTLPARM_LO
1992 #define XM_OPCODE_PAUSE_TIMER   0x0074
1993 #define XM_TXSTAT_LIFO          0x0078
1994
1995 /*
1996  * Perfect filter registers. The XMAC has a table of 16 perfect
1997  * filter entries, spaced 8 bytes apart. This is in addition to
1998  * the station address registers, which appear below.
1999  */
2000 #define XM_RXFILT_BASE          0x0080
2001 #define XM_RXFILT_END           0x0107
2002 #define XM_RXFILT_MAX           16
2003 #define XM_RXFILT_ENTRY(ent)            (XM_RXFILT_BASE + ((ent * 8)))
2004
2005 /* Primary station address. */
2006 #define XM_PAR0                 0x0108
2007 #define XM_PAR1                 0x010A
2008 #define XM_PAR2                 0x010C
2009
2010 /* 64-bit multicast hash table registers */
2011 #define XM_MAR0                 0x0110
2012 #define XM_MAR1                 0x0112
2013 #define XM_MAR2                 0x0114
2014 #define XM_MAR3                 0x0116
2015 #define XM_RX_LOWAT             0x0118
2016 #define XM_RX_HIWAT             0x011A
2017 #define XM_RX_REQTHRESH_LO      0x011C
2018 #define XM_RX_REQTHRESH_HI      0x011E
2019 #define XM_RX_REQTHRESH         XM_RX_REQTHRESH_LO
2020 #define XM_DEVID_LO             0x0120
2021 #define XM_DEVID_HI             0x0122
2022 #define XM_DEVID                XM_DEVID_LO
2023 #define XM_MODE_LO              0x0124
2024 #define XM_MODE_HI              0x0126
2025 #define XM_MODE                 XM_MODE_LO
2026 #define XM_LASTSRC0             0x0128
2027 #define XM_LASTSRC1             0x012A
2028 #define XM_LASTSRC2             0x012C
2029 #define XM_TSTAMP_READ          0x0130
2030 #define XM_TSTAMP_LOAD          0x0134
2031 #define XM_STATS_CMD            0x0200
2032 #define XM_RXCNT_EVENT_LO       0x0204
2033 #define XM_RXCNT_EVENT_HI       0x0206
2034 #define XM_RXCNT_EVENT          XM_RXCNT_EVENT_LO
2035 #define XM_TXCNT_EVENT_LO       0x0208
2036 #define XM_TXCNT_EVENT_HI       0x020A
2037 #define XM_TXCNT_EVENT          XM_TXCNT_EVENT_LO
2038 #define XM_RXCNT_EVMASK_LO      0x020C
2039 #define XM_RXCNT_EVMASK_HI      0x020E
2040 #define XM_RXCNT_EVMASK         XM_RXCNT_EVMASK_LO
2041 #define XM_TXCNT_EVMASK_LO      0x0210
2042 #define XM_TXCNT_EVMASK_HI      0x0212
2043 #define XM_TXCNT_EVMASK         XM_TXCNT_EVMASK_LO
2044
2045 /* Statistics command register */
2046 #define XM_STATCMD_CLR_TX       0x0001
2047 #define XM_STATCMD_CLR_RX       0x0002
2048 #define XM_STATCMD_COPY_TX      0x0004
2049 #define XM_STATCMD_COPY_RX      0x0008
2050 #define XM_STATCMD_SNAP_TX      0x0010
2051 #define XM_STATCMD_SNAP_RX      0x0020
2052
2053 /* TX statistics registers */
2054 #define XM_TXSTATS_PKTSOK       0x280
2055 #define XM_TXSTATS_BYTESOK_HI   0x284
2056 #define XM_TXSTATS_BYTESOK_LO   0x288
2057 #define XM_TXSTATS_BCASTSOK     0x28C
2058 #define XM_TXSTATS_MCASTSOK     0x290
2059 #define XM_TXSTATS_UCASTSOK     0x294
2060 #define XM_TXSTATS_GIANTS       0x298
2061 #define XM_TXSTATS_BURSTCNT     0x29C
2062 #define XM_TXSTATS_PAUSEPKTS    0x2A0
2063 #define XM_TXSTATS_MACCTLPKTS   0x2A4
2064 #define XM_TXSTATS_SINGLECOLS   0x2A8
2065 #define XM_TXSTATS_MULTICOLS    0x2AC
2066 #define XM_TXSTATS_EXCESSCOLS   0x2B0
2067 #define XM_TXSTATS_LATECOLS     0x2B4
2068 #define XM_TXSTATS_DEFER        0x2B8
2069 #define XM_TXSTATS_EXCESSDEFER  0x2BC
2070 #define XM_TXSTATS_UNDERRUN     0x2C0
2071 #define XM_TXSTATS_CARRIERSENSE 0x2C4
2072 #define XM_TXSTATS_UTILIZATION  0x2C8
2073 #define XM_TXSTATS_64           0x2D0
2074 #define XM_TXSTATS_65_127       0x2D4
2075 #define XM_TXSTATS_128_255      0x2D8
2076 #define XM_TXSTATS_256_511      0x2DC
2077 #define XM_TXSTATS_512_1023     0x2E0
2078 #define XM_TXSTATS_1024_MAX     0x2E4
2079
2080 /* RX statistics registers */
2081 #define XM_RXSTATS_PKTSOK       0x300
2082 #define XM_RXSTATS_BYTESOK_HI   0x304
2083 #define XM_RXSTATS_BYTESOK_LO   0x308
2084 #define XM_RXSTATS_BCASTSOK     0x30C
2085 #define XM_RXSTATS_MCASTSOK     0x310
2086 #define XM_RXSTATS_UCASTSOK     0x314
2087 #define XM_RXSTATS_PAUSEPKTS    0x318
2088 #define XM_RXSTATS_MACCTLPKTS   0x31C
2089 #define XM_RXSTATS_BADPAUSEPKTS 0x320
2090 #define XM_RXSTATS_BADMACCTLPKTS        0x324
2091 #define XM_RXSTATS_BURSTCNT     0x328
2092 #define XM_RXSTATS_MISSEDPKTS   0x32C
2093 #define XM_RXSTATS_FRAMEERRS    0x330
2094 #define XM_RXSTATS_OVERRUN      0x334
2095 #define XM_RXSTATS_JABBER       0x338
2096 #define XM_RXSTATS_CARRLOSS     0x33C
2097 #define XM_RXSTATS_INRNGLENERR  0x340
2098 #define XM_RXSTATS_SYMERR       0x344
2099 #define XM_RXSTATS_SHORTEVENT   0x348
2100 #define XM_RXSTATS_RUNTS        0x34C
2101 #define XM_RXSTATS_GIANTS       0x350
2102 #define XM_RXSTATS_CRCERRS      0x354
2103 #define XM_RXSTATS_CEXTERRS     0x35C
2104 #define XM_RXSTATS_UTILIZATION  0x360
2105 #define XM_RXSTATS_64           0x368
2106 #define XM_RXSTATS_65_127       0x36C
2107 #define XM_RXSTATS_128_255      0x370
2108 #define XM_RXSTATS_256_511      0x374
2109 #define XM_RXSTATS_512_1023     0x378
2110 #define XM_RXSTATS_1024_MAX     0x37C
2111
2112 #define XM_MMUCMD_TX_ENB        0x0001
2113 #define XM_MMUCMD_RX_ENB        0x0002
2114 #define XM_MMUCMD_GMIILOOP      0x0004
2115 #define XM_MMUCMD_RATECTL       0x0008
2116 #define XM_MMUCMD_GMIIFDX       0x0010
2117 #define XM_MMUCMD_NO_MGMT_PRMB  0x0020
2118 #define XM_MMUCMD_SIMCOL        0x0040
2119 #define XM_MMUCMD_FORCETX       0x0080
2120 #define XM_MMUCMD_LOOPENB       0x0200
2121 #define XM_MMUCMD_IGNPAUSE      0x0400
2122 #define XM_MMUCMD_PHYBUSY       0x0800
2123 #define XM_MMUCMD_PHYDATARDY    0x1000
2124
2125 #define XM_TXCMD_AUTOPAD        0x0001
2126 #define XM_TXCMD_NOCRC          0x0002
2127 #define XM_TXCMD_NOPREAMBLE     0x0004
2128 #define XM_TXCMD_NOGIGAMODE     0x0008
2129 #define XM_TXCMD_SAMPLELINE     0x0010
2130 #define XM_TXCMD_ENCBYPASS      0x0020
2131 #define XM_TXCMD_XMITBK2BK      0x0040
2132 #define XM_TXCMD_FAIRSHARE      0x0080
2133
2134 #define XM_RXCMD_DISABLE_CEXT   0x0001
2135 #define XM_RXCMD_STRIPPAD       0x0002
2136 #define XM_RXCMD_SAMPLELINE     0x0004
2137 #define XM_RXCMD_SELFRX         0x0008
2138 #define XM_RXCMD_STRIPFCS       0x0010
2139 #define XM_RXCMD_TRANSPARENT    0x0020
2140 #define XM_RXCMD_IPGCAPTURE     0x0040
2141 #define XM_RXCMD_BIGPKTOK       0x0080
2142 #define XM_RXCMD_LENERROK       0x0100
2143
2144 #define XM_GPIO_GP0_SET         0x0001
2145 #define XM_GPIO_RESETSTATS      0x0004
2146 #define XM_GPIO_RESETMAC        0x0008
2147 #define XM_GPIO_FORCEINT        0x0020
2148 #define XM_GPIO_ANEGINPROG      0x0040
2149
2150 #define XM_IMR_RX_EOF           0x0001
2151 #define XM_IMR_TX_EOF           0x0002
2152 #define XM_IMR_TX_UNDERRUN      0x0004
2153 #define XM_IMR_RX_OVERRUN       0x0008
2154 #define XM_IMR_TX_STATS_OFLOW   0x0010
2155 #define XM_IMR_RX_STATS_OFLOW   0x0020
2156 #define XM_IMR_TSTAMP_OFLOW     0x0040
2157 #define XM_IMR_AUTONEG_DONE     0x0080
2158 #define XM_IMR_NEXTPAGE_RDY     0x0100
2159 #define XM_IMR_PAGE_RECEIVED    0x0200
2160 #define XM_IMR_LP_REQCFG        0x0400
2161 #define XM_IMR_GP0_SET          0x0800
2162 #define XM_IMR_FORCEINTR        0x1000
2163 #define XM_IMR_TX_ABORT         0x2000
2164 #define XM_IMR_LINKEVENT        0x4000
2165
2166 #define XM_INTRS        \
2167         (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN))
2168
2169 #define XM_ISR_RX_EOF           0x0001
2170 #define XM_ISR_TX_EOF           0x0002
2171 #define XM_ISR_TX_UNDERRUN      0x0004
2172 #define XM_ISR_RX_OVERRUN       0x0008
2173 #define XM_ISR_TX_STATS_OFLOW   0x0010
2174 #define XM_ISR_RX_STATS_OFLOW   0x0020
2175 #define XM_ISR_TSTAMP_OFLOW     0x0040
2176 #define XM_ISR_AUTONEG_DONE     0x0080
2177 #define XM_ISR_NEXTPAGE_RDY     0x0100
2178 #define XM_ISR_PAGE_RECEIVED    0x0200
2179 #define XM_ISR_LP_REQCFG        0x0400
2180 #define XM_ISR_GP0_SET          0x0800
2181 #define XM_ISR_FORCEINTR        0x1000
2182 #define XM_ISR_TX_ABORT         0x2000
2183 #define XM_ISR_LINKEVENT        0x4000
2184
2185 #define XM_HWCFG_GENEOP         0x0008
2186 #define XM_HWCFG_SIGSTATCKH     0x0004
2187 #define XM_HWCFG_GMIIMODE       0x0001
2188
2189 #define XM_MODE_FLUSH_RXFIFO    0x00000001
2190 #define XM_MODE_FLUSH_TXFIFO    0x00000002
2191 #define XM_MODE_BIGENDIAN       0x00000004
2192 #define XM_MODE_RX_PROMISC      0x00000008
2193 #define XM_MODE_RX_NOBROAD      0x00000010
2194 #define XM_MODE_RX_NOMULTI      0x00000020
2195 #define XM_MODE_RX_NOUNI        0x00000040
2196 #define XM_MODE_RX_BADFRAMES    0x00000080
2197 #define XM_MODE_RX_CRCERRS      0x00000100
2198 #define XM_MODE_RX_GIANTS       0x00000200
2199 #define XM_MODE_RX_INRANGELEN   0x00000400
2200 #define XM_MODE_RX_RUNTS        0x00000800
2201 #define XM_MODE_RX_MACCTL       0x00001000
2202 #define XM_MODE_RX_USE_PERFECT  0x00002000
2203 #define XM_MODE_RX_USE_STATION  0x00004000
2204 #define XM_MODE_RX_USE_HASH     0x00008000
2205 #define XM_MODE_RX_ADDRPAIR     0x00010000
2206 #define XM_MODE_PAUSEONHI       0x00020000
2207 #define XM_MODE_PAUSEONLO       0x00040000
2208 #define XM_MODE_TIMESTAMP       0x00080000
2209 #define XM_MODE_SENDPAUSE       0x00100000
2210 #define XM_MODE_SENDCONTINUOUS  0x00200000
2211 #define XM_MODE_LE_STATUSWORD   0x00400000
2212 #define XM_MODE_AUTOFIFOPAUSE   0x00800000
2213 #define XM_MODE_EXPAUSEGEN      0x02000000
2214 #define XM_MODE_RX_INVERSE      0x04000000
2215
2216 #define XM_RXSTAT_MACCTL        0x00000001
2217 #define XM_RXSTAT_ERRFRAME      0x00000002
2218 #define XM_RXSTAT_CRCERR        0x00000004
2219 #define XM_RXSTAT_GIANT         0x00000008
2220 #define XM_RXSTAT_RUNT          0x00000010
2221 #define XM_RXSTAT_FRAMEERR      0x00000020
2222 #define XM_RXSTAT_INRANGEERR    0x00000040
2223 #define XM_RXSTAT_CARRIERERR    0x00000080
2224 #define XM_RXSTAT_COLLERR       0x00000100
2225 #define XM_RXSTAT_802_3         0x00000200
2226 #define XM_RXSTAT_CARREXTERR    0x00000400
2227 #define XM_RXSTAT_BURSTMODE     0x00000800
2228 #define XM_RXSTAT_UNICAST       0x00002000
2229 #define XM_RXSTAT_MULTICAST     0x00004000
2230 #define XM_RXSTAT_BROADCAST     0x00008000
2231 #define XM_RXSTAT_VLAN_LEV1     0x00010000
2232 #define XM_RXSTAT_VLAN_LEV2     0x00020000
2233 #define XM_RXSTAT_LEN           0xFFFC0000
2234 #define XM_RXSTAT_LENSHIFT      18
2235
2236 #define XM_RXSTAT_BYTES(x)      ((x) >> XM_RXSTAT_LENSHIFT)
2237
2238 /*
2239  * XMAC PHY registers, indirectly accessed through
2240  * XM_PHY_ADDR and XM_PHY_REG.
2241  */
2242
2243 #define XM_PHY_BMCR             0x0000  /* control */
2244 #define XM_PHY_BMSR             0x0001  /* status */
2245 #define XM_PHY_VENID            0x0002  /* vendor id */
2246 #define XM_PHY_DEVID            0x0003  /* device id */
2247 #define XM_PHY_ANAR             0x0004  /* autoneg advertisenemt */
2248 #define XM_PHY_LPAR             0x0005  /* link partner ability */
2249 #define XM_PHY_ANEXP            0x0006  /* autoneg expansion */
2250 #define XM_PHY_NEXTP            0x0007  /* nextpage */
2251 #define XM_PHY_LPNEXTP          0x0008  /* link partner's nextpage */
2252 #define XM_PHY_EXTSTS           0x000F  /* extented status */
2253 #define XM_PHY_RESAB            0x0010  /* resolved ability */
2254
2255 #define XM_BMCR_DUPLEX          0x0100
2256 #define XM_BMCR_RENEGOTIATE     0x0200
2257 #define XM_BMCR_AUTONEGENBL     0x1000
2258 #define XM_BMCR_LOOPBACK        0x4000
2259 #define XM_BMCR_RESET           0x8000
2260
2261 #define XM_BMSR_EXTCAP          0x0001
2262 #define XM_BMSR_LINKSTAT        0x0004
2263 #define XM_BMSR_AUTONEGABLE     0x0008
2264 #define XM_BMSR_REMFAULT        0x0010
2265 #define XM_BMSR_AUTONEGDONE     0x0020
2266 #define XM_BMSR_EXTSTAT         0x0100
2267
2268 #define XM_VENID_XAQTI          0xD14C
2269 #define XM_DEVID_XMAC           0x0002
2270
2271 #define XM_ANAR_FULLDUPLEX      0x0020
2272 #define XM_ANAR_HALFDUPLEX      0x0040
2273 #define XM_ANAR_PAUSEBITS       0x0180
2274 #define XM_ANAR_REMFAULTBITS    0x1800
2275 #define XM_ANAR_ACK             0x4000
2276 #define XM_ANAR_NEXTPAGE        0x8000
2277
2278 #define XM_LPAR_FULLDUPLEX      0x0020
2279 #define XM_LPAR_HALFDUPLEX      0x0040
2280 #define XM_LPAR_PAUSEBITS       0x0180
2281 #define XM_LPAR_REMFAULTBITS    0x1800
2282 #define XM_LPAR_ACK             0x4000
2283 #define XM_LPAR_NEXTPAGE        0x8000
2284
2285 #define XM_PAUSE_NOPAUSE        0x0000
2286 #define XM_PAUSE_SYMPAUSE       0x0080
2287 #define XM_PAUSE_ASYMPAUSE      0x0100
2288 #define XM_PAUSE_BOTH           0x0180
2289
2290 #define XM_REMFAULT_LINKOK      0x0000
2291 #define XM_REMFAULT_LINKFAIL    0x0800
2292 #define XM_REMFAULT_OFFLINE     0x1000
2293 #define XM_REMFAULT_ANEGERR     0x1800
2294
2295 #define XM_ANEXP_GOTPAGE        0x0002
2296 #define XM_ANEXP_NEXTPAGE_SELF  0x0004
2297 #define XM_ANEXP_NEXTPAGE_LP    0x0008
2298
2299 #define XM_NEXTP_MESSAGE        0x07FF
2300 #define XM_NEXTP_TOGGLE         0x0800
2301 #define XM_NEXTP_ACK2           0x1000
2302 #define XM_NEXTP_MPAGE          0x2000
2303 #define XM_NEXTP_ACK1           0x4000
2304 #define XM_NEXTP_NPAGE          0x8000
2305
2306 #define XM_LPNEXTP_MESSAGE      0x07FF
2307 #define XM_LPNEXTP_TOGGLE       0x0800
2308 #define XM_LPNEXTP_ACK2         0x1000
2309 #define XM_LPNEXTP_MPAGE        0x2000
2310 #define XM_LPNEXTP_ACK1         0x4000
2311 #define XM_LPNEXTP_NPAGE        0x8000
2312
2313 #define XM_EXTSTS_HALFDUPLEX    0x4000
2314 #define XM_EXTSTS_FULLDUPLEX    0x8000
2315
2316 #define XM_RESAB_PAUSEMISMATCH  0x0008
2317 #define XM_RESAB_ABLMISMATCH    0x0010
2318 #define XM_RESAB_FDMODESEL      0x0020
2319 #define XM_RESAB_HDMODESEL      0x0040
2320 #define XM_RESAB_PAUSEBITS      0x0180
2321 #endif /* _DEV_PCI_IF_SKREG_H_ */