1 /* $NetBSD: if_tlvar.h,v 1.13 2008/06/01 00:38:29 tsutsui Exp $ */
4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Texas Instruments ThunderLAN ethernet controller
29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A)
30 * available from www.ti.com
39 #include <dev/i2c/i2cvar.h>
41 struct tl_product_desc
{
48 device_t sc_dev
; /* base device */
49 bus_space_tag_t tl_bustag
;
50 bus_space_handle_t tl_bushandle
; /* CSR region handle */
51 bus_dma_tag_t tl_dmatag
;
52 const struct tl_product_desc
*tl_product
;
54 struct ethercom tl_ec
;
55 struct callout tl_tick_ch
; /* tick callout */
56 struct callout tl_restart_ch
; /* restart callout */
57 u_int8_t tl_enaddr
[ETHER_ADDR_LEN
]; /* hardware address */
58 struct i2c_controller sc_i2c
; /* i2c controller info, for eeprom */
59 mii_data_t tl_mii
; /* mii bus */
60 bus_dma_segment_t ctrl_segs
; /* bus-dma memory for control blocks */
62 char *ctrl
; /* vaddr for ctrl_segs */
63 struct Rx_list
*Rx_list
; /* Receive and transmit lists */
64 struct tl_Rx_list
*hw_Rx_list
; /* and assocoated hw descriptor */
65 bus_dmamap_t Rx_dmamap
; /* and associated DMA maps */
66 struct Tx_list
*Tx_list
;
67 struct tl_Tx_list
*hw_Tx_list
;
68 bus_dmamap_t Tx_dmamap
;
69 struct Rx_list
*active_Rx
, *last_Rx
;
70 struct Tx_list
*active_Tx
, *last_Tx
;
71 struct Tx_list
*Free_Tx
;
72 bus_dmamap_t null_dmamap
; /* for small packets padding */
88 rndsource_element_t rnd_source
;
91 #define tl_if tl_ec.ec_if
92 #define tl_bpf tl_if.if_bpf
94 typedef struct tl_softc tl_softc_t
;
95 typedef u_long ioctl_cmd_t
;
97 #define TL_HR_READ(sc, reg) \
98 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg))
99 #define TL_HR_READ_BYTE(sc, reg) \
100 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg))
101 #define TL_HR_WRITE(sc, reg, data) \
102 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data))
103 #define TL_HR_WRITE_BYTE(sc, reg, data) \
104 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data))
105 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header))