1 /* $NetBSD: if_wmreg.h,v 1.30 2010/01/05 10:02:01 msaitoh Exp $ */
4 * Copyright (c) 2001 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Register description for the Intel i82542 (``Wiseman''),
40 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit
45 * The wiseman supports 64-bit PCI addressing. This structure
46 * describes the address in descriptors.
48 typedef struct wiseman_addr
{
49 uint32_t wa_low
; /* low-order 32 bits */
50 uint32_t wa_high
; /* high-order 32 bits */
51 } __packed wiseman_addr_t
;
54 * The Wiseman receive descriptor.
56 * The receive descriptor ring must be aligned to a 4K boundary,
57 * and there must be an even multiple of 8 descriptors in the ring.
59 typedef struct wiseman_rxdesc
{
60 wiseman_addr_t wrx_addr
; /* buffer address */
62 uint16_t wrx_len
; /* buffer length */
63 uint16_t wrx_cksum
; /* checksum (starting at PCSS) */
65 uint8_t wrx_status
; /* Rx status */
66 uint8_t wrx_errors
; /* Rx errors */
67 uint16_t wrx_special
; /* special field (VLAN, etc.) */
68 } __packed wiseman_rxdesc_t
;
71 #define WRX_ST_DD (1U << 0) /* descriptor done */
72 #define WRX_ST_EOP (1U << 1) /* end of packet */
73 #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */
74 #define WRX_ST_VP (1U << 3) /* VLAN packet */
75 #define WRX_ST_BPDU (1U << 4) /* ??? */
76 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */
77 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */
78 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */
81 #define WRX_ER_CE (1U << 0) /* CRC error */
82 #define WRX_ER_SE (1U << 1) /* symbol error */
83 #define WRX_ER_SEQ (1U << 2) /* sequence error */
84 #define WRX_ER_ICE (1U << 3) /* ??? */
85 #define WRX_ER_CXE (1U << 4) /* carrier extension error */
86 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */
87 #define WRX_ER_IPE (1U << 6) /* IP checksum error */
88 #define WRX_ER_RXE (1U << 7) /* Rx data error */
90 /* wrx_special field for VLAN packets */
91 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */
92 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */
93 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */
96 * The Wiseman transmit descriptor.
98 * The transmit descriptor ring must be aligned to a 4K boundary,
99 * and there must be an even multiple of 8 descriptors in the ring.
101 typedef struct wiseman_tx_fields
{
102 uint8_t wtxu_status
; /* Tx status */
103 uint8_t wtxu_options
; /* options */
104 uint16_t wtxu_vlan
; /* VLAN info */
105 } __packed wiseman_txfields_t
;
106 typedef struct wiseman_txdesc
{
107 wiseman_addr_t wtx_addr
; /* buffer address */
108 uint32_t wtx_cmdlen
; /* command and length */
109 wiseman_txfields_t wtx_fields
; /* fields; see below */
110 } __packed wiseman_txdesc_t
;
112 /* Commands for wtx_cmdlen */
113 #define WTX_CMD_EOP (1U << 24) /* end of packet */
114 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */
115 #define WTX_CMD_RS (1U << 27) /* report status */
116 #define WTX_CMD_RPS (1U << 28) /* report packet sent */
117 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */
118 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */
119 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */
121 /* Descriptor types (if DEXT is set) */
122 #define WTX_DTYP_C (0U << 20) /* context */
123 #define WTX_DTYP_D (1U << 20) /* data */
125 /* wtx_fields status bits */
126 #define WTX_ST_DD (1U << 0) /* descriptor done */
127 #define WTX_ST_EC (1U << 1) /* excessive collisions */
128 #define WTX_ST_LC (1U << 2) /* late collision */
129 #define WTX_ST_TU (1U << 3) /* transmit underrun */
131 /* wtx_fields option bits for IP/TCP/UDP checksum offload */
132 #define WTX_IXSM (1U << 0) /* IP checksum offload */
133 #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */
135 /* Maximum payload per Tx descriptor */
136 #define WTX_MAX_LEN 4096
139 * The Livengood TCP/IP context descriptor.
141 struct livengood_tcpip_ctxdesc
{
142 uint32_t tcpip_ipcs
; /* IP checksum context */
143 uint32_t tcpip_tucs
; /* TCP/UDP checksum context */
144 uint32_t tcpip_cmdlen
;
145 uint32_t tcpip_seg
; /* TCP segmentation context */
148 /* commands for context descriptors */
149 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */
150 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */
151 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */
153 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */
154 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */
155 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */
157 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */
158 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */
159 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */
161 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0)
162 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8)
163 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16)
166 * PCI config registers used by the Wiseman.
168 #define WM_PCI_MMBA PCI_MAPREG_START
169 /* registers for FLASH access on ICH8 */
170 #define WM_ICH8_FLASH 0x0014
173 * Wiseman Control/Status Registers.
175 #define WMREG_CTRL 0x0000 /* Device Control Register */
176 #define CTRL_FD (1U << 0) /* full duplex */
177 #define CTRL_BEM (1U << 1) /* big-endian mode */
178 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */
179 #define CTRL_LRST (1U << 3) /* link reset */
180 #define CTRL_GIO_M_DIS (1U << 3) /* disabl PCI master access */
181 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */
182 #define CTRL_SLU (1U << 6) /* set link up */
183 #define CTRL_ILOS (1U << 7) /* invert loss of signal */
184 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */
185 #define CTRL_SPEED_10 CTRL_SPEED(0)
186 #define CTRL_SPEED_100 CTRL_SPEED(1)
187 #define CTRL_SPEED_1000 CTRL_SPEED(2)
188 #define CTRL_SPEED_MASK CTRL_SPEED(3)
189 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */
190 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */
191 #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */
192 #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */
193 #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */
194 #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */
195 #define CTRL_SWDPINS_SHIFT 18
196 #define CTRL_SWDPINS_MASK 0x0f
197 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x)))
198 #define CTRL_SWDPIO_SHIFT 22
199 #define CTRL_SWDPIO_MASK 0x0f
200 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x)))
201 #define CTRL_RST (1U << 26) /* device reset */
202 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */
203 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */
204 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */
205 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */
207 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */
209 #define WMREG_STATUS 0x0008 /* Device Status Register */
210 #define STATUS_FD (1U << 0) /* full duplex */
211 #define STATUS_LU (1U << 1) /* link up */
212 #define STATUS_TCKOK (1U << 2) /* Tx clock running */
213 #define STATUS_RBCOK (1U << 3) /* Rx clock running */
214 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */
215 #define STATUS_FUNCID_MASK 3 /* ... */
216 #define STATUS_TXOFF (1U << 4) /* Tx paused */
217 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */
218 #define STATUS_SPEED(x) ((x) << 6) /* speed indication */
219 #define STATUS_SPEED_10 STATUS_SPEED(0)
220 #define STATUS_SPEED_100 STATUS_SPEED(1)
221 #define STATUS_SPEED_1000 STATUS_SPEED(2)
222 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */
223 #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */
224 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */
225 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */
226 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */
227 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */
228 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */
229 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0)
230 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1)
231 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
232 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3)
233 #define STATUS_GIO_M_ENA (1U << 16) /* PCIX master enable */
235 #define WMREG_EECD 0x0010 /* EEPROM Control Register */
236 #define EECD_SK (1U << 0) /* clock */
237 #define EECD_CS (1U << 1) /* chip select */
238 #define EECD_DI (1U << 2) /* data in */
239 #define EECD_DO (1U << 3) /* data out */
240 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */
241 #define EECD_FWE_DISABLED EECD_FWE(1)
242 #define EECD_FWE_ENABLED EECD_FWE(2)
243 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */
244 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */
245 #define EECD_EE_PRES (1U << 8) /* EEPROM present */
246 #define EECD_EE_SIZE (1U << 9) /* EEPROM size
247 (0 = 64 word, 1 = 256 word) */
248 #define EECD_EE_AUTORD (1U << 9) /* auto read done */
249 #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits
251 #define EECD_EE_TYPE (1U << 13) /* EEPROM type
252 (0 = Microwire, 1 = SPI) */
253 #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */
255 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */
256 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */
257 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */
259 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */
260 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */
261 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */
262 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */
263 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */
264 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */
265 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */
266 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */
268 #define SPI_SR_RDY 0x01
269 #define SPI_SR_WEN 0x02
270 #define SPI_SR_BP0 0x04
271 #define SPI_SR_BP1 0x08
272 #define SPI_SR_WPEN 0x80
274 #define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */
275 #define EEPROM_OFF_CFG1 0x0a /* config word 1 */
276 #define EEPROM_OFF_CFG2 0x0f /* config word 2 */
277 #define EEPROM_INIT_3GIO_3 0x1a /* PCIe Initial Configuration Word 3 */
278 #define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */
280 #define EEPROM_CFG1_LVDID (1U << 0)
281 #define EEPROM_CFG1_LSSID (1U << 1)
282 #define EEPROM_CFG1_PME_CLOCK (1U << 2)
283 #define EEPROM_CFG1_PM (1U << 3)
284 #define EEPROM_CFG1_ILOS (1U << 4)
285 #define EEPROM_CFG1_SWDPIO_SHIFT 5
286 #define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT)
287 #define EEPROM_CFG1_IPS1 (1U << 8)
288 #define EEPROM_CFG1_LRST (1U << 9)
289 #define EEPROM_CFG1_FD (1U << 10)
290 #define EEPROM_CFG1_FRCSPD (1U << 11)
291 #define EEPROM_CFG1_IPS0 (1U << 12)
292 #define EEPROM_CFG1_64_32_BAR (1U << 13)
294 #define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1)
295 #define EEPROM_CFG2_APM_EN (1U << 2)
296 #define EEPROM_CFG2_64_BIT (1U << 3)
297 #define EEPROM_CFG2_MAX_READ (1U << 4)
298 #define EEPROM_CFG2_DMCR_MAP (1U << 5)
299 #define EEPROM_CFG2_133_CAP (1U << 6)
300 #define EEPROM_CFG2_MSI_DIS (1U << 7)
301 #define EEPROM_CFG2_FLASH_DIS (1U << 8)
302 #define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9)
303 #define EEPROM_CFG2_ANE (1U << 11)
304 #define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12)
305 #define EEPROM_CFG2_ASDE (1U << 14)
306 #define EEPROM_CFG2_APM_PME (1U << 15)
307 #define EEPROM_CFG2_SWDPIO_SHIFT 4
308 #define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT)
309 #define EEPROM_CFG2_MNGM_MASK (3U << 13) /* Manageability Operation mode */
311 #define EEPROM_SWDPIN_MASK 0xdf
312 #define EEPROM_SWDPIN_SWDPIN_SHIFT 0
313 #define EEPROM_SWDPIN_SWDPIO_SHIFT 8
315 #define EEPROM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */
317 #define WMREG_EERD 0x0014 /* EEPROM read */
318 #define EERD_DONE 0x02 /* done bit */
319 #define EERD_START 0x01 /* First bit for telling part to start operation */
320 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */
321 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */
323 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */
324 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */
325 #define CTRL_EXT_SWDPINS_SHIFT 4
326 #define CTRL_EXT_SWDPINS_MASK 0x0d
327 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4))
328 #define CTRL_EXT_SWDPIO_SHIFT 8
329 #define CTRL_EXT_SWDPIO_MASK 0x0d
330 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4))
331 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */
332 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */
333 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */
334 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */
335 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */
336 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */
337 #define CTRL_EXT_LINK_MODE_MASK 0x00C00000
338 #define CTRL_EXT_LINK_MODE_GMII 0x00000000
339 #define CTRL_EXT_LINK_MODE_TBI 0x00C00000
340 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000
341 #define CTRL_EXT_LINK_MODE_SERDES 0x00C00000
342 #define CTRL_EXT_DRV_LOAD 0x10000000
345 #define WMREG_MDIC 0x0020 /* MDI Control Register */
346 #define MDIC_DATA(x) ((x) & 0xffff)
347 #define MDIC_REGADD(x) ((x) << 16)
348 #define MDIC_PHYADD(x) ((x) << 21)
349 #define MDIC_OP_WRITE (1U << 26)
350 #define MDIC_OP_READ (2U << 26)
351 #define MDIC_READY (1U << 28)
352 #define MDIC_I (1U << 29) /* interrupt on MDI complete */
353 #define MDIC_E (1U << 30) /* MDI error */
355 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */
356 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */
358 #define WMREG_FCAH 0x002c /* Flow Control Address High */
359 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */
361 #define WMREG_FCT 0x0030 /* Flow Control Type */
363 #define WMREG_VET 0x0038 /* VLAN Ethertype */
365 #define WMREG_RAL_BASE 0x0040 /* Receive Address List */
366 #define WMREG_CORDOVA_RAL_BASE 0x5400
367 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3))
368 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4)
370 * Receive Address List: The LO part is the low-order 32-bits
371 * of the MAC address. The HI part is the high-order 16-bits
372 * along with a few control bits.
374 #define RAL_AS(x) ((x) << 16) /* address select */
375 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */
376 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */
377 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */
378 #define RAL_AV (1U << 31) /* entry is valid */
380 #define WM_RAL_TABSIZE 16
381 #define WM_ICH8_RAL_TABSIZE 7
383 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */
384 #define ICR_TXDW (1U << 0) /* Tx desc written back */
385 #define ICR_TXQE (1U << 1) /* Tx queue empty */
386 #define ICR_LSC (1U << 2) /* link status change */
387 #define ICR_RXSEQ (1U << 3) /* receive sequence error */
388 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */
389 #define ICR_RXO (1U << 6) /* Rx overrun */
390 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */
391 #define ICR_MDAC (1U << 9) /* MDIO access complete */
392 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */
393 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */
394 #define ICR_INT (1U << 31) /* device generated an interrupt */
396 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */
397 #define ITR_IVAL_MASK 0xffff /* Interval mask */
398 #define ITR_IVAL_SHIFT 0 /* Interval shift */
400 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */
403 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */
406 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */
409 #define WMREG_RCTL 0x0100 /* Receive Control */
410 #define RCTL_EN (1U << 1) /* receiver enable */
411 #define RCTL_SBP (1U << 2) /* store bad packets */
412 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */
413 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */
414 #define RCTL_LPE (1U << 5) /* large packet enable */
415 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */
416 #define RCTL_LBM_NONE RCTL_LBM(0)
417 #define RCTL_LBM_PHY RCTL_LBM(3)
418 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */
419 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0)
420 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1)
421 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2)
422 #define RCTL_RDMTS_MASK RCTL_RDMTS(3)
423 #define RCTL_MO(x) ((x) << 12) /* multicast offset */
424 #define RCTL_BAM (1U << 15) /* broadcast accept mode */
425 #define RCTL_2k (0 << 16) /* 2k Rx buffers */
426 #define RCTL_1k (1 << 16) /* 1k Rx buffers */
427 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */
428 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */
429 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */
430 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */
431 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */
432 #define RCTL_DPF (1U << 22) /* discard pause frames */
433 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */
434 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */
435 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */
437 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */
438 #define WMREG_RDTR 0x2820
439 #define RDTR_FPD (1U << 31) /* flush partial descriptor */
441 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */
443 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */
444 #define WMREG_RDBAL 0x2800
446 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */
447 #define WMREG_RDBAH 0x2804
449 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */
450 #define WMREG_RDLEN 0x2808
452 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */
453 #define WMREG_RDH 0x2810
455 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */
456 #define WMREG_RDT 0x2818
458 #define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */
459 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
460 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
461 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
462 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */
464 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */
466 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */
468 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */
470 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */
472 #define WMREG_OLD_RDH1 0x0148
474 #define WMREG_OLD_RDT1 0x0150
476 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */
477 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */
478 #define FCRTH_DFLT 0x00008000
480 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */
481 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */
482 #define FCRTL_DFLT 0x00004000
483 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
485 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */
486 #define FCTTV_DFLT 0x00000600
488 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */
489 /* See MII ANAR_X bits. */
490 #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */
491 #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */
492 #define TXCW_TxConfig (1U << 30) /* Tx Config */
493 #define TXCW_ANE (1U << 31) /* Autonegotiate */
495 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */
496 /* See MII ANLPAR_X bits. */
497 #define RXCW_NC (1U << 26) /* no carrier */
498 #define RXCW_IV (1U << 27) /* config invalid */
499 #define RXCW_CC (1U << 28) /* config change */
500 #define RXCW_C (1U << 29) /* /C/ reception */
501 #define RXCW_SYNCH (1U << 30) /* synchronized */
502 #define RXCW_ANC (1U << 31) /* autonegotiation complete */
504 #define WMREG_MTA 0x0200 /* Multicast Table Array */
505 #define WMREG_CORDOVA_MTA 0x5200
507 #define WMREG_TCTL 0x0400 /* Transmit Control Register */
508 #define TCTL_EN (1U << 1) /* transmitter enable */
509 #define TCTL_PSP (1U << 3) /* pad short packets */
510 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */
511 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */
512 #define TCTL_SWXOFF (1U << 22) /* software XOFF */
513 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */
514 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */
515 #define TCTL_MULR (1U << 28) /* multiple request */
517 #define TX_COLLISION_THRESHOLD 15
518 #define TX_COLLISION_DISTANCE_HDX 512
519 #define TX_COLLISION_DISTANCE_FDX 64
521 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */
522 #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
523 #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
525 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
527 #define WMREG_TQSA_LO 0x0408
529 #define WMREG_TQSA_HI 0x040c
531 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */
532 #define TIPG_IPGT(x) (x) /* IPG transmit time */
533 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */
534 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */
536 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a))
537 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
538 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06))
539 #define TIPG_1000T_80003_DFLT \
540 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
541 #define TIPG_10_100_80003_DFLT \
542 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07))
544 #define WMREG_TQC 0x0418
546 #define WMREG_EEWR 0x102c /* EEPROM write */
548 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */
550 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */
552 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */
554 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */
556 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */
558 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */
560 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */
562 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */
564 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */
566 #define WMREG_OLD_TBDAL 0x0420 /* Transmit Descriptor Base Lo */
567 #define WMREG_TBDAL 0x3800
569 #define WMREG_OLD_TBDAH 0x0424 /* Transmit Descriptor Base Hi */
570 #define WMREG_TBDAH 0x3804
572 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */
573 #define WMREG_TDLEN 0x3808
575 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */
576 #define WMREG_TDH 0x3810
578 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */
579 #define WMREG_TDT 0x3818
581 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */
582 #define WMREG_TIDV 0x3820
584 #define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */
585 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */
586 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */
587 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */
589 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */
591 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */
593 #define WMREG_VFTA 0x0600
595 #define WM_MC_TABSIZE 128
596 #define WM_ICH8_MC_TABSIZE 32
597 #define WM_VLAN_TABSIZE 128
599 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */
600 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */
601 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */
602 #define PBA_8K 0x0008
603 #define PBA_10K 0x000a
604 #define PBA_12K 0x000c
605 #define PBA_16K 0x0010 /* 16K, default Tx allocation */
606 #define PBA_20K 0x0014
607 #define PBA_22K 0x0016
608 #define PBA_24K 0x0018
609 #define PBA_30K 0x001e
610 #define PBA_32K 0x0020
611 #define PBA_40K 0x0028
612 #define PBA_48K 0x0030 /* 48K, default Rx allocation */
614 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */
616 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */
617 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */
618 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */
620 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */
621 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */
623 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */
624 #define KABGTXD_BGSQLBIAS 0x00050000
626 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum
627 Threshold (Cordova) */
629 #define WMREG_TARC0 0x3840 /* Tx arbitration count */
631 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */
632 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */
634 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */
635 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */
636 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */
637 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */
638 #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */
640 #define WMREG_RXERRC 0x400C /* receive error Count - R/clr */
641 #define WMREG_COLC 0x4028 /* collision Count - R/clr */
642 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */
643 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */
644 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */
645 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */
646 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */
648 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */
649 #define KUMCTRLSTA_MASK 0x0000FFFF
650 #define KUMCTRLSTA_OFFSET 0x001F0000
651 #define KUMCTRLSTA_OFFSET_SHIFT 16
652 #define KUMCTRLSTA_REN 0x00200000
654 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
655 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001
656 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
657 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003
658 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
659 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
660 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
661 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
662 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
665 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
666 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
668 /* In-Band Control */
669 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500
670 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
672 /* Half-Duplex Control */
673 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
674 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
676 #define WMREG_MDPHYA 0x003C /* PHY address - RW */
678 #define WMREG_MANC 0x5820 /* Management Control */
679 #define MANC_BLK_PHY_RST_ON_IDE 0x00040000
681 #define WMREG_MANC2H 0x5860 /* Manaegment Control To Host - RW */
683 #define WMREG_SWSM 0x5b50 /* SW Semaphore */
684 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
685 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
686 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */
687 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
689 #define WMREG_FWSM 0x5b54 /* FW Semaphore */
690 #define FWSM_MODE_MASK 0xe
691 #define FWSM_MODE_SHIFT 0x1
692 #define MNG_ICH_IAMT_MODE 0x2
693 #define MNG_IAMT_MODE 0x3
694 #define FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
696 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */
697 #define SWFW_EEP_SM 0x0001 /* eeprom access */
698 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */
699 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */
700 #define SWFW_MAC_CSR_SM 0x0008
701 #define SWFW_SOFT_SHIFT 0 /* software semaphores */
702 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */
704 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */
705 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001
706 #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002
707 #define EXTCNFCTR_D_UD_ENABLE 0x00000004
708 #define EXTCNFCTR_D_UD_LATENCY 0x00000008
709 #define EXTCNFCTR_D_UD_OWNER 0x00000010
710 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020
711 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040
712 #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000
713 #define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP
715 /* ich8 flash control */
716 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
717 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
718 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
719 #define ICH_FLASH_SEG_SIZE_256 256
720 #define ICH_FLASH_SEG_SIZE_4K 4096
721 #define ICH_FLASH_SEG_SIZE_64K 65536
723 #define ICH_CYCLE_READ 0x0
724 #define ICH_CYCLE_RESERVED 0x1
725 #define ICH_CYCLE_WRITE 0x2
726 #define ICH_CYCLE_ERASE 0x3
728 #define ICH_FLASH_GFPREG 0x0000
729 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */
730 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */
731 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */
732 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */
733 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */
734 #define HSFSTS_ERSZ_SHIFT 3
735 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */
736 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */
737 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */
738 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */
739 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */
740 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */
741 #define HSFCTL_CYCLE_SHIFT 1
742 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */
743 #define HSFCTL_BCOUNT_SHIFT 8
744 #define ICH_FLASH_FADDR 0x0008
745 #define ICH_FLASH_FDATA0 0x0010
746 #define ICH_FLASH_FRACC 0x0050
747 #define ICH_FLASH_FREG0 0x0054
748 #define ICH_FLASH_FREG1 0x0058
749 #define ICH_FLASH_FREG2 0x005C
750 #define ICH_FLASH_FREG3 0x0060
751 #define ICH_FLASH_FPR0 0x0074
752 #define ICH_FLASH_FPR1 0x0078
753 #define ICH_FLASH_SSFSTS 0x0090
754 #define ICH_FLASH_SSFCTL 0x0092
755 #define ICH_FLASH_PREOP 0x0094
756 #define ICH_FLASH_OPTYPE 0x0096
757 #define ICH_FLASH_OPMENU 0x0098
759 #define ICH_FLASH_REG_MAPSIZE 0x00A0
760 #define ICH_FLASH_SECTOR_SIZE 4096
761 #define ICH_GFPREG_BASE_MASK 0x1FFF
762 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
764 #define ICH_NVM_SIG_WORD 0x13
765 #define ICH_NVM_SIG_MASK 0xc000
