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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / isp_pci.c
blobbc3e3fb6a989995f5a2ffa7edb9f345b28b2bf58
1 /* $NetBSD: isp_pci.c,v 1.109 2009/06/25 23:44:02 mjacob Exp $ */
2 /*
3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration
4 * All rights reserved.
5 *
6 * Additional Copyright (C) 2000-2007 by Matthew Jacob
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 /*
32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
33 */
34
35 /*
36 * 24XX 4Gb material support provided by MetrumRG Associates.
37 * Many thanks are due to them.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.109 2009/06/25 23:44:02 mjacob Exp $");
42
43 #include <dev/ic/isp_netbsd.h>
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcidevs.h>
47 #include <uvm/uvm_extern.h>
48 #include <sys/reboot.h>
49
50 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int);
51 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t);
52 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
53 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int);
54 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t);
55 #endif
56 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
57 !defined(ISP_DISABLE_2200_SUPPORT) && \
58 !defined(ISP_DISABLE_1020_SUPPORT) && \
59 !defined(ISP_DISABLE_1080_SUPPORT) && \
60 !defined(ISP_DISABLE_12160_SUPPORT)
61 static int
62 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
63 #endif
64 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT))
65 static int
66 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
67 #endif
68 #if !defined(ISP_DISABLE_2400_SUPPORT)
69 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int);
70 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t);
71 static int
72 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *);
73 #endif
74 static int isp_pci_mbxdma(struct ispsoftc *);
75 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *);
76 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t);
77 static void isp_pci_reset0(struct ispsoftc *);
78 static void isp_pci_reset1(struct ispsoftc *);
79 static void isp_pci_dumpregs(struct ispsoftc *, const char *);
80 static int isp_pci_intr(void *);
81
82 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW)
83 #define ISP_1040_RISC_CODE NULL
84 #else
85 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code
86 #include <dev/microcode/isp/asm_1040.h>
87 #endif
88
89 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW)
90 #define ISP_1080_RISC_CODE NULL
91 #else
92 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code
93 #include <dev/microcode/isp/asm_1080.h>
94 #endif
95
96 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW)
97 #define ISP_12160_RISC_CODE NULL
98 #else
99 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code
100 #include <dev/microcode/isp/asm_12160.h>
101 #endif
102
103 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW)
104 #define ISP_2100_RISC_CODE NULL
105 #else
106 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code
107 #include <dev/microcode/isp/asm_2100.h>
108 #endif
109
110 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW)
111 #define ISP_2200_RISC_CODE NULL
112 #else
113 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code
114 #include <dev/microcode/isp/asm_2200.h>
115 #endif
116
117 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW)
118 #define ISP_2300_RISC_CODE NULL
119 #else
120 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code
121 #include <dev/microcode/isp/asm_2300.h>
122 #endif
123 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW)
124 #define ISP_2322_RISC_CODE NULL
125 #else
126 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code
127 #include <dev/microcode/isp/asm_2322.h>
128 #endif
129
130 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW)
131 #define ISP_2400_RISC_CODE NULL
132 #define ISP_2500_RISC_CODE NULL
133 #else
134 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code
135 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code
136 #include <dev/microcode/isp/asm_2400.h>
137 #include <dev/microcode/isp/asm_2500.h>
138 #endif
139
140 #ifndef ISP_DISABLE_1020_SUPPORT
141 static struct ispmdvec mdvec = {
142 isp_pci_rd_isr,
143 isp_pci_rd_reg,
144 isp_pci_wr_reg,
145 isp_pci_mbxdma,
146 isp_pci_dmasetup,
147 isp_pci_dmateardown,
148 isp_pci_reset0,
149 isp_pci_reset1,
150 isp_pci_dumpregs,
151 ISP_1040_RISC_CODE,
152 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
153 0
154 };
155 #endif
156
157 #ifndef ISP_DISABLE_1080_SUPPORT
158 static struct ispmdvec mdvec_1080 = {
159 isp_pci_rd_isr,
160 isp_pci_rd_reg_1080,
161 isp_pci_wr_reg_1080,
162 isp_pci_mbxdma,
163 isp_pci_dmasetup,
164 isp_pci_dmateardown,
165 isp_pci_reset0,
166 isp_pci_reset1,
167 isp_pci_dumpregs,
168 ISP_1080_RISC_CODE,
169 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
170 0
171 };
172 #endif
173
174 #ifndef ISP_DISABLE_12160_SUPPORT
175 static struct ispmdvec mdvec_12160 = {
176 isp_pci_rd_isr,
177 isp_pci_rd_reg_1080,
178 isp_pci_wr_reg_1080,
179 isp_pci_mbxdma,
180 isp_pci_dmasetup,
181 isp_pci_dmateardown,
182 isp_pci_reset0,
183 isp_pci_reset1,
184 isp_pci_dumpregs,
185 ISP_12160_RISC_CODE,
186 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
187 0
188 };
189 #endif
190
191 #ifndef ISP_DISABLE_2100_SUPPORT
192 static struct ispmdvec mdvec_2100 = {
193 isp_pci_rd_isr,
194 isp_pci_rd_reg,
195 isp_pci_wr_reg,
196 isp_pci_mbxdma,
197 isp_pci_dmasetup,
198 isp_pci_dmateardown,
199 isp_pci_reset0,
200 isp_pci_reset1,
201 isp_pci_dumpregs,
202 ISP_2100_RISC_CODE,
203 0,
204 0
205 };
206 #endif
207
208 #ifndef ISP_DISABLE_2200_SUPPORT
209 static struct ispmdvec mdvec_2200 = {
210 isp_pci_rd_isr,
211 isp_pci_rd_reg,
212 isp_pci_wr_reg,
213 isp_pci_mbxdma,
214 isp_pci_dmasetup,
215 isp_pci_dmateardown,
216 isp_pci_reset0,
217 isp_pci_reset1,
218 isp_pci_dumpregs,
219 ISP_2200_RISC_CODE,
220 0,
221 0
222 };
223 #endif
224
225 #ifndef ISP_DISABLE_2300_SUPPORT
226 static struct ispmdvec mdvec_2300 = {
227 isp_pci_rd_isr_2300,
228 isp_pci_rd_reg,
229 isp_pci_wr_reg,
230 isp_pci_mbxdma,
231 isp_pci_dmasetup,
232 isp_pci_dmateardown,
233 isp_pci_reset0,
234 isp_pci_reset1,
235 isp_pci_dumpregs,
236 ISP_2300_RISC_CODE,
237 0,
238 0
239 };
240 #endif
241
242 #ifndef ISP_DISABLE_2322_SUPPORT
243 static struct ispmdvec mdvec_2322 = {
244 isp_pci_rd_isr_2300,
245 isp_pci_rd_reg,
246 isp_pci_wr_reg,
247 isp_pci_mbxdma,
248 isp_pci_dmasetup,
249 isp_pci_dmateardown,
250 isp_pci_reset0,
251 isp_pci_reset1,
252 isp_pci_dumpregs,
253 ISP_2322_RISC_CODE,
254 0,
255 0
256 };
257 #endif
258
259 #ifndef ISP_DISABLE_2400_SUPPORT
260 static struct ispmdvec mdvec_2400 = {
261 isp_pci_rd_isr_2400,
262 isp_pci_rd_reg_2400,
263 isp_pci_wr_reg_2400,
264 isp_pci_mbxdma,
265 isp_pci_dmasetup,
266 isp_pci_dmateardown,
267 isp_pci_reset0,
268 isp_pci_reset1,
269 NULL,
270 ISP_2400_RISC_CODE,
271 0,
272 0
273 };
274 static struct ispmdvec mdvec_2500 = {
275 isp_pci_rd_isr_2400,
276 isp_pci_rd_reg_2400,
277 isp_pci_wr_reg_2400,
278 isp_pci_mbxdma,
279 isp_pci_dmasetup,
280 isp_pci_dmateardown,
281 isp_pci_reset0,
282 isp_pci_reset1,
283 NULL,
284 ISP_2500_RISC_CODE,
285 0,
286 0
287 };
288 #endif
289
290 #ifndef PCI_VENDOR_QLOGIC
291 #define PCI_VENDOR_QLOGIC 0x1077
292 #endif
293
294 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
295 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
296 #endif
297
298 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
299 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
300 #endif
301
302 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
303 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
304 #endif
305
306 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
307 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
308 #endif
309
310 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
311 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
312 #endif
313
314 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
315 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
316 #endif
317
318 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
319 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
320 #endif
321
322 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
323 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
324 #endif
325
326 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
327 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
328 #endif
329
330 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
331 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
332 #endif
333
334 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
335 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
336 #endif
337
338 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
339 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
340 #endif
341
342 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
343 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
344 #endif
345
346 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
347 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
348 #endif
349
350 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
351 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
352 #endif
353
354 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
355 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
356 #endif
357
358
359 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
360
361 #define PCI_QLOGIC_ISP1080 \
362 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
363
364 #define PCI_QLOGIC_ISP10160 \
365 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
366
367 #define PCI_QLOGIC_ISP12160 \
368 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
369
370 #define PCI_QLOGIC_ISP1240 \
371 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
372
373 #define PCI_QLOGIC_ISP1280 \
374 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
375
376 #define PCI_QLOGIC_ISP2100 \
377 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
378
379 #define PCI_QLOGIC_ISP2200 \
380 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
381
382 #define PCI_QLOGIC_ISP2300 \
383 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
384
385 #define PCI_QLOGIC_ISP2312 \
386 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
387
388 #define PCI_QLOGIC_ISP2322 \
389 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
390
391 #define PCI_QLOGIC_ISP2422 \
392 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
393
394 #define PCI_QLOGIC_ISP2432 \
395 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
396
397 #define PCI_QLOGIC_ISP2532 \
398 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
399
400 #define PCI_QLOGIC_ISP6312 \
401 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
402
403 #define PCI_QLOGIC_ISP6322 \
404 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
405
406 #define IO_MAP_REG 0x10
407 #define MEM_MAP_REG 0x14
408 #define PCIR_ROMADDR 0x30
409
410 #define PCI_DFLT_LTNCY 0x40
411 #define PCI_DFLT_LNSZ 0x10
412
413 static int isp_pci_probe(device_t, cfdata_t, void *);
414 static void isp_pci_attach(device_t, device_t, void *);
415
416 struct isp_pcisoftc {
417 struct ispsoftc pci_isp;
418 pci_chipset_tag_t pci_pc;
419 pcitag_t pci_tag;
420 bus_space_tag_t pci_st;
421 bus_space_handle_t pci_sh;
422 bus_dmamap_t *pci_xfer_dmap;
423 void * pci_ih;
424 int16_t pci_poff[_NREG_BLKS];
425 };
426
427 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc),
428 isp_pci_probe, isp_pci_attach, NULL, NULL);
429
430 static int
431 isp_pci_probe(device_t parent, cfdata_t match, void *aux)
432 {
433 struct pci_attach_args *pa = aux;
434 switch (pa->pa_id) {
435 #ifndef ISP_DISABLE_1020_SUPPORT
436 case PCI_QLOGIC_ISP:
437 return (1);
438 #endif
439 #ifndef ISP_DISABLE_1080_SUPPORT
440 case PCI_QLOGIC_ISP1080:
441 case PCI_QLOGIC_ISP1240:
442 case PCI_QLOGIC_ISP1280:
443 return (1);
444 #endif
445 #ifndef ISP_DISABLE_12160_SUPPORT
446 case PCI_QLOGIC_ISP10160:
447 case PCI_QLOGIC_ISP12160:
448 return (1);
449 #endif
450 #ifndef ISP_DISABLE_2100_SUPPORT
451 case PCI_QLOGIC_ISP2100:
452 return (1);
453 #endif
454 #ifndef ISP_DISABLE_2200_SUPPORT
455 case PCI_QLOGIC_ISP2200:
456 return (1);
457 #endif
458 #ifndef ISP_DISABLE_2300_SUPPORT
459 case PCI_QLOGIC_ISP2300:
460 case PCI_QLOGIC_ISP2312:
461 case PCI_QLOGIC_ISP6312:
462 #endif
463 #ifndef ISP_DISABLE_2322_SUPPORT
464 case PCI_QLOGIC_ISP2322:
465 case PCI_QLOGIC_ISP6322:
466 return (1);
467 #endif
468 #ifndef ISP_DISABLE_2400_SUPPORT
469 case PCI_QLOGIC_ISP2422:
470 case PCI_QLOGIC_ISP2432:
471 case PCI_QLOGIC_ISP2532:
472 return (1);
473 #endif
474 default:
475 return (0);
476 }
477 }
478
479 static void
480 isp_pci_attach(device_t parent, device_t self, void *aux)
481 {
482 static const char nomem[] = "\n%s: no mem for sdparam table\n";
483 uint32_t data, rev, linesz = PCI_DFLT_LNSZ;
484 struct pci_attach_args *pa = aux;
485 struct isp_pcisoftc *pcs = device_private(self);
486 struct ispsoftc *isp = &pcs->pci_isp;
487 bus_space_tag_t st, iot, memt;
488 bus_space_handle_t sh, ioh, memh;
489 pci_intr_handle_t ih;
490 pcireg_t mem_type;
491 const char *dstring;
492 const char *intrstr;
493 int ioh_valid, memh_valid;
494 size_t mamt;
495
496 isp->isp_osinfo.dev = self;
497
498 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
499 PCI_MAPREG_TYPE_IO, 0,
500 &iot, &ioh, NULL, NULL) == 0);
501
502 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG);
503 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) {
504 memh_valid = 0;
505 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT &&
506 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) {
507 memh_valid = 0;
508 } else {
509 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0,
510 &memt, &memh, NULL, NULL) == 0);
511 }
512 if (memh_valid) {
513 st = memt;
514 sh = memh;
515 } else if (ioh_valid) {
516 st = iot;
517 sh = ioh;
518 } else {
519 printf(": unable to map device registers\n");
520 return;
521 }
522 dstring = "\n";
523
524 isp->isp_nchan = 1;
525 mamt = 0;
526
527 pcs->pci_st = st;
528 pcs->pci_sh = sh;
529 pcs->pci_pc = pa->pa_pc;
530 pcs->pci_tag = pa->pa_tag;
531 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
532 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
533 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
534 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
535 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
536 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
537
538
539 #ifndef ISP_DISABLE_1020_SUPPORT
540 if (pa->pa_id == PCI_QLOGIC_ISP) {
541 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n";
542 isp->isp_mdvec = &mdvec;
543 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
544 mamt = sizeof (sdparam);
545 }
546 #endif
547 #ifndef ISP_DISABLE_1080_SUPPORT
548 if (pa->pa_id == PCI_QLOGIC_ISP1080) {
549 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n";
550 isp->isp_mdvec = &mdvec_1080;
551 isp->isp_type = ISP_HA_SCSI_1080;
552 mamt = sizeof (sdparam);
553 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
554 ISP1080_DMA_REGS_OFF;
555 }
556 if (pa->pa_id == PCI_QLOGIC_ISP1240) {
557 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n";
558 isp->isp_mdvec = &mdvec_1080;
559 isp->isp_type = ISP_HA_SCSI_1240;
560 isp->isp_nchan++;
561 mamt = sizeof (sdparam) * 2;
562 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
563 ISP1080_DMA_REGS_OFF;
564 }
565 if (pa->pa_id == PCI_QLOGIC_ISP1280) {
566 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n";
567 isp->isp_mdvec = &mdvec_1080;
568 isp->isp_type = ISP_HA_SCSI_1280;
569 isp->isp_nchan++;
570 mamt = sizeof (sdparam) * 2;
571 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
572 ISP1080_DMA_REGS_OFF;
573 }
574 #endif
575 #ifndef ISP_DISABLE_12160_SUPPORT
576 if (pa->pa_id == PCI_QLOGIC_ISP10160) {
577 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n";
578 isp->isp_mdvec = &mdvec_12160;
579 isp->isp_type = ISP_HA_SCSI_10160;
580 mamt = sizeof (sdparam);
581 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
582 ISP1080_DMA_REGS_OFF;
583 }
584 if (pa->pa_id == PCI_QLOGIC_ISP12160) {
585 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n";
586 isp->isp_mdvec = &mdvec_12160;
587 isp->isp_type = ISP_HA_SCSI_12160;
588 isp->isp_nchan++;
589 mamt = sizeof (sdparam) * 2;
590 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] =
591 ISP1080_DMA_REGS_OFF;
592 }
593 #endif
594 #ifndef ISP_DISABLE_2100_SUPPORT
595 if (pa->pa_id == PCI_QLOGIC_ISP2100) {
596 dstring = ": QLogic FC-AL HBA\n";
597 isp->isp_mdvec = &mdvec_2100;
598 isp->isp_type = ISP_HA_FC_2100;
599 mamt = sizeof (fcparam);
600 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
601 PCI_MBOX_REGS2100_OFF;
602 if (rev < 3) {
603 /*
604 * XXX: Need to get the actual revision
605 * XXX: number of the 2100 FB. At any rate,
606 * XXX: lower cache line size for early revision
607 * XXX; boards.
608 */
609 linesz = 1;
610 }
611 }
612 #endif
613 #ifndef ISP_DISABLE_2200_SUPPORT
614 if (pa->pa_id == PCI_QLOGIC_ISP2200) {
615 dstring = ": QLogic FC-AL and Fabric HBA\n";
616 isp->isp_mdvec = &mdvec_2200;
617 isp->isp_type = ISP_HA_FC_2200;
618 mamt = sizeof (fcparam);
619 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
620 PCI_MBOX_REGS2100_OFF;
621 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
622 }
623 #endif
624 #ifndef ISP_DISABLE_2300_SUPPORT
625 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
626 pa->pa_id == PCI_QLOGIC_ISP2312 ||
627 pa->pa_id == PCI_QLOGIC_ISP6312) {
628 isp->isp_mdvec = &mdvec_2300;
629 if (pa->pa_id == PCI_QLOGIC_ISP2300 ||
630 pa->pa_id == PCI_QLOGIC_ISP6312) {
631 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n";
632 isp->isp_type = ISP_HA_FC_2300;
633 } else {
634 dstring =
635 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n";
636 isp->isp_port = pa->pa_function;
637 }
638 isp->isp_type = ISP_HA_FC_2312;
639 mamt = sizeof (fcparam);
640 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
641 PCI_MBOX_REGS2300_OFF;
642 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
643 }
644 #endif
645 #ifndef ISP_DISABLE_2322_SUPPORT
646 if (pa->pa_id == PCI_QLOGIC_ISP2322 ||
647 pa->pa_id == PCI_QLOGIC_ISP6322) {
648 isp->isp_mdvec = &mdvec_2322;
649 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n";
650 isp->isp_type = ISP_HA_FC_2322;
651 isp->isp_port = pa->pa_function;
652 mamt = sizeof (fcparam);
653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
654 PCI_MBOX_REGS2300_OFF;
655 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
656 }
657 #endif
658 #ifndef ISP_DISABLE_2400_SUPPORT
659 if (pa->pa_id == PCI_QLOGIC_ISP2422 ||
660 pa->pa_id == PCI_QLOGIC_ISP2432) {
661 isp->isp_mdvec = &mdvec_2400;
662 if (pa->pa_id == PCI_QLOGIC_ISP2422) {
663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n";
664 } else {
665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n";
666 }
667 isp->isp_type = ISP_HA_FC_2400;
668 mamt = sizeof (fcparam);
669 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
670 PCI_MBOX_REGS2400_OFF;
671 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
672 }
673 if (pa->pa_id == PCI_QLOGIC_ISP2532) {
674 isp->isp_mdvec = &mdvec_2500;
675 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n";
676 isp->isp_type = ISP_HA_FC_2500;
677 mamt = sizeof (fcparam);
678 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] =
679 PCI_MBOX_REGS2400_OFF;
680 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
681 }
682 #endif
683 if (mamt == 0) {
684 return;
685 }
686
687 isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT);
688 if (isp->isp_param == NULL) {
689 printf(nomem, device_xname(self));
690 return;
691 }
692 memset(isp->isp_param, 0, mamt);
693 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan;
694 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT);
695 if (isp->isp_osinfo.chan == NULL) {
696 free(isp->isp_param, M_DEVBUF);
697 printf(nomem, device_xname(self));
698 return;
699 }
700 memset(isp->isp_osinfo.chan, 0, mamt);
701 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan;
702
703 /*
704 * Set up logging levels.
705 */
706 #ifdef ISP_LOGDEFAULT
707 isp->isp_dblev = ISP_LOGDEFAULT;
708 #else
709 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
710 if (bootverbose)
711 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
712 #ifdef SCSIDEBUG
713 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2;
714 #endif
715 #endif
716 if (isp->isp_dblev & ISP_LOGCONFIG) {
717 printf("\n");
718 } else {
719 printf(dstring);
720 }
721
722 isp->isp_dmatag = pa->pa_dmat;
723 isp->isp_revision = rev;
724
725 /*
726 * Make sure that command register set sanely.
727 */
728 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
729 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
730
731 /*
732 * Not so sure about these- but I think it's important that they get
733 * enabled......
734 */
735 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
736 if (IS_2300(isp)) { /* per QLogic errata */
737 data &= ~PCI_COMMAND_INVALIDATE_ENABLE;
738 }
739 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
740
741 /*
742 * Make sure that the latency timer, cache line size,
743 * and ROM is disabled.
744 */
745 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
746 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
747 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
748 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT);
749 data |= (linesz << PCI_CACHELINE_SHIFT);
750 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
751
752 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR);
753 data &= ~1;
754 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data);
755
756 if (pci_intr_map(pa, &ih)) {
757 aprint_error_dev(self, "couldn't map interrupt\n");
758 free(isp->isp_param, M_DEVBUF);
759 free(isp->isp_osinfo.chan, M_DEVBUF);
760 return;
761 }
762 intrstr = pci_intr_string(pa->pa_pc, ih);
763 if (intrstr == NULL)
764 intrstr = "<I dunno>";
765 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
766 isp_pci_intr, isp);
767 if (pcs->pci_ih == NULL) {
768 aprint_error_dev(self, "couldn't establish interrupt at %s\n",
769 intrstr);
770 free(isp->isp_param, M_DEVBUF);
771 free(isp->isp_osinfo.chan, M_DEVBUF);
772 return;
773 }
774
775 printf("%s: interrupting at %s\n", device_xname(self), intrstr);
776
777 isp->isp_confopts = device_cfdata(self)->cf_flags;
778 ISP_LOCK(isp);
779 isp_reset(isp, 1);
780 if (isp->isp_state != ISP_RESETSTATE) {
781 ISP_UNLOCK(isp);
782 free(isp->isp_param, M_DEVBUF);
783 free(isp->isp_osinfo.chan, M_DEVBUF);
784 return;
785 }
786 isp_init(isp);
787 if (isp->isp_state != ISP_INITSTATE) {
788 isp_uninit(isp);
789 ISP_UNLOCK(isp);
790 free(isp->isp_param, M_DEVBUF);
791 free(isp->isp_osinfo.chan, M_DEVBUF);
792 return;
793 }
794 /*
795 * Do platform attach.
796 */
797 ISP_UNLOCK(isp);
798 isp_attach(isp);
799 }
800
801 #define IspVirt2Off(a, x) \
802 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
803 _BLK_REG_SHFT] + ((x) & 0xff))
804
805 #define BXR2(pcs, off) \
806 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off)
807 #define BXW2(pcs, off, v) \
808 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v)
809 #define BXR4(pcs, off) \
810 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off)
811 #define BXW4(pcs, off, v) \
812 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v)
813
814
815 static int
816 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp)
817 {
818 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
819 uint16_t val0, val1;
820 int i = 0;
821
822 do {
823 val0 = BXR2(pcs, IspVirt2Off(isp, off));
824 val1 = BXR2(pcs, IspVirt2Off(isp, off));
825 } while (val0 != val1 && ++i < 1000);
826 if (val0 != val1) {
827 return (1);
828 }
829 *rp = val0;
830 return (0);
831 }
832
833 #if !defined(ISP_DISABLE_2100_SUPPORT) && \
834 !defined(ISP_DISABLE_2200_SUPPORT) && \
835 !defined(ISP_DISABLE_1020_SUPPORT) && \
836 !defined(ISP_DISABLE_1080_SUPPORT) && \
837 !defined(ISP_DISABLE_12160_SUPPORT)
838 static int
839 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp,
840 uint16_t *semap, uint16_t *mbp)
841 {
842 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
843 uint16_t isr, sema;
844
845 if (IS_2100(isp)) {
846 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
847 return (0);
848 }
849 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
850 return (0);
851 }
852 } else {
853 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR));
854 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA));
855 }
856 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
857 isr &= INT_PENDING_MASK(isp);
858 sema &= BIU_SEMA_LOCK;
859 if (isr == 0 && sema == 0) {
860 return (0);
861 }
862 *isrp = isr;
863 if ((*semap = sema) != 0) {
864 if (IS_2100(isp)) {
865 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) {
866 return (0);
867 }
868 } else {
869 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0));
870 }
871 }
872 return (1);
873 }
874 #endif
875
876 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT))
877 static int
878 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp,
879 uint16_t *semap, uint16_t *mbox0p)
880 {
881 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
882 uint32_t r2hisr;
883
884 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) {
885 *isrp = 0;
886 return (0);
887 }
888 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh,
889 IspVirt2Off(pcs, BIU_R2HSTSLO));
890 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
891 if ((r2hisr & BIU_R2HST_INTR) == 0) {
892 *isrp = 0;
893 return (0);
894 }
895 switch (r2hisr & BIU_R2HST_ISTAT_MASK) {
896 case ISPR2HST_ROM_MBX_OK:
897 case ISPR2HST_ROM_MBX_FAIL:
898 case ISPR2HST_MBX_OK:
899 case ISPR2HST_MBX_FAIL:
900 case ISPR2HST_ASYNC_EVENT:
901 *isrp = r2hisr & 0xffff;
902 *mbox0p = (r2hisr >> 16);
903 *semap = 1;
904 return (1);
905 case ISPR2HST_RIO_16:
906 *isrp = r2hisr & 0xffff;
907 *mbox0p = ASYNC_RIO1;
908 *semap = 1;
909 return (1);
910 case ISPR2HST_FPOST:
911 *isrp = r2hisr & 0xffff;
912 *mbox0p = ASYNC_CMD_CMPLT;
913 *semap = 1;
914 return (1);
915 case ISPR2HST_FPOST_CTIO:
916 *isrp = r2hisr & 0xffff;
917 *mbox0p = ASYNC_CTIO_DONE;
918 *semap = 1;
919 return (1);
920 case ISPR2HST_RSPQ_UPDATE:
921 *isrp = r2hisr & 0xffff;
922 *mbox0p = 0;
923 *semap = 0;
924 return (1);
925 default:
926 return (0);
927 }
928 }
929 #endif
930
931 #ifndef ISP_DISABLE_2400_SUPPORT
932 static int
933 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp,
934 uint16_t *semap, uint16_t *mbox0p)
935 {
936 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
937 uint32_t r2hisr;
938
939 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO));
940 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
941 if ((r2hisr & BIU2400_R2HST_INTR) == 0) {
942 *isrp = 0;
943 return (0);
944 }
945 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) {
946 case ISP2400R2HST_ROM_MBX_OK:
947 case ISP2400R2HST_ROM_MBX_FAIL:
948 case ISP2400R2HST_MBX_OK:
949 case ISP2400R2HST_MBX_FAIL:
950 case ISP2400R2HST_ASYNC_EVENT:
951 *isrp = r2hisr & 0xffff;
952 *mbox0p = (r2hisr >> 16);
953 *semap = 1;
954 return (1);
955 case ISP2400R2HST_RSPQ_UPDATE:
956 case ISP2400R2HST_ATIO_RSPQ_UPDATE:
957 case ISP2400R2HST_ATIO_RQST_UPDATE:
958 *isrp = r2hisr & 0xffff;
959 *mbox0p = 0;
960 *semap = 0;
961 return (1);
962 default:
963 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
964 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
965 return (0);
966 }
967 }
968
969 static uint32_t
970 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
971 {
972 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
973 uint32_t rv;
974 int block = regoff & _BLK_REG_MASK;
975
976 switch (block) {
977 case BIU_BLOCK:
978 break;
979 case MBOX_BLOCK:
980 return (BXR2(pcs, IspVirt2Off(pcs, regoff)));
981 case SXP_BLOCK:
982 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff);
983 return (0xffffffff);
984 case RISC_BLOCK:
985 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff);
986 return (0xffffffff);
987 case DMA_BLOCK:
988 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff);
989 return (0xffffffff);
990 default:
991 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff);
992 return (0xffffffff);
993 }
994
995
996 switch (regoff) {
997 case BIU2400_FLASH_ADDR:
998 case BIU2400_FLASH_DATA:
999 case BIU2400_ICR:
1000 case BIU2400_ISR:
1001 case BIU2400_CSR:
1002 case BIU2400_REQINP:
1003 case BIU2400_REQOUTP:
1004 case BIU2400_RSPINP:
1005 case BIU2400_RSPOUTP:
1006 case BIU2400_PRI_REQINP:
1007 case BIU2400_PRI_REQOUTP:
1008 case BIU2400_ATIO_RSPINP:
1009 case BIU2400_ATIO_RSPOUTP:
1010 case BIU2400_HCCR:
1011 case BIU2400_GPIOD:
1012 case BIU2400_GPIOE:
1013 case BIU2400_HSEMA:
1014 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1015 break;
1016 case BIU2400_R2HSTSLO:
1017 rv = BXR4(pcs, IspVirt2Off(pcs, regoff));
1018 break;
1019 case BIU2400_R2HSTSHI:
1020 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16;
1021 break;
1022 default:
1023 isp_prt(isp, ISP_LOGERR,
1024 "isp_pci_rd_reg_2400: unknown offset %x", regoff);
1025 rv = 0xffffffff;
1026 break;
1027 }
1028 return (rv);
1029 }
1030
1031 static void
1032 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1033 {
1034 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1035 int block = regoff & _BLK_REG_MASK;
1036 volatile int junk;
1037
1038 switch (block) {
1039 case BIU_BLOCK:
1040 break;
1041 case MBOX_BLOCK:
1042 BXW2(pcs, IspVirt2Off(pcs, regoff), val);
1043 junk = BXR2(pcs, IspVirt2Off(pcs, regoff));
1044 return;
1045 case SXP_BLOCK:
1046 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff);
1047 return;
1048 case RISC_BLOCK:
1049 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff);
1050 return;
1051 case DMA_BLOCK:
1052 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff);
1053 return;
1054 default:
1055 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x",
1056 regoff);
1057 break;
1058 }
1059
1060 switch (regoff) {
1061 case BIU2400_FLASH_ADDR:
1062 case BIU2400_FLASH_DATA:
1063 case BIU2400_ICR:
1064 case BIU2400_ISR:
1065 case BIU2400_CSR:
1066 case BIU2400_REQINP:
1067 case BIU2400_REQOUTP:
1068 case BIU2400_RSPINP:
1069 case BIU2400_RSPOUTP:
1070 case BIU2400_PRI_REQINP:
1071 case BIU2400_PRI_REQOUTP:
1072 case BIU2400_ATIO_RSPINP:
1073 case BIU2400_ATIO_RSPOUTP:
1074 case BIU2400_HCCR:
1075 case BIU2400_GPIOD:
1076 case BIU2400_GPIOE:
1077 case BIU2400_HSEMA:
1078 BXW4(pcs, IspVirt2Off(pcs, regoff), val);
1079 junk = BXR4(pcs, IspVirt2Off(pcs, regoff));
1080 break;
1081 default:
1082 isp_prt(isp, ISP_LOGERR,
1083 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff);
1084 break;
1085 }
1086 }
1087 #endif
1088
1089 static uint32_t
1090 isp_pci_rd_reg(struct ispsoftc *isp, int regoff)
1091 {
1092 uint32_t rv;
1093 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1094 int oldconf = 0;
1095
1096 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1097 /*
1098 * We will assume that someone has paused the RISC processor.
1099 */
1100 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1101 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1102 oldconf | BIU_PCI_CONF1_SXP);
1103 }
1104 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1105 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1106 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1107 }
1108 return (rv);
1109 }
1110
1111 static void
1112 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val)
1113 {
1114 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1115 int oldconf = 0;
1116
1117 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1118 /*
1119 * We will assume that someone has paused the RISC processor.
1120 */
1121 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1122 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1123 oldconf | BIU_PCI_CONF1_SXP);
1124 }
1125 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1126 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1127 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf);
1128 }
1129 }
1130
1131 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT))
1132 static uint32_t
1133 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff)
1134 {
1135 uint16_t rv, oc = 0;
1136 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1137
1138 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1139 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1140 uint16_t tc;
1141 /*
1142 * We will assume that someone has paused the RISC processor.
1143 */
1144 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1145 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1146 if (regoff & SXP_BANK1_SELECT)
1147 tc |= BIU_PCI1080_CONF1_SXP1;
1148 else
1149 tc |= BIU_PCI1080_CONF1_SXP0;
1150 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1151 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1152 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1153 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1154 oc | BIU_PCI1080_CONF1_DMA);
1155 }
1156 rv = BXR2(pcs, IspVirt2Off(isp, regoff));
1157 if (oc) {
1158 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1159 }
1160 return (rv);
1161 }
1162
1163 static void
1164 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val)
1165 {
1166 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
1167 int oc = 0;
1168
1169 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK ||
1170 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) {
1171 uint16_t tc;
1172 /*
1173 * We will assume that someone has paused the RISC processor.
1174 */
1175 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1176 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1177 if (regoff & SXP_BANK1_SELECT)
1178 tc |= BIU_PCI1080_CONF1_SXP1;
1179 else
1180 tc |= BIU_PCI1080_CONF1_SXP0;
1181 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc);
1182 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1183 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1));
1184 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1),
1185 oc | BIU_PCI1080_CONF1_DMA);
1186 }
1187 BXW2(pcs, IspVirt2Off(isp, regoff), val);
1188 if (oc) {
1189 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc);
1190 }
1191 }
1192 #endif
1193
1194 static int
1195 isp_pci_mbxdma(struct ispsoftc *isp)
1196 {
1197 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1198 bus_dma_tag_t dmat = isp->isp_dmatag;
1199 bus_dma_segment_t sg;
1200 bus_size_t len, dbound;
1201 fcparam *fcp;
1202 int rs, i;
1203
1204 if (isp->isp_rquest_dma) /* been here before? */
1205 return (0);
1206
1207 if (isp->isp_type <= ISP_HA_SCSI_1040B) {
1208 dbound = 1 << 24;
1209 } else {
1210 /*
1211 * For 32-bit PCI DMA, the range is 32 bits or zero :-)
1212 */
1213 dbound = 0;
1214 }
1215 len = isp->isp_maxcmds * sizeof (XS_T *);
1216 isp->isp_xflist = (XS_T **) malloc(len, M_DEVBUF, M_WAITOK);
1217 if (isp->isp_xflist == NULL) {
1218 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array");
1219 return (1);
1220 }
1221 memset(isp->isp_xflist, 0, len);
1222 len = isp->isp_maxcmds * sizeof (bus_dmamap_t);
1223 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK);
1224 if (pcs->pci_xfer_dmap == NULL) {
1225 free(isp->isp_xflist, M_DEVBUF);
1226 isp->isp_xflist = NULL;
1227 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array");
1228 return (1);
1229 }
1230 for (i = 0; i < isp->isp_maxcmds; i++) {
1231 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1,
1232 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) {
1233 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps");
1234 break;
1235 }
1236 }
1237 if (i < isp->isp_maxcmds) {
1238 while (--i >= 0) {
1239 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1240 }
1241 free(isp->isp_xflist, M_DEVBUF);
1242 free(pcs->pci_xfer_dmap, M_DEVBUF);
1243 isp->isp_xflist = NULL;
1244 pcs->pci_xfer_dmap = NULL;
1245 return (1);
1246 }
1247
1248 /*
1249 * Allocate and map the request queue.
1250 */
1251 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1252 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) {
1253 goto dmafail;
1254 }
1255 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len,
1256 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1257 goto dmafail;
1258 }
1259 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1260 &isp->isp_rqdmap)) {
1261 goto dmafail;
1262 }
1263 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL,
1264 BUS_DMA_NOWAIT)) {
1265 goto dmafail;
1266 }
1267 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr;
1268
1269 /*
1270 * Allocate and map the result queue.
1271 */
1272 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1273 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs,
1274 BUS_DMA_NOWAIT)) {
1275 goto dmafail;
1276 }
1277 if (bus_dmamem_map(dmat, &sg, rs, len,
1278 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1279 goto dmafail;
1280 }
1281 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1282 &isp->isp_rsdmap)) {
1283 goto dmafail;
1284 }
1285 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL,
1286 BUS_DMA_NOWAIT)) {
1287 goto dmafail;
1288 }
1289 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr;
1290
1291 if (IS_SCSI(isp)) {
1292 return (0);
1293 }
1294
1295 /*
1296 * Allocate and map an FC scratch area
1297 */
1298 fcp = isp->isp_param;
1299 len = ISP_FC_SCRLEN;
1300 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs,
1301 BUS_DMA_NOWAIT)) {
1302 goto dmafail;
1303 }
1304 if (bus_dmamem_map(dmat, &sg, rs, len,
1305 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
1306 goto dmafail;
1307 }
1308 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT,
1309 &isp->isp_scdmap)) {
1310 goto dmafail;
1311 }
1312 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL,
1313 BUS_DMA_NOWAIT)) {
1314 goto dmafail;
1315 }
1316 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr;
1317 return (0);
1318 dmafail:
1319 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure");
1320 for (i = 0; i < isp->isp_maxcmds; i++) {
1321 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]);
1322 }
1323 free(isp->isp_xflist, M_DEVBUF);
1324 free(pcs->pci_xfer_dmap, M_DEVBUF);
1325 isp->isp_xflist = NULL;
1326 pcs->pci_xfer_dmap = NULL;
1327 return (1);
1328 }
1329
1330 static int
1331 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg)
1332 {
1333 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1334 ispreq_t *rq = arg;
1335 bus_dmamap_t dmap;
1336 bus_dma_segment_t *dm_segs;
1337 uint32_t nsegs;
1338 isp_ddir_t ddir;
1339
1340 dmap = pcs->pci_xfer_dmap[isp_handle_index(rq->req_handle)];
1341 if (xs->datalen == 0) {
1342 ddir = ISP_NOXFR;
1343 nsegs = 0;
1344 dm_segs = NULL;
1345 } else {
1346 int error;
1347 uint32_t flag, flg2;
1348
1349 if (sizeof (bus_addr_t) > 4) {
1350 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1351 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1352 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1353 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1354 }
1355 }
1356
1357 if (xs->xs_control & XS_CTL_DATA_IN) {
1358 flg2 = BUS_DMASYNC_PREREAD;
1359 flag = BUS_DMA_READ;
1360 ddir = ISP_FROM_DEVICE;
1361 } else {
1362 flg2 = BUS_DMASYNC_PREWRITE;
1363 flag = BUS_DMA_WRITE;
1364 ddir = ISP_TO_DEVICE;
1365 }
1366 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen,
1367 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag);
1368 if (error) {
1369 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error);
1370 XS_SETERR(xs, HBA_BOTCH);
1371 if (error == EAGAIN || error == ENOMEM) {
1372 return (CMD_EAGAIN);
1373 } else {
1374 return (CMD_COMPLETE);
1375 }
1376 }
1377 dm_segs = dmap->dm_segs;
1378 nsegs = dmap->dm_nsegs;
1379 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, flg2);
1380 }
1381
1382 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) != CMD_QUEUED) {
1383 return (CMD_EAGAIN);
1384 } else {
1385 return (CMD_QUEUED);
1386 }
1387 }
1388
1389 static int
1390 isp_pci_intr(void *arg)
1391 {
1392 uint32_t isr;
1393 uint16_t sema, mbox;
1394 struct ispsoftc *isp = arg;
1395
1396 isp->isp_intcnt++;
1397 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) {
1398 isp->isp_intbogus++;
1399 return (0);
1400 } else {
1401 isp->isp_osinfo.onintstack = 1;
1402 isp_intr(isp, isr, sema, mbox);
1403 isp->isp_osinfo.onintstack = 0;
1404 return (1);
1405 }
1406 }
1407
1408 static void
1409 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle)
1410 {
1411 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1412 bus_dmamap_t dmap = pcs->pci_xfer_dmap[isp_handle_index(handle)];
1413 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize,
1414 xs->xs_control & XS_CTL_DATA_IN ?
1415 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1416 bus_dmamap_unload(isp->isp_dmatag, dmap);
1417 }
1418
1419 static void
1420 isp_pci_reset0(ispsoftc_t *isp)
1421 {
1422 ISP_DISABLE_INTS(isp);
1423 }
1424
1425 static void
1426 isp_pci_reset1(ispsoftc_t *isp)
1427 {
1428 if (!IS_24XX(isp)) {
1429 /* Make sure the BIOS is disabled */
1430 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
1431 }
1432 /* and enable interrupts */
1433 ISP_ENABLE_INTS(isp);
1434 }
1435
1436 static void
1437 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg)
1438 {
1439 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
1440 if (msg)
1441 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg);
1442 if (IS_SCSI(isp))
1443 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
1444 else
1445 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
1446 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
1447 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
1448 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
1449
1450
1451 if (IS_SCSI(isp)) {
1452 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
1453 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
1454 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
1455 ISP_READ(isp, CDMA_FIFO_STS));
1456 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
1457 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
1458 ISP_READ(isp, DDMA_FIFO_STS));
1459 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
1460 ISP_READ(isp, SXP_INTERRUPT),
1461 ISP_READ(isp, SXP_GROSS_ERR),
1462 ISP_READ(isp, SXP_PINS_CTRL));
1463 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
1464 }
1465 printf(" mbox regs: %x %x %x %x %x\n",
1466 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
1467 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
1468 ISP_READ(isp, OUTMAILBOX4));
1469 printf(" PCI Status Command/Status=%x\n",
1470 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG));
1471 }
NetBSD on the FriendlyARM MINI2440