sys/dev/pci/iwicreg.h

   1 /*      $NetBSD: iwicreg.h,v 1.1 2002/09/24 22:05:20 pooka Exp $        */
   2
   3 /*
   4  * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *---------------------------------------------------------------------------
  28  *
  29  *      i4b_iwic - isdn4bsd Winbond W6692 driver
  30  *      ----------------------------------------
  31  *
  32  * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic.h,v 1.1 2000/10/09 13:28:59 hm Exp $
  33  *
  34  *      last edit-date: [Sun Jan 21 11:08:44 2001]
  35  *
  36  *---------------------------------------------------------------------------*/
  37
  38 #ifndef _IWICREG_H_
  39 #define _IWICREG_H_
  40
  41 #define IWIC_BCH_A       0      /* channel A */
  42 #define IWIC_BCH_B       1      /* channel B */
  43
  44 /*---------------------------------------------------------------------------*
  45  *      FIFO depths
  46  *---------------------------------------------------------------------------*/
  47 #define IWIC_DCHAN_FIFO_LEN     64
  48 #define IWIC_BCHAN_FIFO_LEN     64
  49
  50 /*---------------------------------------------------------------------------*
  51  *      D-Channel register offsets
  52  *---------------------------------------------------------------------------*/
  53 #define D_RFIFO         0x00    /* D channel receive FIFO */
  54 #define D_XFIFO         0x04    /* D channel transmit FIFO */
  55 #define D_CMDR          0x08    /* D channel command register */
  56 #define D_MODE          0x0c    /* D channel mode control */
  57 #define D_TIMR          0x10    /* D channel timer control */
  58 #define D_EXIR          0x1c    /* D channel extended interrupt */
  59 #define D_EXIM          0x20    /* D channel extended interrupt mask */
  60 #define D_STAR          0x24    /* D channel status register */
  61 #define D_RSTA          0x28    /* D channel receive status */
  62 #define D_SAM           0x2c    /* D channel address mask 1 */
  63 #define D_SAP1          0x30    /* D channel individual SAPI 1 */
  64 #define D_SAP2          0x34    /* D channel individual SAPI 2 */
  65 #define D_TAM           0x38    /* D channel address mask 2 */
  66 #define D_TEI1          0x3c    /* D channel individual TEI 1 */
  67 #define D_TEI2          0x40    /* D channel individual TEI 2 */
  68 #define D_RBCH          0x44    /* D channel receive frame byte count high */
  69 #define D_RBCL          0x48    /* D channel receive frame byte count low */
  70 #define D_CTL           0x54    /* D channel control register */
  71
  72 /*---------------------------------------------------------------------------*
  73  *      B-channel base offsets
  74  *---------------------------------------------------------------------------*/
  75 #define B1_CHAN_OFFSET  0x80    /* B1 channel offset */
  76 #define B2_CHAN_OFFSET  0xc0    /* B2 channel offset */
  77
  78 /*---------------------------------------------------------------------------*
  79  *      B-channel register offsets, from base
  80  *---------------------------------------------------------------------------*/
  81 #define B_RFIFO         0x00    /* B channel receive FIFO */
  82 #define B_XFIFO         0x04    /* B channel transmit FIFO */
  83 #define B_CMDR          0x08    /* B channel command register */
  84 #define B_MODE          0x0c    /* B channel mode control */
  85 #define B_EXIR          0x10    /* B channel extended interrupt */
  86 #define B_EXIM          0x14    /* B channel extended interrupt mask */
  87 #define B_STAR          0x18    /* B channel status register */
  88 #define B_ADM1          0x1c    /* B channel address mask 1 */
  89 #define B_ADM2          0x20    /* B channel address mask 2 */
  90 #define B_ADR1          0x24    /* B channel address 1 */
  91 #define B_ADR2          0x28    /* B channel address 2 */
  92 #define B_RBCL          0x2c    /* B channel receive frame byte count high */
  93 #define B_RBCH          0x30    /* B channel receive frame byte count low */
  94
  95 /*---------------------------------------------------------------------------*
  96  *      Remaining control register offsets.
  97  *---------------------------------------------------------------------------*/
  98 #define ISTA            0x14    /* Interrupt status register */
  99 #define IWIC_IMASK      0x18    /* Interrupt mask register */
 100 #define TIMR2           0x4c    /* Timer 2 */
 101 #define L1_RC           0x50    /* GCI layer 1 ready code */
 102 #define CIR             0x58    /* Command/Indication receive */
 103 #define CIX             0x5c    /* Command/Indication transmit */
 104 #define SQR             0x60    /* S/Q channel receive register */
 105 #define SQX             0x64    /* S/Q channel transmit register */
 106 #define PCTL            0x68    /* Peripheral control register */
 107 #define MOR             0x6c    /* Monitor receive channel */
 108 #define MOX             0x70    /* Monitor transmit channel */
 109 #define MOSR            0x74    /* Monitor channel status register */
 110 #define MOCR            0x78    /* Monitor channel control register */
 111 #define GCR             0x7c    /* GCI mode control register */
 112 #define XADDR           0xf4    /* Peripheral address register */
 113 #define XDATA           0xf8    /* Peripheral data register */
 114 #define EPCTL           0xfc    /* Serial EEPROM control */
 115
 116 /*---------------------------------------------------------------------------*
 117  *      register bits
 118  *---------------------------------------------------------------------------*/
 119 #define D_CMDR_RACK     0x80
 120 #define D_CMDR_RRST     0x40
 121 #define D_CMDR_STT      0x10
 122 #define D_CMDR_XMS      0x08
 123 #define D_CMDR_XME      0x02
 124 #define D_CMDR_XRST     0x01
 125
 126 #define D_MODE_MMS      0x80
 127 #define D_MODE_RACT     0x40
 128 #define D_MODE_TMS      0x10
 129 #define D_MODE_TEE      0x08
 130 #define D_MODE_MFD      0x04
 131 #define D_MODE_DLP      0x02
 132 #define D_MODE_RLP      0x01
 133
 134 #define D_TIMR_CNT(i)   (((i) >> 5) & 0x07)
 135 #define D_TIMR_VAL(i)   ((i) & 0x1f)
 136
 137 #define ISTA_D_RMR      0x80
 138 #define ISTA_D_RME      0x40
 139 #define ISTA_D_XFR      0x20
 140 #define ISTA_XINT1      0x10
 141 #define ISTA_XINT0      0x08
 142 #define ISTA_D_EXI      0x04
 143 #define ISTA_B1_EXI     0x02
 144 #define ISTA_B2_EXI     0x01
 145
 146 #define IMASK_D_RMR     0x80
 147 #define IMASK_D_RME     0x40
 148 #define IMASK_D_XFR     0x20
 149 #define IMASK_XINT1     0x10
 150 #define IMASK_XINT0     0x08
 151 #define IMASK_D_EXI     0x04
 152 #define IMASK_B1_EXI    0x02
 153 #define IMASK_B2_EXI    0x01
 154
 155 #define D_EXIR_RDOV     0x80
 156 #define D_EXIR_XDUN     0x40
 157 #define D_EXIR_XCOL     0x20
 158 #define D_EXIR_TIN2     0x10
 159 #define D_EXIR_MOC      0x08
 160 #define D_EXIR_ISC      0x04
 161 #define D_EXIR_TEXP     0x02
 162 #define D_EXIR_WEXP     0x01
 163
 164 #define D_EXIM_RDOV     0x80
 165 #define D_EXIM_XDUN     0x40
 166 #define D_EXIM_XCOL     0x20
 167 #define D_EXIM_TIM2     0x10
 168 #define D_EXIM_MOC      0x08
 169 #define D_EXIM_ISC      0x04
 170 #define D_EXIM_TEXP     0x02
 171 #define D_EXIM_WEXP     0x01
 172
 173 #define D_STAR_XDOW     0x80
 174 #define D_STAR_XBZ      0x20
 175 #define D_STAR_DRDY     0x10
 176
 177 #define D_RSTA_RDOV     0x40
 178 #define D_RSTA_CRCE     0x20
 179 #define D_RSTA_RMB      0x10
 180
 181 #define D_RBCH_VN(i)    (((i) >> 6) & 0x03)
 182 #define D_RBCH_LOV      0x20
 183 #define D_RBC(h,l)      (((((h) & 0x1f)) << 8) + (l))
 184
 185 #define D_TIMR2_TMD     0x80
 186 #define D_TIMR2_TBCN(i) ((i) & 0x3f)
 187
 188 #define L1_RC_RC(i)     ((i) & 0x0f)
 189
 190 #define D_CTL_WTT(i)    (((i) > 6) & 0x03)
 191 #define D_CTL_SRST      0x20
 192 #define D_CTL_TPS       0x04
 193 #define D_CTL_OPS(i)    ((i) & 0x03)
 194
 195 #define CIR_SCC         0x80
 196 #define CIR_ICC         0x40
 197 #define CIR_CODR(i)     ((i) & 0x0f)
 198
 199 #define CIX_ECK         0x00
 200 #define CIX_RST         0x01
 201 #define CIX_SCP         0x04
 202 #define CIX_SSP         0x02
 203 #define CIX_AR8         0x08
 204 #define CIX_AR10        0x09
 205 #define CIX_EAL         0x0a
 206 #define CIX_DRC         0x0f
 207
 208 #define CIR_CE          0x07
 209 #define CIR_DRD         0x00
 210 #define CIR_LD          0x04
 211 #define CIR_ARD         0x08
 212 #define CIR_TI          0x0a
 213 #define CIR_ATI         0x0b
 214 #define CIR_AI8         0x0c
 215 #define CIR_AI10        0x0d
 216 #define CIR_CD          0x0f
 217
 218 #define SQR_XIND1       0x80
 219 #define SQR_XIND0       0x40
 220 #define SQR_MSYN        0x20
 221 #define SQR_SCIE        0x10
 222 #define SQR_S(i)        ((i) & 0x0f)
 223
 224 #define SQX_SCIE        0x10
 225 #define SQX_Q(i)        ((i) & 0x0f)
 226
 227
 228 #define B_CMDR_RACK     0x80
 229 #define B_CMDR_RRST     0x40
 230 #define B_CMDR_RACT     0x20
 231 #define B_CMDR_XMS      0x04
 232 #define B_CMDR_XME      0x02
 233 #define B_CMDR_XRST     0x01
 234
 235 #define B_MODE_MMS      0x80
 236 #define B_MODE_ITF      0x40
 237 #define B_MODE_EPCM     0x20
 238 #define B_MODE_BSW1     0x10
 239 #define B_MODE_BSW0     0x08
 240 #define B_MODE_SW56     0x04
 241 #define B_MODE_FTS1     0x02
 242 #define B_MODE_FTS0     0x01
 243
 244 #define B_EXIR_RMR      0x40
 245 #define B_EXIR_RME      0x20
 246 #define B_EXIR_RDOV     0x10
 247 #define B_EXIR_XFR      0x02
 248 #define B_EXIR_XDUN     0x01
 249
 250 #define B_EXIM_RMR      0x40
 251 #define B_EXIM_RME      0x20
 252 #define B_EXIM_RDOV     0x10
 253 #define B_EXIM_XFR      0x02
 254 #define B_EXIM_XDUN     0x01
 255
 256 #define B_STAR_RDOV     0x40
 257 #define B_STAR_CRCE     0x20
 258 #define B_STAR_RMB      0x10
 259 #define B_STAR_XDOW     0x04
 260 #define B_STAR_XBZ      0x01
 261
 262 #define B_RBC(h,l)      (((((h) & 0x1f)) << 8) + (l))
 263
 264 #endif /* !_IWICREG_H_ */