sys/dev/pci/pciide_apollo_reg.h

   1 /*      $NetBSD: pciide_apollo_reg.h,v 1.17 2007/12/25 18:33:41 perry Exp $     */
   2
   3 /*
   4  * Copyright (c) 1998 Manuel Bouyer.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  */
  27
  28 /*
  29  * Copyright (c) 2000 David Sainty.
  30  *
  31  * Redistribution and use in source and binary forms, with or without
  32  * modification, are permitted provided that the following conditions
  33  * are met:
  34  * 1. Redistributions of source code must retain the above copyright
  35  *    notice, this list of conditions and the following disclaimer.
  36  * 2. Redistributions in binary form must reproduce the above copyright
  37  *    notice, this list of conditions and the following disclaimer in the
  38  *    documentation and/or other materials provided with the distribution.
  39  * 3. All advertising materials mentioning features or use of this software
  40  *    must display the following acknowledgement:
  41  *      This product includes software developed by the University of
  42  *      California, Berkeley and its contributors.
  43  * 4. Neither the name of the University nor the names of its contributors
  44  *    may be used to endorse or promote products derived from this software
  45  *    without specific prior written permission.
  46  *
  47  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  48  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  49  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  50  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  51  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  52  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  53  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  54  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  56  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  57  * SUCH DAMAGE.
  58  *
  59  */
  60
  61 /*
  62  * Registers definitions for VIA technologies's Apollo controllers (VT82V580VO,
  63  * VT82C586A and VT82C586B). Available from http://www.via.com.tw/ or
  64  * http://www.viatech.com/
  65  */
  66
  67 /*
  68  * AMD 7x6 PCI IDE controller is a clone of the VIA apollo.
  69  *      http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf (756)
  70  *      http://www.amd.com/products/cpg/athlon/techdocs/pdf/23167.pdf (766)
  71  */
  72
  73 /*
  74  * The nVidia nForce and nForce2 IDE controllers are compatible with
  75  * the AMD controllers, but their registers are offset 0x10 bytes.
  76  */
  77
  78 /* Chip revisions */
  79 #define AMD756_CHIPREV_D2 3
  80
  81 /*
  82  * The AMD756 chip revision D2 has a bug affecting DMA (but not UDMA)
  83  * modes.  The workaround documented by AMD is to not use DMA on any
  84  * drive which does not support UDMA modes.
  85  *
  86  * See: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22591.pdf
  87  */
  88 #define AMD756_CHIPREV_DISABLEDMA(rev) ((rev) <= AMD756_CHIPREV_D2)
  89
  90 /* registers offset - vendor dependant */
  91 #define APO_VIA_REGBASE                 0x40
  92 #define APO_AMD_REGBASE                 0x40
  93 #define APO_NVIDIA_REGBASE              0x50
  94
  95 /* misc. configuration registers */
  96 #define APO_IDECONF(sc) ((sc)->sc_apo_regbase + 0x00)
  97 #define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel)))
  98 #define APO_IDECONF_SERR_EN     0x00000100 /* VIA 580 only */
  99 #define APO_IDECONF_DS_SOURCE   0x00000200 /* VIA 580 only */
 100 #define APO_IDECONF_ALT_INTR_EN 0x00000400 /* VIA 580 only */
 101 #define APO_IDECONF_PERR_EN     0x00000800 /* VIA 580 only */
 102 #define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1))
 103 #define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1))
 104 #define APO_IDECONF_DEVSEL_TME  0x00010000 /* VIA 580 only */
 105 #define APO_IDECONF_MAS_CMD_MON 0x00020000 /* VIA 580 only */
 106 #define APO_IDECONF_IO_NAT(channel) \
 107         (0x00400000 << (1 - (channel))) /* VIA 580 only */
 108 #define APO_IDECONF_FIFO_TRSH(channel, x) \
 109         ((x) & 0x3) << ((1 - (channel)) << 1 + 24)
 110 #define APO_IDECONF_FIFO_CONF_MASK 0x60000000
 111
 112 /* Misc. controls register - VIA only */
 113 #define APO_CTLMISC(sc) 0x44
 114 #define APO_CTLMISC_BM_STS_RTY  0x00000008
 115 #define APO_CTLMISC_FIFO_HWS    0x00000010
 116 #define APO_CTLMISC_WR_IRDY_WS  0x00000020
 117 #define APO_CTLMISC_RD_IRDY_WS  0x00000040
 118 #define APO_CTLMISC_INTR_SWP    0x00004000
 119 #define APO_CTLMISC_DRDY_TIME_MASK 0x00030000
 120 #define APO_CTLMISC_FIFO_FLSH_RD(channel) (0x00100000 << (1 - (channel)))
 121 #define APO_CTLMISC_FIFO_FLSH_DMA(channel) (0x00400000 << (1 - (channel)))
 122
 123 /* data port timings controls */
 124 #define APO_DATATIM(sc) ((sc)->sc_apo_regbase + 0x08)
 125 #define APO_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
 126 #define APO_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
 127         (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
 128 #define APO_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
 129         (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
 130
 131 /* misc timings control - VIA only */
 132 #define APO_MISCTIM(sc) 0x4c
 133
 134 /* Ultra-DMA control (586A/B only, amd and nvidia ) */
 135 #define APO_UDMA(sc) ((sc)->sc_apo_regbase + 0x10)
 136 #define APO_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
 137 #define APO_UDMA_TIME(channel, drive, x) (((x) & 0xf) << \
 138         (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
 139 #define APO_UDMA_PIO_MODE(channel, drive) (0x20 << \
 140         (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) /* via only */
 141 #define APO_UDMA_EN(channel, drive) (0x40 << \
 142         (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
 143 #define APO_UDMA_EN_MTH(channel, drive) (0x80 << \
 144         (((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
 145 #define APO_UDMA_CLK66(channel) (0x08 << ((1 - (channel)) << 4)) /* via only */
 146
 147 /* for via */
 148 static const int8_t via_udma133_tim[] __unused =
 149     {0x07, 0x07, 0x06, 0x04, 0x02, 0x01, 0x00};
 150 static const int8_t via_udma100_tim[] __unused =
 151     {0x07, 0x07, 0x04, 0x02, 0x01, 0x00};
 152 static const int8_t via_udma66_tim[] __unused =
 153     {0x03, 0x03, 0x02, 0x01, 0x00};
 154 static const int8_t via_udma33_tim[] __unused =
 155     {0x03, 0x02, 0x00};
 156
 157 /* for amd and nvidia */
 158 static const int8_t amd7x6_udma_tim[] __unused =
 159     {0x02, 0x01, 0x00, 0x04, 0x05, 0x06, 0x07};
 160
 161 /* for all */
 162 static const int8_t apollo_pio_set[] __unused =
 163     {0x0a, 0x0a, 0x0a, 0x02, 0x02};
 164 static const int8_t apollo_pio_rec[] __unused =
 165     {0x08, 0x08, 0x08, 0x02, 0x00};