sys/dev/pci/pciide_ixp_reg.h

   1 /* $NetBSD: pciide_ixp_reg.h,v 1.4 2007/09/10 10:35:54 cube Exp $ */
   2
   3 /*
   4  *  Copyright (c) 2004 The NetBSD Foundation.
   5  *  All rights reserved.
   6  *
   7  *  Redistribution and use in source and binary forms, with or without
   8  *  modification, are permitted provided that the following conditions
   9  *  are met:
  10  *  1. Redistributions of source code must retain the above copyright
  11  *     notice, this list of conditions and the following disclaimer.
  12  *  2. Redistributions in binary form must reproduce the above copyright
  13  *     notice, this list of conditions and the following disclaimer in the
  14  *     documentation and/or other materials provided with the distribution.
  15  *
  16  *  THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  17  *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  18  *  TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  *  PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  20  *  BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  *  POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* All values gathered from the linux driver. */
  30
  31 #define IXP_PIO_TIMING  0x40
  32 #define IXP_MDMA_TIMING 0x44
  33 #define IXP_PIO_CTL     0x48
  34 #define IXP_PIO_MODE    0x4a
  35 #define IXP_UDMA_CTL    0x54
  36 #define IXP_UDMA_MODE   0x56
  37
  38 /* First 4 bits of UDMA_CTL enable or disable UDMA for the drive */
  39 #define IXP_UDMA_ENABLE(u, c, d)        do {    \
  40         (u) |= (1 << (2 * (c) + (d)));          \
  41     } while (0)
  42 #define IXP_UDMA_DISABLE(u, c, d)       do {    \
  43         (u) &= ~(1 << (2 * (c) + (d)));         \
  44     } while (0)
  45
  46 /*
  47  * UDMA_MODE has 4 bits per drive, though only 3 are actually used
  48  * Note that in this macro u is the whole
  49  * UDMA_CTL+UDMA_MODE register (32bits).
  50  * PIO_MODE works just the same.
  51  */
  52 #define IXP_SET_MODE(u, c, d, m)        do {    \
  53         int __ixpshift = 16 + 8*(c) + 4*(d);    \
  54         (u) &= ~(0x7 << __ixpshift);            \
  55         (u) |= (((m) & 0x7) << __ixpshift);     \
  56     } while (0)
  57
  58 /*
  59  * MDMA_TIMING has one byte per drive.
  60  * PIO_TIMING works just the same.
  61  */
  62 #define IXP_SET_TIMING(m, c, d, t)      do {    \
  63         int __ixpshift = 16*(c) + 8*(d);        \
  64         (m) &= ~(0xff << __ixpshift);           \
  65         (m) |= ((t) & 0xff) << __ixpshift;      \
  66     } while (0)