sys/dev/pci/pciide_piix_reg.h

   1 /*      $NetBSD: pciide_piix_reg.h,v 1.13 2007/12/25 18:33:42 perry Exp $       */
   2
   3 /*
   4  * Copyright (c) 1998 Manuel Bouyer.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  */
  27
  28 /*
  29  * Registers definitions for Intel's PIIX serie PCI IDE controllers.
  30  * See Intel's
  31  * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR"
  32  * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and
  33  * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub"
  34  * available from http://developers.intel.com/
  35  */
  36
  37 /*
  38  * Bus master interface base address register
  39  */
  40 #define PIIX_BMIBA 0x20
  41 #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0)
  42 #define PIIX_BMIBA_RTE(x) (x & 0x000000001)
  43 #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */
  44
  45 /*
  46  * IDE timing register
  47  * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
  48  */
  49 #define PIIX_IDETIM 0x40
  50 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
  51 #define PIIX_IDETIM_SET(x, bytes, channel) \
  52         ((x) | ((bytes) << (16 * (channel))))
  53 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \
  54         ((x) & ~((bytes) << (16 * (channel))))
  55
  56 #define PIIX_IDETIM_IDE         0x8000 /* PIIX decode IDE registers */
  57 #define PIIX_IDETIM_SITRE       0x4000 /* slaves IDE timing registers
  58                                         enabled (PIIX3/4 only) */
  59 #define PIIX_IDETIM_ISP_MASK    0x3000 /* IOrdy sample point */
  60 #define PIIX_IDETIM_ISP_SHIFT   12
  61 #define PIIX_IDETIM_ISP_SET(x)  ((x) << PIIX_IDETIM_ISP_SHIFT)
  62 #define PIIX_IDETIM_RTC_MASK    0x0300 /* recovery time */
  63 #define PIIX_IDETIM_RTC_SHIFT   8
  64 #define PIIX_IDETIM_RTC_SET(x)  ((x) << PIIX_IDETIM_RTC_SHIFT)
  65 #define PIIX_IDETIM_DTE(d)      (0x0008 << (4 * (d))) /* DMA timing only */
  66 #define PIIX_IDETIM_PPE(d)      (0x0004 << (4 * (d))) /* prefetch/posting */
  67 #define PIIX_IDETIM_IE(d)       (0x0002 << (4 * (d))) /* IORDY enable */
  68 #define PIIX_IDETIM_TIME(d)     (0x0001 << (4 * (d))) /* Fast timing enable */
  69 /*
  70  * Slave IDE timing register (PIIX3/4 only)
  71  * This register must be enabled via the PIIX_IDETIM_SITRE bit
  72  */
  73 #define PIIX_SIDETIM 0x44
  74 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
  75 #define PIIX_SIDETIM_ISP_SHIFT  2
  76 #define PIIX_SIDETIM_ISP_SET(x, channel) \
  77         (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4)))
  78 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4))
  79 #define PIIX_SIDETIM_RTC_SHIFT  0
  80 #define PIIX_SIDETIM_RTC_SET(x, channel) \
  81         (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4)))
  82
  83 /*
  84  * Ultra DMA/33 register (PIIX4 only)
  85  */
  86 #define PIIX_UDMAREG 0x48
  87 /* Control register */
  88 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive)))
  89 /* Ultra DMA/33 timing register (PIIX4 only) */
  90 #define PIIX_UDMATIM 0x4a
  91 #define PIIX_UDMATIM_SHIFT 16
  92 #define PIIX_UDMATIM_SET(x, channel, drive) \
  93         (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
  94
  95 /*
  96  * IDE config register (ICH/ICH0/ICH2 only)
  97  */
  98 #define PIIX_CONFIG     0x54
  99 #define PIIX_CONFIG_PINGPONG    0x0400
 100 /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */
 101 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive)))
 102 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive)))
 103 /* The following are only for the 82801BA (ICH2) */
 104 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive)))
 105
 106 /*
 107  * these tables define the differents values to upload to the
 108  * ISP and RTC registers for the various PIO and DMA mode
 109  * (from the PIIX4 doc).
 110  */
 111 static const int8_t piix_isp_pio[] __unused =
 112     {0x00, 0x00, 0x01, 0x02, 0x02};
 113 static const int8_t piix_rtc_pio[] __unused =
 114     {0x00, 0x00, 0x00, 0x01, 0x03};
 115 static const int8_t piix_isp_dma[] __unused =
 116     {0x00, 0x02, 0x02};
 117 static const int8_t piix_rtc_dma[] __unused =
 118     {0x00, 0x02, 0x03};
 119 static const int8_t piix4_sct_udma[] __unused =
 120     {0x00, 0x01, 0x02, 0x01, 0x02, 0x01};
 121
 122 /*
 123  * ICH5/ICH5R SATA registers definitions
 124  */
 125 #define ICH5_SATA_MAP           0x90 /* Address Map Register */
 126 #define ICH5_SATA_MAP_MV_MASK   0x07 /* Map Value mask */
 127 #define ICH5_SATA_MAP_COMBINED  0x04 /* Combined mode */
 128
 129 #define ICH5_SATA_PI            0x09 /* Program Interface register */
 130 #define ICH5_SATA_PI_PRI_NATIVE 0x01 /* Put Pri IDE channel in native mode */
 131 #define ICH5_SATA_PI_SEC_NATIVE 0x04 /* Put Sec IDE channel in native mode */
 132
 133 #define ICH_SATA_PCS            0x92 /* Port Control and Status Register */
 134 #define ICH_SATA_PCS_P0E        0x01 /* Port 0 enabled */
 135 #define ICH_SATA_PCS_P1E        0x02 /* Port 1 enabled */
 136 #define ICH_SATA_PCS_P0P        0x10 /* Port 0 present */
 137 #define ICH_SATA_PCS_P1P        0x20 /* Port 1 present */
 138
 139 /*
 140  *  * ICH6/ICH7 SATA registers definitions
 141  *   */
 142 #define ICH6_SATA_MAP_CMB_MASK  0x03 /* Combined mode bits */
 143 #define ICH6_SATA_MAP_CMB_PRI   0x01 /* Combined mode, IDE Primary */
 144 #define ICH6_SATA_MAP_CMB_SEC   0x02 /* Combined mode, IDE Secondary */
 145 #define ICH7_SATA_MAP_SMS_MASK  0xc0 /* SATA Mode Select */
 146 #define ICH7_SATA_MAP_SMS_IDE   0x00
 147 #define ICH7_SATA_MAP_SMS_AHCI  0x40
 148 #define ICH7_SATA_MAP_SMS_RAID  0x80