sys/dev/pci/pcivar.h

   1 /*      $NetBSD: pcivar.h,v 1.82 2008/05/30 19:26:35 ad Exp $   */
   2
   3 /*
   4  * Copyright (c) 1996, 1997 Christopher G. Demetriou.  All rights reserved.
   5  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Charles M. Hannum.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _DEV_PCI_PCIVAR_H_
  34 #define _DEV_PCI_PCIVAR_H_
  35
  36 /*
  37  * Definitions for PCI autoconfiguration.
  38  *
  39  * This file describes types and functions which are used for PCI
  40  * configuration.  Some of this information is machine-specific, and is
  41  * provided by pci_machdep.h.
  42  */
  43
  44 #include <sys/device.h>
  45 #include <sys/pmf.h>
  46 #include <sys/bus.h>
  47 #include <dev/pci/pcireg.h>
  48
  49 /*
  50  * Structures and definitions needed by the machine-dependent header.
  51  */
  52 typedef u_int32_t pcireg_t;             /* configuration space register XXX */
  53 struct pcibus_attach_args;
  54 struct pci_softc;
  55
  56 #ifdef _KERNEL
  57 /*
  58  * Machine-dependent definitions.
  59  */
  60 #include <machine/pci_machdep.h>
  61
  62 /*
  63  * PCI bus attach arguments.
  64  */
  65 struct pcibus_attach_args {
  66         char            *_pba_busname;  /* XXX placeholder */
  67         bus_space_tag_t pba_iot;        /* pci i/o space tag */
  68         bus_space_tag_t pba_memt;       /* pci mem space tag */
  69         bus_dma_tag_t pba_dmat;         /* DMA tag */
  70         bus_dma_tag_t pba_dmat64;       /* DMA tag */
  71         pci_chipset_tag_t pba_pc;
  72         int             pba_flags;      /* flags; see below */
  73
  74         int             pba_bus;        /* PCI bus number */
  75
  76         /*
  77          * Pointer to the pcitag of our parent bridge.  If there is no
  78          * parent bridge, then we assume we are a root bus.
  79          */
  80         pcitag_t        *pba_bridgetag;
  81
  82         /*
  83          * Interrupt swizzling information.  These fields
  84          * are only used by secondary busses.
  85          */
  86         u_int           pba_intrswiz;   /* how to swizzle pins */
  87         pcitag_t        pba_intrtag;    /* intr. appears to come from here */
  88 };
  89
  90 /*
  91  * PCI device attach arguments.
  92  */
  93 struct pci_attach_args {
  94         bus_space_tag_t pa_iot;         /* pci i/o space tag */
  95         bus_space_tag_t pa_memt;        /* pci mem space tag */
  96         bus_dma_tag_t pa_dmat;          /* DMA tag */
  97         bus_dma_tag_t pa_dmat64;        /* DMA tag */
  98         pci_chipset_tag_t pa_pc;
  99         int             pa_flags;       /* flags; see below */
 100
 101         u_int           pa_bus;
 102         u_int           pa_device;
 103         u_int           pa_function;
 104         pcitag_t        pa_tag;
 105         pcireg_t        pa_id, pa_class;
 106
 107         /*
 108          * Interrupt information.
 109          *
 110          * "Intrline" is used on systems whose firmware puts
 111          * the right routing data into the line register in
 112          * configuration space.  The rest are used on systems
 113          * that do not.
 114          */
 115         u_int           pa_intrswiz;    /* how to swizzle pins if ppb */
 116         pcitag_t        pa_intrtag;     /* intr. appears to come from here */
 117         pci_intr_pin_t  pa_intrpin;     /* intr. appears on this pin */
 118         pci_intr_line_t pa_intrline;    /* intr. routing information */
 119         pci_intr_pin_t  pa_rawintrpin;  /* unswizzled pin */
 120 };
 121
 122 /*
 123  * Flags given in the bus and device attachment args.
 124  */
 125 #define PCI_FLAGS_IO_ENABLED    0x01            /* I/O space is enabled */
 126 #define PCI_FLAGS_MEM_ENABLED   0x02            /* memory space is enabled */
 127 #define PCI_FLAGS_MRL_OKAY      0x04            /* Memory Read Line okay */
 128 #define PCI_FLAGS_MRM_OKAY      0x08            /* Memory Read Multiple okay */
 129 #define PCI_FLAGS_MWI_OKAY      0x10            /* Memory Write and Invalidate
 130                                                    okay */
 131
 132 /*
 133  * PCI device 'quirks'.
 134  *
 135  * In general strange behaviour which can be handled by a driver (e.g.
 136  * a bridge's inability to pass a type of access correctly) should be.
 137  * The quirks table should only contain information which impacts
 138  * the operation of the MI PCI code and which can't be pushed lower
 139  * (e.g. because it's unacceptable to require a driver to be present
 140  * for the information to be known).
 141  */
 142 struct pci_quirkdata {
 143         pci_vendor_id_t         vendor;         /* Vendor ID */
 144         pci_product_id_t        product;        /* Product ID */
 145         int                     quirks;         /* quirks; see below */
 146 };
 147 #define PCI_QUIRK_MULTIFUNCTION         1
 148 #define PCI_QUIRK_MONOFUNCTION          2
 149 #define PCI_QUIRK_SKIP_FUNC(n)          (4 << n)
 150 #define PCI_QUIRK_SKIP_FUNC0            PCI_QUIRK_SKIP_FUNC(0)
 151 #define PCI_QUIRK_SKIP_FUNC1            PCI_QUIRK_SKIP_FUNC(1)
 152 #define PCI_QUIRK_SKIP_FUNC2            PCI_QUIRK_SKIP_FUNC(2)
 153 #define PCI_QUIRK_SKIP_FUNC3            PCI_QUIRK_SKIP_FUNC(3)
 154 #define PCI_QUIRK_SKIP_FUNC4            PCI_QUIRK_SKIP_FUNC(4)
 155 #define PCI_QUIRK_SKIP_FUNC5            PCI_QUIRK_SKIP_FUNC(5)
 156 #define PCI_QUIRK_SKIP_FUNC6            PCI_QUIRK_SKIP_FUNC(6)
 157 #define PCI_QUIRK_SKIP_FUNC7            PCI_QUIRK_SKIP_FUNC(7)
 158
 159 struct pci_conf_state {
 160         pcireg_t reg[16];
 161 };
 162
 163 struct pci_child {
 164         device_t                c_dev;
 165         bool                    c_psok;
 166         pcireg_t                c_powerstate;
 167         struct pci_conf_state   c_conf;
 168 };
 169
 170 struct pci_softc {
 171         device_t sc_dev;
 172         bus_space_tag_t sc_iot, sc_memt;
 173         bus_dma_tag_t sc_dmat;
 174         bus_dma_tag_t sc_dmat64;
 175         pci_chipset_tag_t sc_pc;
 176         int sc_bus, sc_maxndevs;
 177         pcitag_t *sc_bridgetag;
 178         u_int sc_intrswiz;
 179         pcitag_t sc_intrtag;
 180         int sc_flags;
 181         /* accounting of child devices */
 182         struct pci_child sc_devices[32*8];
 183 #define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)]
 184 };
 185
 186 extern struct cfdriver pci_cd;
 187
 188 int pcibusprint(void *, const char *);
 189
 190 /*
 191  * Configuration space access and utility functions.  (Note that most,
 192  * e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.)
 193  */
 194 int     pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *);
 195 pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int);
 196 int     pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t,
 197             bus_addr_t *, bus_size_t *, int *);
 198 int     pci_mapreg_map(struct pci_attach_args *, int, pcireg_t, int,
 199             bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *,
 200             bus_size_t *);
 201 int     pci_mapreg_submap(struct pci_attach_args *, int, pcireg_t, int,
 202             bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *,
 203             bus_addr_t *, bus_size_t *);
 204
 205 int pci_find_rom(struct pci_attach_args *, bus_space_tag_t, bus_space_handle_t,
 206             int, bus_space_handle_t *, bus_size_t *);
 207
 208 int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *);
 209
 210 /*
 211  * Helper functions for autoconfiguration.
 212  */
 213 int     pci_probe_device(struct pci_softc *, pcitag_t tag,
 214             int (*)(struct pci_attach_args *), struct pci_attach_args *);
 215 void    pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t);
 216 void    pci_conf_print(pci_chipset_tag_t, pcitag_t,
 217             void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *));
 218 const struct pci_quirkdata *
 219         pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t);
 220
 221 /*
 222  * Helper functions for user access to the PCI bus.
 223  */
 224 struct proc;
 225 int     pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *,
 226             int flag, struct lwp *);
 227
 228 /*
 229  * Power Management (PCI 2.2)
 230  */
 231
 232 #define PCI_PWR_D0      0
 233 #define PCI_PWR_D1      1
 234 #define PCI_PWR_D2      2
 235 #define PCI_PWR_D3      3
 236 int     pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *);
 237
 238 /*
 239  * Vital Product Data (PCI 2.2)
 240  */
 241 int     pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
 242 int     pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
 243
 244 /*
 245  * Misc.
 246  */
 247 const char *pci_findvendor(pcireg_t);
 248 const char *pci_findproduct(pcireg_t);
 249 int     pci_find_device(struct pci_attach_args *pa,
 250                         int (*match)(struct pci_attach_args *));
 251 int     pci_dma64_available(struct pci_attach_args *);
 252 void    pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
 253 void    pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
 254 int     pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *);
 255 int     pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t);
 256 int     pci_activate(pci_chipset_tag_t, pcitag_t, device_t,
 257     int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t));
 258 int     pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t);
 259 void    pci_disable_retry(pci_chipset_tag_t, pcitag_t);
 260
 261 /*
 262  * Device abstraction for inheritance by elanpci(4), for example.
 263  */
 264 int pcimatch(device_t, cfdata_t, void *);
 265 void pciattach(device_t, device_t, void *);
 266 int pcidetach(device_t, int);
 267 void pcidevdetached(device_t, device_t);
 268 int pcirescan(device_t, const char *, const int *);
 269
 270 /*
 271  * Interrupts.
 272  */
 273 #define PCI_INTR_MPSAFE         1
 274
 275 int     pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t);
 276
 277 #endif /* _KERNEL */
 278
 279 #endif /* _DEV_PCI_PCIVAR_H_ */