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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / pdcide.c
blob7708db283f2019f844cf723a3824100e8fcb2c3f
1 /* $NetBSD: pdcide.c,v 1.26 2008/03/18 20:46:37 cube Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: pdcide.c,v 1.26 2008/03/18 20:46:37 cube Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32
33 #include <dev/pci/pcivar.h>
34 #include <dev/pci/pcidevs.h>
35 #include <dev/pci/pciidereg.h>
36 #include <dev/pci/pciidevar.h>
37 #include <dev/pci/pciide_pdc202xx_reg.h>
38
39 static void pdc202xx_chip_map(struct pciide_softc *, struct pci_attach_args *);
40 static void pdc202xx_setup_channel(struct ata_channel *);
41 static void pdc20268_setup_channel(struct ata_channel *);
42 static int pdc202xx_pci_intr(void *);
43 static int pdc20265_pci_intr(void *);
44 static void pdc20262_dma_start(void *, int, int);
45 static int pdc20262_dma_finish(void *, int, int, int);
46
47 static int pdcide_match(device_t, cfdata_t, void *);
48 static void pdcide_attach(device_t, device_t, void *);
49
50 CFATTACH_DECL_NEW(pdcide, sizeof(struct pciide_softc),
51 pdcide_match, pdcide_attach, NULL, NULL);
52
53 static const struct pciide_product_desc pciide_promise_products[] = {
54 { PCI_PRODUCT_PROMISE_PDC20246,
55 0,
56 "Promise Ultra33/ATA Bus Master IDE Accelerator",
57 pdc202xx_chip_map,
58 },
59 { PCI_PRODUCT_PROMISE_PDC20262,
60 0,
61 "Promise Ultra66/ATA Bus Master IDE Accelerator",
62 pdc202xx_chip_map,
63 },
64 { PCI_PRODUCT_PROMISE_PDC20267,
65 0,
66 "Promise Ultra100/ATA Bus Master IDE Accelerator",
67 pdc202xx_chip_map,
68 },
69 { PCI_PRODUCT_PROMISE_PDC20265,
70 0,
71 "Promise Ultra100/ATA Bus Master IDE Accelerator",
72 pdc202xx_chip_map,
73 },
74 { PCI_PRODUCT_PROMISE_PDC20268,
75 0,
76 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator",
77 pdc202xx_chip_map,
78 },
79 { PCI_PRODUCT_PROMISE_PDC20270,
80 0,
81 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator",
82 pdc202xx_chip_map,
83 },
84 { PCI_PRODUCT_PROMISE_PDC20269,
85 0,
86 "Promise Ultra133/ATA Bus Master IDE Accelerator",
87 pdc202xx_chip_map,
88 },
89 { PCI_PRODUCT_PROMISE_PDC20276,
90 0,
91 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator",
92 pdc202xx_chip_map,
93 },
94 { PCI_PRODUCT_PROMISE_PDC20275,
95 0,
96 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)",
97 pdc202xx_chip_map,
98 },
99 { PCI_PRODUCT_PROMISE_PDC20271,
100 0,
101 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator",
102 pdc202xx_chip_map,
103 },
104 { PCI_PRODUCT_PROMISE_PDC20277,
105 0,
106 "Promise Fasttrak133 Lite Bus Master IDE Accelerator",
107 pdc202xx_chip_map,
108 },
109 { 0,
110 0,
111 NULL,
112 NULL
113 }
114 };
115
116 static int
117 pdcide_match(device_t parent, cfdata_t match, void *aux)
118 {
119 struct pci_attach_args *pa = aux;
120
121 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) {
122 if (pciide_lookup_product(pa->pa_id, pciide_promise_products))
123 return (2);
124 }
125 return (0);
126 }
127
128 static void
129 pdcide_attach(device_t parent, device_t self, void *aux)
130 {
131 struct pci_attach_args *pa = aux;
132 struct pciide_softc *sc = device_private(self);
133
134 sc->sc_wdcdev.sc_atac.atac_dev = self;
135
136 pciide_common_attach(sc, pa,
137 pciide_lookup_product(pa->pa_id, pciide_promise_products));
138
139 }
140
141 /* Macros to test product */
142 #define PDC_IS_262(sc) \
143 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 || \
144 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \
145 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \
146 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \
147 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \
148 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \
149 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \
150 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \
151 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \
152 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
153 #define PDC_IS_265(sc) \
154 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 || \
155 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265 || \
156 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \
157 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \
158 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \
159 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \
160 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \
161 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \
162 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
163 #define PDC_IS_268(sc) \
164 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20268 || \
165 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20270 || \
166 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \
167 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \
168 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \
169 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \
170 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
171 #define PDC_IS_276(sc) \
172 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20269 || \
173 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20276 || \
174 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20275 || \
175 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20271 || \
176 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20277)
177
178 static void
179 pdc202xx_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
180 {
181 struct pciide_channel *cp;
182 int channel;
183 pcireg_t interface, st, mode;
184 bus_size_t cmdsize, ctlsize;
185
186 if (!PDC_IS_268(sc)) {
187 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
188 ATADEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n",
189 st), DEBUG_PROBE);
190 /* turn off RAID mode */
191 if (st & PDC2xx_STATE_IDERAID) {
192 ATADEBUG_PRINT(("pdc202xx_setup_chip: turning off RAID mode\n"), DEBUG_PROBE);
193 st &= ~PDC2xx_STATE_IDERAID;
194 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st);
195 }
196 } else
197 st = PDC2xx_STATE_NATIVE | PDC262_STATE_EN(0) | PDC262_STATE_EN(1);
198
199 if (pciide_chipen(sc, pa) == 0)
200 return;
201
202 /*
203 * can't rely on the PCI_CLASS_REG content if the chip was in raid
204 * mode. We have to fake interface
205 */
206 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1);
207 if (st & PDC2xx_STATE_NATIVE)
208 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
209
210 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
211 "bus-master DMA support present");
212 pciide_mapreg_dma(sc, pa);
213 aprint_verbose("\n");
214 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
215 if (sc->sc_dma_ok) {
216 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
217 sc->sc_wdcdev.irqack = pciide_irqack;
218 }
219 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
220 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
221 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
222 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
223 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
224 if (PDC_IS_276(sc))
225 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
226 else if (PDC_IS_265(sc))
227 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
228 else if (PDC_IS_262(sc))
229 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
230 else
231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
232 sc->sc_wdcdev.sc_atac.atac_set_modes = PDC_IS_268(sc) ?
233 pdc20268_setup_channel : pdc202xx_setup_channel;
234 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
235 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
236
237 wdc_allocate_regs(&sc->sc_wdcdev);
238
239 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20262 ||
240 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20267 ||
241 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_PDC20265) {
242 sc->sc_wdcdev.dma_start = pdc20262_dma_start;
243 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish;
244 }
245
246 if (!PDC_IS_268(sc)) {
247 /* setup failsafe defaults */
248 mode = 0;
249 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]);
250 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]);
251 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]);
252 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]);
253 for (channel = 0;
254 channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
255 channel++) {
256 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
257 "drive 0 initial timings 0x%x, now 0x%x\n",
258 channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
259 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp),
260 DEBUG_PROBE);
261 pci_conf_write(sc->sc_pc, sc->sc_tag,
262 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp);
263 ATADEBUG_PRINT(("pdc202xx_setup_chip: channel %d "
264 "drive 1 initial timings 0x%x, now 0x%x\n",
265 channel, pci_conf_read(sc->sc_pc, sc->sc_tag,
266 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE);
267 pci_conf_write(sc->sc_pc, sc->sc_tag,
268 PDC2xx_TIM(channel, 1), mode);
269 }
270
271 mode = PDC2xx_SCR_DMA;
272 if (PDC_IS_265(sc)) {
273 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT);
274 } else if (PDC_IS_262(sc)) {
275 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT);
276 } else {
277 /* the BIOS set it up this way */
278 mode = PDC2xx_SCR_SET_GEN(mode, 0x1);
279 }
280 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */
281 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */
282 ATADEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, "
283 "now 0x%x\n",
284 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
285 PDC2xx_SCR),
286 mode), DEBUG_PROBE);
287 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
288 PDC2xx_SCR, mode);
289
290 /* controller initial state register is OK even without BIOS */
291 /* Set DMA mode to IDE DMA compatibility */
292 mode =
293 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM);
294 ATADEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode),
295 DEBUG_PROBE);
296 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM,
297 mode | 0x1);
298 mode =
299 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM);
300 ATADEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE);
301 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM,
302 mode | 0x1);
303 }
304 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
305 channel++) {
306 cp = &sc->pciide_channels[channel];
307 if (pciide_chansetup(sc, channel, interface) == 0)
308 continue;
309 if ((st & (PDC_IS_262(sc) ?
310 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) {
311 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
312 "%s channel ignored (disabled)\n", cp->name);
313 cp->ata_channel.ch_flags |= ATACH_DISABLED;
314 continue;
315 }
316 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
317 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr);
318 /* clear interrupt, in case there is one pending */
319 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
320 IDEDMA_CTL_INTR);
321 }
322 return;
323 }
324
325 static void
326 pdc202xx_setup_channel(struct ata_channel *chp)
327 {
328 struct ata_drive_datas *drvp;
329 int drive, s;
330 pcireg_t mode, st;
331 u_int32_t idedma_ctl, scr, atapi;
332 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
333 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
334 int channel = chp->ch_channel;
335
336 /* setup DMA if needed */
337 pciide_channel_dma_setup(cp);
338
339 idedma_ctl = 0;
340 ATADEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n",
341 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
342 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)),
343 DEBUG_PROBE);
344
345 /* Per channel settings */
346 if (PDC_IS_262(sc)) {
347 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
348 PDC262_U66);
349 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE);
350 /* Trim UDMA mode */
351 if ((st & PDC262_STATE_80P(channel)) != 0 ||
352 (chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
353 chp->ch_drive[0].UDMA_mode <= 2) ||
354 (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&
355 chp->ch_drive[1].UDMA_mode <= 2)) {
356 if (chp->ch_drive[0].UDMA_mode > 2)
357 chp->ch_drive[0].UDMA_mode = 2;
358 if (chp->ch_drive[1].UDMA_mode > 2)
359 chp->ch_drive[1].UDMA_mode = 2;
360 }
361 /* Set U66 if needed */
362 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA &&
363 chp->ch_drive[0].UDMA_mode > 2) ||
364 (chp->ch_drive[1].drive_flags & DRIVE_UDMA &&
365 chp->ch_drive[1].UDMA_mode > 2))
366 scr |= PDC262_U66_EN(channel);
367 else
368 scr &= ~PDC262_U66_EN(channel);
369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
370 PDC262_U66, scr);
371 ATADEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n",
372 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
373 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh,
374 PDC262_ATAPI(channel))), DEBUG_PROBE);
375 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI ||
376 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) {
377 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&
378 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&
379 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) ||
380 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) &&
381 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) &&
382 (chp->ch_drive[0].drive_flags & DRIVE_DMA)))
383 atapi = 0;
384 else
385 atapi = PDC262_ATAPI_UDMA;
386 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
387 PDC262_ATAPI(channel), atapi);
388 }
389 }
390 for (drive = 0; drive < 2; drive++) {
391 drvp = &chp->ch_drive[drive];
392 /* If no drive, skip */
393 if ((drvp->drive_flags & DRIVE) == 0)
394 continue;
395 mode = 0;
396 if (drvp->drive_flags & DRIVE_UDMA) {
397 /* use Ultra/DMA */
398 s = splbio();
399 drvp->drive_flags &= ~DRIVE_DMA;
400 splx(s);
401 mode = PDC2xx_TIM_SET_MB(mode,
402 pdc2xx_udma_mb[drvp->UDMA_mode]);
403 mode = PDC2xx_TIM_SET_MC(mode,
404 pdc2xx_udma_mc[drvp->UDMA_mode]);
405 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
406 } else if (drvp->drive_flags & DRIVE_DMA) {
407 mode = PDC2xx_TIM_SET_MB(mode,
408 pdc2xx_dma_mb[drvp->DMA_mode]);
409 mode = PDC2xx_TIM_SET_MC(mode,
410 pdc2xx_dma_mc[drvp->DMA_mode]);
411 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
412 } else {
413 mode = PDC2xx_TIM_SET_MB(mode,
414 pdc2xx_dma_mb[0]);
415 mode = PDC2xx_TIM_SET_MC(mode,
416 pdc2xx_dma_mc[0]);
417 }
418 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]);
419 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]);
420 if (drvp->drive_flags & DRIVE_ATA)
421 mode |= PDC2xx_TIM_PRE;
422 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY;
423 if (drvp->PIO_mode >= 3) {
424 mode |= PDC2xx_TIM_IORDY;
425 if (drive == 0)
426 mode |= PDC2xx_TIM_IORDYp;
427 }
428 ATADEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d "
429 "timings 0x%x\n",
430 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
431 chp->ch_channel, drive, mode), DEBUG_PROBE);
432 pci_conf_write(sc->sc_pc, sc->sc_tag,
433 PDC2xx_TIM(chp->ch_channel, drive), mode);
434 }
435 if (idedma_ctl != 0) {
436 /* Add software bits in status register */
437 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
438 0, idedma_ctl);
439 }
440 }
441
442 static void
443 pdc20268_setup_channel(struct ata_channel *chp)
444 {
445 struct ata_drive_datas *drvp;
446 int drive, s;
447 u_int32_t idedma_ctl;
448 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
449 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
450 int u100;
451
452 /* setup DMA if needed */
453 pciide_channel_dma_setup(cp);
454
455 idedma_ctl = 0;
456
457 /* I don't know what this is for, FreeBSD does it ... */
458 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
459 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->ch_channel, 0x0b);
460
461 /*
462 * cable type detect, from FreeBSD
463 */
464 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
465 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->ch_channel) & 0x04) ?
466 0 : 1;
467
468 for (drive = 0; drive < 2; drive++) {
469 drvp = &chp->ch_drive[drive];
470 /* If no drive, skip */
471 if ((drvp->drive_flags & DRIVE) == 0)
472 continue;
473 if (drvp->drive_flags & DRIVE_UDMA) {
474 /* use Ultra/DMA */
475 s = splbio();
476 drvp->drive_flags &= ~DRIVE_DMA;
477 splx(s);
478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
479 if (drvp->UDMA_mode > 2 && u100 == 0)
480 drvp->UDMA_mode = 2;
481 } else if (drvp->drive_flags & DRIVE_DMA) {
482 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
483 }
484 }
485 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
486 if (idedma_ctl != 0) {
487 /* Add software bits in status register */
488 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
489 0, idedma_ctl);
490 }
491 }
492
493 static int
494 pdc202xx_pci_intr(void *arg)
495 {
496 struct pciide_softc *sc = arg;
497 struct pciide_channel *cp;
498 struct ata_channel *wdc_cp;
499 int i, rv, crv;
500 u_int32_t scr;
501
502 rv = 0;
503 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR);
504 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
505 cp = &sc->pciide_channels[i];
506 wdc_cp = &cp->ata_channel;
507 /* If a compat channel skip. */
508 if (cp->compat)
509 continue;
510 if (scr & PDC2xx_SCR_INT(i)) {
511 crv = wdcintr(wdc_cp);
512 if (crv == 0)
513 aprint_error("%s:%d: bogus intr (reg 0x%x)\n",
514 device_xname(
515 sc->sc_wdcdev.sc_atac.atac_dev), i, scr);
516 else
517 rv = 1;
518 }
519 }
520 return rv;
521 }
522
523 static int
524 pdc20265_pci_intr(void *arg)
525 {
526 struct pciide_softc *sc = arg;
527 struct pciide_channel *cp;
528 struct ata_channel *wdc_cp;
529 int i, rv, crv;
530 u_int32_t dmastat;
531
532 rv = 0;
533 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
534 cp = &sc->pciide_channels[i];
535 wdc_cp = &cp->ata_channel;
536 /* If a compat channel skip. */
537 if (cp->compat)
538 continue;
539 #if 0
540 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * i, 0x0b);
541 if ((bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * i) & 0x20) == 0)
542 continue;
543 #endif
544 /*
545 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously,
546 * however it asserts INT in IDEDMA_CTL even for non-DMA ops.
547 * So use it instead (requires 2 reg reads instead of 1,
548 * but we can't do it another way).
549 */
550 dmastat = bus_space_read_1(sc->sc_dma_iot,
551 cp->dma_iohs[IDEDMA_CTL], 0);
552 if((dmastat & IDEDMA_CTL_INTR) == 0)
553 continue;
554 crv = wdcintr(wdc_cp);
555 if (crv == 0)
556 aprint_error("%s:%d: bogus intr\n",
557 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i);
558 else
559 rv = 1;
560 }
561 return rv;
562 }
563
564 static void
565 pdc20262_dma_start(void *v, int channel, int drive)
566 {
567 struct pciide_softc *sc = v;
568 struct pciide_dma_maps *dma_maps =
569 &sc->pciide_channels[channel].dma_maps[drive];
570 int atapi;
571
572 if (dma_maps->dma_flags & WDC_DMA_LBA48) {
573 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ?
574 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE;
575 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1;
576 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
577 PDC262_ATAPI(channel), atapi);
578 }
579
580 pciide_dma_start(v, channel, drive);
581 }
582
583 static int
584 pdc20262_dma_finish(void *v, int channel, int drive, int force)
585 {
586 struct pciide_softc *sc = v;
587 struct pciide_dma_maps *dma_maps =
588 &sc->pciide_channels[channel].dma_maps[drive];
589 struct ata_channel *chp;
590 int atapi, error;
591
592 error = pciide_dma_finish(v, channel, drive, force);
593
594 if (dma_maps->dma_flags & WDC_DMA_LBA48) {
595 chp = sc->wdc_chanarray[channel];
596 atapi = 0;
597 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI ||
598 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) {
599 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) ||
600 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) ||
601 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) &&
602 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) ||
603 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) ||
604 !(chp->ch_drive[0].drive_flags & DRIVE_DMA)))
605 atapi = PDC262_ATAPI_UDMA;
606 }
607 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh,
608 PDC262_ATAPI(channel), atapi);
609 }
610
611 return error;
612 }
NetBSD on the FriendlyARM MINI2440