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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / pdcsata.c
blobe0d4a16c609abaad95e3ae79701c6f75a4817621
1 /* $NetBSD: pdcsata.c,v 1.17 2009/10/19 18:41:16 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 2004, Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.17 2009/10/19 18:41:16 bouyer Exp $");
29
30 #include <sys/types.h>
31 #include <sys/malloc.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34
35 #include <dev/pci/pcivar.h>
36 #include <dev/pci/pcidevs.h>
37 #include <dev/pci/pciidereg.h>
38 #include <dev/pci/pciidevar.h>
39 #include <dev/ata/atareg.h>
40 #include <dev/ata/satavar.h>
41 #include <dev/ata/satareg.h>
42
43 #define PDC203xx_SATA_NCHANNELS 4
44 #define PDC203xx_COMBO_NCHANNELS 3
45 #define PDC40718_SATA_NCHANNELS 4
46 #define PDC20575_COMBO_NCHANNELS 3
47
48 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */
49
50 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80)
51 #define PDC_ERRMASK 0x00780700
52
53 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8))
54 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch)
55 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch)
56 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch)
57 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch)
58
59 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
60 static void pdc203xx_setup_channel(struct ata_channel *);
61 static void pdc203xx_irqack(struct ata_channel *);
62 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int);
63 static void pdc203xx_dma_start(void *,int ,int);
64 static int pdc203xx_dma_finish(void *, int, int, int);
65 static void pdc203xx_combo_probe(struct ata_channel *);
66 static int pdcsata_pci_intr(void *);
67 static void pdcsata_do_reset(struct ata_channel *, int);
68
69 static int pdcsata_match(device_t, cfdata_t, void *);
70 static void pdcsata_attach(device_t, device_t, void *);
71
72 CFATTACH_DECL_NEW(pdcsata, sizeof(struct pciide_softc),
73 pdcsata_match, pdcsata_attach, NULL, NULL);
74
75 static const struct pciide_product_desc pciide_pdcsata_products[] = {
76 { PCI_PRODUCT_PROMISE_PDC20318,
77 0,
78 "Promise PDC20318 SATA150 controller",
79 pdcsata_chip_map,
80 },
81 { PCI_PRODUCT_PROMISE_PDC20319,
82 0,
83 "Promise PDC20319 SATA150 controller",
84 pdcsata_chip_map,
85 },
86 { PCI_PRODUCT_PROMISE_PDC20371,
87 0,
88 "Promise PDC20371 SATA150 controller",
89 pdcsata_chip_map,
90 },
91 { PCI_PRODUCT_PROMISE_PDC20375,
92 0,
93 "Promise PDC20375 SATA150 controller",
94 pdcsata_chip_map,
95 },
96 { PCI_PRODUCT_PROMISE_PDC20376,
97 0,
98 "Promise PDC20376 SATA150 controller",
99 pdcsata_chip_map,
100 },
101 { PCI_PRODUCT_PROMISE_PDC20377,
102 0,
103 "Promise PDC20377 SATA150 controller",
104 pdcsata_chip_map,
105 },
106 { PCI_PRODUCT_PROMISE_PDC20378,
107 0,
108 "Promise PDC20378 SATA150 controller",
109 pdcsata_chip_map,
110 },
111 { PCI_PRODUCT_PROMISE_PDC20379,
112 0,
113 "Promise PDC20379 SATA150 controller",
114 pdcsata_chip_map,
115 },
116 { PCI_PRODUCT_PROMISE_PDC40518,
117 0,
118 "Promise PDC40518 SATA150 controller",
119 pdcsata_chip_map,
120 },
121 { PCI_PRODUCT_PROMISE_PDC40519,
122 0,
123 "Promise PDC40519 SATA 150 controller",
124 pdcsata_chip_map,
125 },
126 { PCI_PRODUCT_PROMISE_PDC40718,
127 0,
128 "Promise PDC40718 SATA300 controller",
129 pdcsata_chip_map,
130 },
131 { PCI_PRODUCT_PROMISE_PDC40719,
132 0,
133 "Promise PDC40719 SATA300 controller",
134 pdcsata_chip_map,
135 },
136 { PCI_PRODUCT_PROMISE_PDC40779,
137 0,
138 "Promise PDC40779 SATA300 controller",
139 pdcsata_chip_map,
140 },
141 { PCI_PRODUCT_PROMISE_PDC20571,
142 0,
143 "Promise PDC20571 SATA150 controller",
144 pdcsata_chip_map,
145 },
146 { PCI_PRODUCT_PROMISE_PDC20575,
147 0,
148 "Promise PDC20575 SATA150 controller",
149 pdcsata_chip_map,
150 },
151 { PCI_PRODUCT_PROMISE_PDC20579,
152 0,
153 "Promise PDC20579 SATA150 controller",
154 pdcsata_chip_map,
155 },
156 { PCI_PRODUCT_PROMISE_PDC20771,
157 0,
158 "Promise PDC20771 SATA300 controller",
159 pdcsata_chip_map,
160 },
161 { PCI_PRODUCT_PROMISE_PDC20775,
162 0,
163 "Promise PDC20775 SATA300 controller",
164 pdcsata_chip_map,
165 },
166 { PCI_PRODUCT_PROMISE_PDC20617,
167 0,
168 "Promise PDC2020617 Ultra/133 controller",
169 pdcsata_chip_map,
170 },
171 { PCI_PRODUCT_PROMISE_PDC20618,
172 0,
173 "Promise PDC20618 Ultra/133 controller",
174 pdcsata_chip_map,
175 },
176 { PCI_PRODUCT_PROMISE_PDC20619,
177 0,
178 "Promise PDC20619 Ultra/133 controller",
179 pdcsata_chip_map,
180 },
181 { PCI_PRODUCT_PROMISE_PDC20620,
182 0,
183 "Promise PDC20620 Ultra/133 controller",
184 pdcsata_chip_map,
185 },
186 { PCI_PRODUCT_PROMISE_PDC20621,
187 0,
188 "Promise PDC20621 Ultra/133 controller",
189 pdcsata_chip_map,
190 },
191 { 0,
192 0,
193 NULL,
194 NULL
195 }
196 };
197
198 static int
199 pdcsata_match(device_t parent, cfdata_t match, void *aux)
200 {
201 struct pci_attach_args *pa = aux;
202
203 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) {
204 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products))
205 return (2);
206 }
207 return (0);
208 }
209
210 static void
211 pdcsata_attach(device_t parent, device_t self, void *aux)
212 {
213 struct pci_attach_args *pa = aux;
214 struct pciide_softc *sc = device_private(self);
215
216 sc->sc_wdcdev.sc_atac.atac_dev = self;
217
218 pciide_common_attach(sc, pa,
219 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products));
220 }
221
222 static void
223 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
224 {
225 struct pciide_channel *cp;
226 struct ata_channel *wdc_cp;
227 struct wdc_regs *wdr;
228 int channel, i;
229 bus_size_t dmasize;
230 pci_intr_handle_t intrhandle;
231 const char *intrstr;
232
233 /*
234 * Promise SATA controllers have 3 or 4 channels,
235 * the usual IDE registers are mapped in I/O space, with offsets.
236 */
237 if (pci_intr_map(pa, &intrhandle) != 0) {
238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
239 "couldn't map interrupt\n");
240 return;
241 }
242 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
243 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
244 intrhandle, IPL_BIO, pdcsata_pci_intr, sc);
245
246 if (sc->sc_pci_ih == NULL) {
247 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
248 "couldn't establish native-PCI interrupt");
249 if (intrstr != NULL)
250 aprint_error(" at %s", intrstr);
251 aprint_error("\n");
252 return;
253 }
254 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
255 "interrupting at %s\n",
256 intrstr ? intrstr : "unknown interrupt");
257
258 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
259 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot,
260 &sc->sc_dma_ioh, NULL, &dmasize) == 0);
261 if (!sc->sc_dma_ok) {
262 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
263 "couldn't map bus-master DMA registers\n");
264 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
265 return;
266 }
267
268 sc->sc_dmat = pa->pa_dmat;
269
270 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS,
271 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st,
272 &sc->sc_ba5_sh, NULL, NULL) != 0) {
273 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
274 "couldn't map IDE registers\n");
275 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize);
276 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih);
277 return;
278 }
279
280 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
281 "bus-master DMA support present\n");
282 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
283 if (sc->sc_dma_ok) {
284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
285 }
286 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
287 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
288 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
289 sc->sc_wdcdev.irqack = pdc203xx_irqack;
290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
291 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
293 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel;
294 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
295
296 sc->sc_wdcdev.reset = pdcsata_do_reset;
297
298 switch (sc->sc_pp->ide_product) {
299 case PCI_PRODUCT_PROMISE_PDC20318:
300 case PCI_PRODUCT_PROMISE_PDC20319:
301 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c,
302 0x00ff0033);
303 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
304 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_SATA_NCHANNELS;
305 break;
306 case PCI_PRODUCT_PROMISE_PDC20371:
307 case PCI_PRODUCT_PROMISE_PDC20375:
308 case PCI_PRODUCT_PROMISE_PDC20376:
309 case PCI_PRODUCT_PROMISE_PDC20377:
310 case PCI_PRODUCT_PROMISE_PDC20378:
311 case PCI_PRODUCT_PROMISE_PDC20379:
312 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c,
313 0x00ff0033);
314 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe;
315 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC203xx_COMBO_NCHANNELS;
316 break;
317
318 case PCI_PRODUCT_PROMISE_PDC40518:
319 case PCI_PRODUCT_PROMISE_PDC40519:
320 case PCI_PRODUCT_PROMISE_PDC40718:
321 case PCI_PRODUCT_PROMISE_PDC40719:
322 case PCI_PRODUCT_PROMISE_PDC40779:
323 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60,
324 0x00ff00ff);
325 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_SATA_NCHANNELS;
326 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
327 break;
328
329 case PCI_PRODUCT_PROMISE_PDC20571:
330 case PCI_PRODUCT_PROMISE_PDC20575:
331 case PCI_PRODUCT_PROMISE_PDC20579:
332 case PCI_PRODUCT_PROMISE_PDC20771:
333 case PCI_PRODUCT_PROMISE_PDC20775:
334 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60,
335 0x00ff00ff);
336 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_COMBO_NCHANNELS;
337 sc->sc_wdcdev.sc_atac.atac_probe = pdc203xx_combo_probe;
338 break;
339
340 case PCI_PRODUCT_PROMISE_PDC20617:
341 case PCI_PRODUCT_PROMISE_PDC20618:
342 case PCI_PRODUCT_PROMISE_PDC20619:
343 case PCI_PRODUCT_PROMISE_PDC20620:
344 case PCI_PRODUCT_PROMISE_PDC20621:
345 sc->sc_wdcdev.sc_atac.atac_nchannels =
346 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh,
347 0x48) & 0x01) ? 1 : 0) +
348 ((bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh,
349 0x48) & 0x02) ? 1 : 0) +
350 2;
351 sc->sc_wdcdev.sc_atac.atac_probe = wdc_drvprobe;
352
353 default:
354 aprint_error("unknown promise product 0x%x\n",
355 sc->sc_pp->ide_product);
356 }
357
358 wdc_allocate_regs(&sc->sc_wdcdev);
359
360 sc->sc_wdcdev.dma_arg = sc;
361 sc->sc_wdcdev.dma_init = pdc203xx_dma_init;
362 sc->sc_wdcdev.dma_start = pdc203xx_dma_start;
363 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish;
364
365 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
366 channel++) {
367 cp = &sc->pciide_channels[channel];
368 sc->wdc_chanarray[channel] = &cp->ata_channel;
369
370 cp->ih = sc->sc_pci_ih;
371 cp->name = NULL;
372 cp->ata_channel.ch_channel = channel;
373 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
374 cp->ata_channel.ch_queue =
375 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
376 cp->ata_channel.ch_ndrive = 2;
377 if (cp->ata_channel.ch_queue == NULL) {
378 aprint_error("%s channel %d: "
379 "can't allocate memory for command queue\n",
380 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
381 channel);
382 goto next_channel;
383 }
384 wdc_cp = &cp->ata_channel;
385 wdr = CHAN_TO_WDC_REGS(wdc_cp);
386
387 wdr->ctl_iot = sc->sc_ba5_st;
388 wdr->cmd_iot = sc->sc_ba5_st;
389
390 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
391 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) {
392 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
393 "couldn't map channel %d ctl regs\n", channel);
394 goto next_channel;
395 }
396 for (i = 0; i < WDC_NREG; i++) {
397 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
398 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1,
399 &wdr->cmd_iohs[i]) != 0) {
400 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
401 "couldn't map channel %d cmd regs\n",
402 channel);
403 goto next_channel;
404 }
405 }
406 wdc_init_shadow_regs(wdc_cp);
407
408 /*
409 * subregion de busmaster registers. They're spread all over
410 * the controller's register space :(. They are also 4 bytes
411 * sized, with some specific extentions in the extra bits.
412 * It also seems that the IDEDMA_CTL register isn't available.
413 */
414 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
415 0x260 + (channel << 7), 1,
416 &cp->dma_iohs[IDEDMA_CMD]) != 0) {
417 aprint_normal("%s channel %d: can't subregion DMA "
418 "registers\n",
419 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
420 channel);
421 goto next_channel;
422 }
423 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
424 0x244 + (channel << 7), 4,
425 &cp->dma_iohs[IDEDMA_TBL]) != 0) {
426 aprint_normal("%s channel %d: can't subregion DMA "
427 "registers\n",
428 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
429 channel);
430 goto next_channel;
431 }
432
433 /* subregion the SATA registers */
434 if (sc->sc_wdcdev.sc_atac.atac_probe == wdc_sataprobe ||
435 (sc->sc_wdcdev.sc_atac.atac_probe == pdc203xx_combo_probe
436 && channel < 2)) {
437 wdr->sata_iot = sc->sc_ba5_st;
438 wdr->sata_baseioh = sc->sc_ba5_sh;
439 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
440 PDC205_SSTATUS(channel), 1,
441 &wdr->sata_status) != 0) {
442 aprint_error_dev(
443 sc->sc_wdcdev.sc_atac.atac_dev,
444 "couldn't map channel %d "
445 "sata_status regs\n", channel);
446 goto next_channel;
447 }
448 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
449 PDC205_SERROR(channel), 1, &wdr->sata_error) != 0) {
450 aprint_error_dev(
451 sc->sc_wdcdev.sc_atac.atac_dev,
452 "couldn't map channel %d "
453 "sata_error regs\n", channel);
454 goto next_channel;
455 }
456 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
457 PDC205_SCONTROL(channel), 1,
458 &wdr->sata_control) != 0) {
459 aprint_error_dev(
460 sc->sc_wdcdev.sc_atac.atac_dev,
461 "couldn't map channel %d "
462 "sata_control regs\n", channel);
463 goto next_channel;
464 }
465 }
466
467 wdcattach(wdc_cp);
468 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
469 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
470 0) & ~0x00003f9f) | (channel + 1));
471 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
472 (channel + 1) << 2, 0x00000001);
473 next_channel:
474 continue;
475 }
476 return;
477 }
478
479 static void
480 pdc203xx_combo_probe(struct ata_channel *chp)
481 {
482 if (chp->ch_channel < 2)
483 wdc_sataprobe(chp);
484 else
485 wdc_drvprobe(chp);
486 }
487
488 static void
489 pdc203xx_setup_channel(struct ata_channel *chp)
490 {
491 struct ata_drive_datas *drvp;
492 int drive, s;
493 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
494
495 pciide_channel_dma_setup(cp);
496
497 for (drive = 0; drive < 2; drive++) {
498 drvp = &chp->ch_drive[drive];
499 if ((drvp->drive_flags & DRIVE) == 0)
500 continue;
501 if (drvp->drive_flags & DRIVE_UDMA) {
502 s = splbio();
503 drvp->drive_flags &= ~DRIVE_DMA;
504 splx(s);
505 }
506 }
507 }
508
509 static int
510 pdcsata_pci_intr(void *arg)
511 {
512 struct pciide_softc *sc = arg;
513 struct pciide_channel *cp;
514 struct ata_channel *wdc_cp;
515 int i, rv, crv;
516 u_int32_t scr, status, chanbase;
517
518 rv = 0;
519 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40);
520 if (scr == 0xffffffff) return(rv);
521 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff);
522 scr = scr & 0x0000ffff;
523 if (!scr) return(rv);
524
525 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
526 cp = &sc->pciide_channels[i];
527 wdc_cp = &cp->ata_channel;
528 if (scr & (1 << (i + 1))) {
529 chanbase = PDC_CHANNELBASE(i) + 0x48;
530 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
531 if (status & PDC_ERRMASK) {
532 chanbase = PDC_CHANNELBASE(i) + 0x60;
533 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
534 status |= 0x800;
535 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
536 status &= ~0x800;
537 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
538 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
539 continue;
540 }
541 crv = wdcintr(wdc_cp);
542 if (crv == 0) {
543 aprint_error("%s:%d: bogus intr (reg 0x%x)\n",
544 device_xname(
545 sc->sc_wdcdev.sc_atac.atac_dev), i, scr);
546 } else
547 rv = 1;
548 }
549 }
550 return rv;
551 }
552
553 static void
554 pdc203xx_irqack(struct ata_channel *chp)
555 {
556 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
557 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
558
559 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
560 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
561 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1));
562 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
563 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001);
564 }
565
566 static int
567 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf,
568 size_t datalen, int flags)
569 {
570 struct pciide_softc *sc = v;
571
572 return pciide_dma_dmamap_setup(sc, channel, drive,
573 databuf, datalen, flags);
574 }
575
576 static void
577 pdc203xx_dma_start(void *v, int channel, int drive)
578 {
579 struct pciide_softc *sc = v;
580 struct pciide_channel *cp = &sc->pciide_channels[channel];
581 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
582
583 /* Write table addr */
584 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0,
585 dma_maps->dmamap_table->dm_segs[0].ds_addr);
586 /* start DMA engine */
587 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
588 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
589 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0));
590 }
591
592 static int
593 pdc203xx_dma_finish(void *v, int channel, int drive, int force)
594 {
595 struct pciide_softc *sc = v;
596 struct pciide_channel *cp = &sc->pciide_channels[channel];
597 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
598
599 /* stop DMA channel */
600 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
601 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD],
602 0) & ~0x80));
603
604 /* Unload the map of the data buffer */
605 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
606 dma_maps->dmamap_xfer->dm_mapsize,
607 (dma_maps->dma_flags & WDC_DMA_READ) ?
608 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
609 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
610
611 return 0;
612 }
613
614
615 static void
616 pdcsata_do_reset(struct ata_channel *chp, int poll)
617 {
618 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
619 int reset, status, i, chanbase;
620
621 /* reset SATA */
622 reset = (1 << 11);
623 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60;
624 for (i = 0; i < 11;i ++) {
625 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
626 if (status & reset) break;
627 delay(100);
628 status |= reset;
629 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
630 }
631 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
632 status &= ~reset;
633 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status);
634 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase);
635
636 wdc_do_reset(chp, poll);
637 }
NetBSD on the FriendlyARM MINI2440